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Searched refs:vsc (Results 1 – 25 of 32) sorted by relevance

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/drivers/net/dsa/
Dvitesse-vsc73xx-core.c376 static int vsc73xx_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, in vsc73xx_read() argument
379 return vsc->ops->read(vsc, block, subblock, reg, val); in vsc73xx_read()
382 static int vsc73xx_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, in vsc73xx_write() argument
385 return vsc->ops->write(vsc, block, subblock, reg, val); in vsc73xx_write()
388 static int vsc73xx_update_bits(struct vsc73xx *vsc, u8 block, u8 subblock, in vsc73xx_update_bits() argument
395 ret = vsc73xx_read(vsc, block, subblock, reg, &orig); in vsc73xx_update_bits()
400 return vsc73xx_write(vsc, block, subblock, reg, tmp); in vsc73xx_update_bits()
403 static int vsc73xx_detect(struct vsc73xx *vsc) in vsc73xx_detect() argument
412 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0, in vsc73xx_detect()
415 dev_err(vsc->dev, "unable to read mailbox (%d)\n", ret); in vsc73xx_detect()
[all …]
Dvitesse-vsc73xx-platform.c37 struct vsc73xx vsc; member
55 static int vsc73xx_platform_read(struct vsc73xx *vsc, u8 block, u8 subblock, in vsc73xx_platform_read() argument
58 struct vsc73xx_platform *vsc_platform = vsc->priv; in vsc73xx_platform_read()
73 static int vsc73xx_platform_write(struct vsc73xx *vsc, u8 block, u8 subblock, in vsc73xx_platform_write() argument
76 struct vsc73xx_platform *vsc_platform = vsc->priv; in vsc73xx_platform_write()
101 vsc_platform->vsc.dev = dev; in vsc73xx_platform_probe()
102 vsc_platform->vsc.priv = vsc_platform; in vsc73xx_platform_probe()
103 vsc_platform->vsc.ops = &vsc73xx_platform_ops; in vsc73xx_platform_probe()
120 return vsc73xx_probe(&vsc_platform->vsc); in vsc73xx_platform_probe()
127 return vsc73xx_remove(&vsc_platform->vsc); in vsc73xx_platform_remove()
Dvitesse-vsc73xx-spi.c35 struct vsc73xx vsc; member
52 static int vsc73xx_spi_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, in vsc73xx_spi_read() argument
55 struct vsc73xx_spi *vsc_spi = vsc->priv; in vsc73xx_spi_read()
94 static int vsc73xx_spi_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg, in vsc73xx_spi_write() argument
97 struct vsc73xx_spi *vsc_spi = vsc->priv; in vsc73xx_spi_write()
146 vsc_spi->vsc.dev = dev; in vsc73xx_spi_probe()
147 vsc_spi->vsc.priv = vsc_spi; in vsc73xx_spi_probe()
148 vsc_spi->vsc.ops = &vsc73xx_spi_ops; in vsc73xx_spi_probe()
159 return vsc73xx_probe(&vsc_spi->vsc); in vsc73xx_spi_probe()
166 return vsc73xx_remove(&vsc_spi->vsc); in vsc73xx_spi_remove()
Dvitesse-vsc73xx.h21 int (*read)(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
23 int (*write)(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
28 int vsc73xx_probe(struct vsc73xx *vsc);
29 int vsc73xx_remove(struct vsc73xx *vsc);
/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_reg.c1040 struct dp_sdp *vsc, bool blocking) in analogix_dp_send_psr_spd() argument
1056 writel(vsc->sdp_header.HB0, dp->reg_base + ANALOGIX_DP_SPD_HB0); in analogix_dp_send_psr_spd()
1057 writel(vsc->sdp_header.HB1, dp->reg_base + ANALOGIX_DP_SPD_HB1); in analogix_dp_send_psr_spd()
1058 writel(vsc->sdp_header.HB2, dp->reg_base + ANALOGIX_DP_SPD_HB2); in analogix_dp_send_psr_spd()
1059 writel(vsc->sdp_header.HB3, dp->reg_base + ANALOGIX_DP_SPD_HB3); in analogix_dp_send_psr_spd()
1068 writel(vsc->db[0], dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB0); in analogix_dp_send_psr_spd()
1069 writel(vsc->db[1], dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB1); in analogix_dp_send_psr_spd()
1091 ((vsc->db[1] && psr_status == DP_PSR_SINK_ACTIVE_RFB) || in analogix_dp_send_psr_spd()
1092 (!vsc->db[1] && psr_status == DP_PSR_SINK_INACTIVE)), 1500, in analogix_dp_send_psr_spd()
Danalogix_dp_core.h255 struct dp_sdp *vsc, bool blocking);
/drivers/lightnvm/
Dpblk-core.c182 le32_add_cpu(line->vsc, -1); in __pblk_map_invalidate()
412 int packed_meta = (le32_to_cpu(*line->vsc) / pblk->min_write_pgs_data) in pblk_line_gc_list()
414 int vsc = le32_to_cpu(*line->vsc) + packed_meta; in pblk_line_gc_list() local
424 } else if (!vsc) { in pblk_line_gc_list()
429 } else if (vsc < lm->high_thrs) { in pblk_line_gc_list()
434 } else if (vsc < lm->mid_thrs) { in pblk_line_gc_list()
439 } else if (vsc < line->sec_in_line) { in pblk_line_gc_list()
444 } else if (vsc == line->sec_in_line) { in pblk_line_gc_list()
457 line->id, vsc, in pblk_line_gc_list()
1114 *line->vsc = cpu_to_le32(line->sec_in_line); in pblk_line_init_bb()
[all …]
Dpblk-sysfs.c180 int msecs = 0, cur_sec = 0, vsc = 0, sec_in_line = 0; in pblk_sysfs_lines() local
262 vsc = le32_to_cpu(*l_mg->data_line->vsc); in pblk_sysfs_lines()
302 cur_data, cur_sec, msecs, vsc, sec_in_line, in pblk_sysfs_lines()
Dpblk-gc.c381 line_vsc = le32_to_cpu(*line->vsc); in pblk_gc_get_victim_line()
384 victim_vsc = le32_to_cpu(*victim->vsc); in pblk_gc_get_victim_line()
Dpblk.h472 __le32 *vsc; /* Valid sector count in line */ member
957 return le32_to_cpu(*line->vsc); in pblk_line_vsc()
/drivers/gpu/drm/amd/display/dc/inc/hw/
Dstream_encoder.h85 struct dc_info_packet vsc; member
/drivers/gpu/drm/amd/amdgpu/
Ddce_v8_0.c633 fixed20_12 vsc; /* vertical scale ratio */ member
804 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v8_0_average_bandwidth()
839 if ((wm->vsc.full > a.full) || in dce_v8_0_latency_watermark()
840 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v8_0_latency_watermark()
842 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce_v8_0_latency_watermark()
927 if (wm->vsc.full > a.full) in dce_v8_0_check_latency_hiding()
991 wm_high.vsc = amdgpu_crtc->vsc; in dce_v8_0_program_watermarks()
1030 wm_low.vsc = amdgpu_crtc->vsc; in dce_v8_0_program_watermarks()
Ddce_v6_0.c497 fixed20_12 vsc; /* vertical scale ratio */ member
668 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v6_0_average_bandwidth()
703 if ((wm->vsc.full > a.full) || in dce_v6_0_latency_watermark()
704 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v6_0_latency_watermark()
706 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce_v6_0_latency_watermark()
791 if (wm->vsc.full > a.full) in dce_v6_0_check_latency_hiding()
864 wm_high.vsc = amdgpu_crtc->vsc; in dce_v6_0_program_watermarks()
891 wm_low.vsc = amdgpu_crtc->vsc; in dce_v6_0_program_watermarks()
Ddce_v11_0.c724 fixed20_12 vsc; /* vertical scale ratio */ member
895 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v11_0_average_bandwidth()
930 if ((wm->vsc.full > a.full) || in dce_v11_0_latency_watermark()
931 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v11_0_latency_watermark()
933 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce_v11_0_latency_watermark()
1018 if (wm->vsc.full > a.full) in dce_v11_0_check_latency_hiding()
1082 wm_high.vsc = amdgpu_crtc->vsc; in dce_v11_0_program_watermarks()
1121 wm_low.vsc = amdgpu_crtc->vsc; in dce_v11_0_program_watermarks()
Ddce_v10_0.c698 fixed20_12 vsc; /* vertical scale ratio */ member
869 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce_v10_0_average_bandwidth()
904 if ((wm->vsc.full > a.full) || in dce_v10_0_latency_watermark()
905 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce_v10_0_latency_watermark()
907 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce_v10_0_latency_watermark()
992 if (wm->vsc.full > a.full) in dce_v10_0_check_latency_hiding()
1056 wm_high.vsc = amdgpu_crtc->vsc; in dce_v10_0_program_watermarks()
1095 wm_low.vsc = amdgpu_crtc->vsc; in dce_v10_0_program_watermarks()
Damdgpu_display.c746 amdgpu_crtc->vsc.full = dfixed_div(a, b); in amdgpu_display_crtc_scaling_mode_fixup()
751 amdgpu_crtc->vsc.full = dfixed_const(1); in amdgpu_display_crtc_scaling_mode_fixup()
Damdgpu_mode.h399 fixed20_12 vsc; member
/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_stream_encoder.c714 if (info_frame->vsc.valid) in enc1_stream_encoder_update_dp_info_packets()
718 &info_frame->vsc); in enc1_stream_encoder_update_dp_info_packets()
739 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); in enc1_stream_encoder_update_dp_info_packets()
/drivers/gpu/drm/radeon/
Drs690.c305 if (crtc->vsc.full > dfixed_const(2)) in rs690_crtc_bandwidth_compute()
333 if (crtc->vsc.full > b.full) in rs690_crtc_bandwidth_compute()
334 b.full = crtc->vsc.full; in rs690_crtc_bandwidth_compute()
Devergreen.c1940 fixed20_12 vsc; /* vertical scale ratio */ member
2055 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in evergreen_average_bandwidth()
2080 if ((wm->vsc.full > a.full) || in evergreen_latency_watermark()
2081 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in evergreen_latency_watermark()
2083 ((wm->vsc.full >= a.full) && wm->interlaced)) in evergreen_latency_watermark()
2135 if (wm->vsc.full > a.full) in evergreen_check_latency_hiding()
2197 wm_high.vsc = radeon_crtc->vsc; in evergreen_program_watermarks()
2224 wm_low.vsc = radeon_crtc->vsc; in evergreen_program_watermarks()
Drv515.c985 if (crtc->vsc.full > dfixed_const(2)) in rv515_crtc_bandwidth_compute()
1013 if (crtc->vsc.full > b.full) in rv515_crtc_bandwidth_compute()
1014 b.full = crtc->vsc.full; in rv515_crtc_bandwidth_compute()
Dsi.c2066 fixed20_12 vsc; /* vertical scale ratio */ member
2198 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce6_average_bandwidth()
2224 if ((wm->vsc.full > a.full) || in dce6_latency_watermark()
2225 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce6_latency_watermark()
2227 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce6_latency_watermark()
2281 if (wm->vsc.full > a.full) in dce6_check_latency_hiding()
2346 wm_high.vsc = radeon_crtc->vsc; in dce6_program_watermarks()
2373 wm_low.vsc = radeon_crtc->vsc; in dce6_program_watermarks()
Dcik.c8928 fixed20_12 vsc; /* vertical scale ratio */ member
9099 bandwidth.full = dfixed_mul(bandwidth, wm->vsc); in dce8_average_bandwidth()
9134 if ((wm->vsc.full > a.full) || in dce8_latency_watermark()
9135 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || in dce8_latency_watermark()
9137 ((wm->vsc.full >= a.full) && wm->interlaced)) in dce8_latency_watermark()
9222 if (wm->vsc.full > a.full) in dce8_check_latency_hiding()
9287 wm_high.vsc = radeon_crtc->vsc; in dce8_program_watermarks()
9327 wm_low.vsc = radeon_crtc->vsc; in dce8_program_watermarks()
/drivers/gpu/drm/amd/display/dc/dce/
Ddce_stream_encoder.c856 if (info_frame->vsc.valid) in dce110_stream_encoder_update_dp_info_packets()
860 &info_frame->vsc); in dce110_stream_encoder_update_dp_info_packets()
877 REG_UPDATE(DP_SEC_CNTL, DP_SEC_GSP0_ENABLE, info_frame->vsc.valid); in dce110_stream_encoder_update_dp_info_packets()
/drivers/video/fbdev/
Dcg14.c123 u16 vsc; /* Vert Sync Clear */ member

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