| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_optc.c | 63 int vstartup_start, in optc1_program_global_sync() argument
70 optc1->vstartup_start = vstartup_start; in optc1_program_global_sync()
74 if (optc1->vstartup_start == 0) { in optc1_program_global_sync()
80 VSTARTUP_START, optc1->vstartup_start); in optc1_program_global_sync()
143 int vstartup_start, in optc1_program_timing() argument
163 optc1->vstartup_start = vstartup_start; in optc1_program_timing()
271 vstartup_start, in optc1_program_timing()
319 vertical_line_start = asic_blank_end - optc1->vstartup_start + 1; in optc1_set_vtg_params()
327 if ((optc1->vstartup_start/2)*2 > asic_blank_end) in optc1_set_vtg_params()
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| D | dcn10_optc.h | 517 int vstartup_start; member
562 int vstartup_start,
582 int vstartup_start,
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| D | dcn10_hw_sequencer.c | 766 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn10_enable_stream_timing()
2508 pipe_ctx->pipe_dlg_param.vstartup_start, in program_all_pipe_in_tree()
3099 pipe_ctx->pipe_dlg_param.vstartup_start + 1; in get_vupdate_offset_from_vsync()
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| D | dcn10_hubp.c | 131 if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width in hubp1_vready_workaround()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | display_rq_dlg_calc_20v2.c | 854 unsigned int vstartup_start; in dml20v2_rq_dlg_get_dlg_params() local
1024 vstartup_start = dst->vstartup_start; in dml20v2_rq_dlg_get_dlg_params()
1026 if (vstartup_start / 2.0 in dml20v2_rq_dlg_get_dlg_params()
1033 if (vstartup_start in dml20v2_rq_dlg_get_dlg_params()
1043 vstartup_start = vstartup_start / 2; in dml20v2_rq_dlg_get_dlg_params()
1046 if (vstartup_start >= min_vblank) { in dml20v2_rq_dlg_get_dlg_params()
1053 vstartup_start, in dml20v2_rq_dlg_get_dlg_params()
1055 min_vblank = vstartup_start + 1; in dml20v2_rq_dlg_get_dlg_params()
1058 vstartup_start, in dml20v2_rq_dlg_get_dlg_params()
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| D | display_rq_dlg_calc_20.c | 854 unsigned int vstartup_start; in dml20_rq_dlg_get_dlg_params() local
1024 vstartup_start = dst->vstartup_start; in dml20_rq_dlg_get_dlg_params()
1026 if (vstartup_start / 2.0 in dml20_rq_dlg_get_dlg_params()
1033 if (vstartup_start in dml20_rq_dlg_get_dlg_params()
1043 vstartup_start = vstartup_start / 2; in dml20_rq_dlg_get_dlg_params()
1046 if (vstartup_start >= min_vblank) { in dml20_rq_dlg_get_dlg_params()
1053 vstartup_start, in dml20_rq_dlg_get_dlg_params()
1055 min_vblank = vstartup_start + 1; in dml20_rq_dlg_get_dlg_params()
1058 vstartup_start, in dml20_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| D | display_rq_dlg_calc_21.c | 901 unsigned int vstartup_start; in dml_rq_dlg_get_dlg_params() local
1064 vstartup_start = dst->vstartup_start; in dml_rq_dlg_get_dlg_params()
1066 if (vstartup_start / 2.0 in dml_rq_dlg_get_dlg_params()
1073 if (vstartup_start in dml_rq_dlg_get_dlg_params()
1083 vstartup_start = vstartup_start / 2; in dml_rq_dlg_get_dlg_params()
1086 if (vstartup_start >= min_vblank) { in dml_rq_dlg_get_dlg_params()
1095 vstartup_start, in dml_rq_dlg_get_dlg_params()
1097 min_vblank = vstartup_start + 1; in dml_rq_dlg_get_dlg_params()
1101 vstartup_start, in dml_rq_dlg_get_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| D | dml1_display_rq_dlg_calc.c | 1049 unsigned int vstartup_start; in dml1_rq_dlg_get_dlg_params() local
1234 vstartup_start = e2e_pipe_param.pipe.dest.vstartup_start; in dml1_rq_dlg_get_dlg_params()
1237 vstartup_start = vstartup_start / 2; in dml1_rq_dlg_get_dlg_params()
1239 if (vstartup_start >= min_vblank) { in dml1_rq_dlg_get_dlg_params()
1248 vstartup_start, in dml1_rq_dlg_get_dlg_params()
1250 min_vblank = vstartup_start + 1; in dml1_rq_dlg_get_dlg_params()
1254 vstartup_start, in dml1_rq_dlg_get_dlg_params()
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| D | display_mode_structs.h | 316 unsigned int vstartup_start; member
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | timing_generator.h | 142 int vstartup_start,
223 int vstartup_start,
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| /drivers/gpu/drm/amd/display/dc/dce110/ |
| D | dce110_timing_generator.h | 260 int vstartup_start,
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| D | dce110_timing_generator_v.c | 439 int vstartup_start, in dce110_timing_generator_v_program_timing() argument
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| D | dce110_timing_generator.c | 1956 int vstartup_start, in dce110_tg_program_timing() argument
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| /drivers/gpu/drm/amd/display/dc/dce80/ |
| D | dce80_timing_generator.c | 111 int vstartup_start, in program_timing() argument
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 434 input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start; in pipe_ctx_to_e2e_pipe_params()
1184 pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; in dcn_validate_bandwidth()
1225 hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx]; in dcn_validate_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hwseq.c | 573 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn20_enable_stream_timing()
1043 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn20_program_all_pipe_in_tree()
1335 pipe_ctx->pipe_dlg_param.vstartup_start, in dcn20_update_bandwidth()
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| D | dcn20_hubp.c | 182 if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width in hubp2_vready_at_or_After_vsync()
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| D | dcn20_resource.c | 2659 dst->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit]; in dcn20_calculate_dlg_params()
2674 dst_j->vstartup_start = context->bw_ctx.dml.vba.VStartup[pipe_idx_unsplit]; in dcn20_calculate_dlg_params()
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| /drivers/gpu/drm/amd/display/dc/dce120/ |
| D | dce120_timing_generator.c | 740 int vstartup_start, in dce120_tg_program_timing() argument
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