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Searched refs:wait_for (Results 1 – 25 of 34) sorted by relevance

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/drivers/mmc/host/
Dsh_mmcif.c234 enum sh_mmcif_wait_for wait_for; member
584 host->state, host->wait_for); in sh_mmcif_error_manage()
588 host->state, host->wait_for); in sh_mmcif_error_manage()
592 host->state, host->wait_for); in sh_mmcif_error_manage()
624 host->wait_for = MMCIF_WAIT_FOR_READ; in sh_mmcif_single_read()
648 host->wait_for = MMCIF_WAIT_FOR_READ_END; in sh_mmcif_read_block()
664 host->wait_for = MMCIF_WAIT_FOR_MREAD; in sh_mmcif_multi_read()
704 host->wait_for = MMCIF_WAIT_FOR_WRITE; in sh_mmcif_single_write()
728 host->wait_for = MMCIF_WAIT_FOR_WRITE_END; in sh_mmcif_write_block()
744 host->wait_for = MMCIF_WAIT_FOR_MWRITE; in sh_mmcif_multi_write()
[all …]
/drivers/gpu/drm/v3d/
Dv3d_mmu.c40 ret = wait_for(!(V3D_READ(V3D_MMU_CTL) & in v3d_mmu_flush_all()
52 ret = wait_for(!(V3D_READ(V3D_MMU_CTL) & in v3d_mmu_flush_all()
59 ret = wait_for(!(V3D_READ(V3D_MMUC_CONTROL) & in v3d_mmu_flush_all()
Dv3d_gem.c52 if (wait_for((V3D_CORE_READ(core, V3D_GMP_STATUS) & in v3d_idle_axi()
68 if (wait_for((V3D_GCA_READ(V3D_GCA_SAFE_SHUTDOWN_ACK) & in v3d_idle_gca()
197 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & in v3d_clean_caches()
207 if (wait_for(!(V3D_CORE_READ(core, V3D_CTL_L2TCACTL) & in v3d_clean_caches()
Dv3d_drv.h264 #define wait_for(COND, MS) ({ \ macro
/drivers/gpu/drm/gma500/
Dintel_gmbus.c52 #define wait_for(COND, MS) _wait_for(COND, MS, 1) macro
279 if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & in gmbus_xfer()
308 if (wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & in gmbus_xfer()
325 …if (i + 1 < num && wait_for(GMBUS_REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PH… in gmbus_xfer()
Dcdv_intel_display.c126 #define wait_for(COND, MS) _wait_for(COND, MS, 1) macro
133 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
145 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_read()
168 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
181 ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000); in cdv_sb_write()
Dcdv_intel_dp.c249 #define wait_for(COND, MS) _wait_for(COND, MS, 1) macro
431 if (wait_for(((REG_READ(PP_STATUS) & idle_on_mask) == idle_on_mask), 1000)) { in cdv_intel_edp_panel_on()
465 if (wait_for((REG_READ(PP_STATUS) & idle_off_mask) == 0, 1000)) { in cdv_intel_edp_panel_off()
/drivers/gpu/drm/i915/gt/uc/
Dintel_guc_fw.c104 ret = wait_for(guc_ready(uncore, &status), 100); in guc_wait_ucode()
Dselftest_guc.c69 err = wait_for(READ_ONCE(desc->head) == READ_ONCE(desc->tail), 10); in ring_doorbell_nop()
Dintel_guc_ct.c387 err = wait_for(done, 10); in wait_for_ctb_desc_update()
433 err = wait_for(done, 10); in wait_for_ct_request_update()
/drivers/gpu/drm/vc4/
Dvc4_hdmi.c325 return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & in vc4_hdmi_stop_packet()
371 ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & in vc4_hdmi_write_infoframe()
628 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & in vc4_hdmi_encoder_enable()
640 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & in vc4_hdmi_encoder_enable()
673 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) & in vc4_hdmi_encoder_enable()
Dvc4_drv.h705 #define wait_for(COND, MS) _wait_for(COND, MS, 1) macro
Dvc4_dsi.c702 ret = wait_for((DSI_PORT_READ(STAT) & stat_ulps) == stat_ulps, 200); in vc4_dsi_ulps()
721 ret = wait_for((DSI_PORT_READ(STAT) & stat_stop) == stat_stop, 200); in vc4_dsi_ulps()
/drivers/gpu/drm/i915/selftests/
Digt_spinner.c200 wait_for(i915_seqno_passed(hws_seqno(spin, rq), in igt_wait_for_spinner()
Dintel_uncore.c241 if (wait_for(readl(reg) == 0, 100)) { in live_forcewake_ops()
/drivers/gpu/drm/i915/display/
Dintel_cdclk.c562 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in vlv_set_cdclk()
580 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & in vlv_set_cdclk()
644 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & in chv_set_cdclk()
1597 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) == 0, 1)) in cnl_cdclk_pll_disable()
1615 if (wait_for((I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK) != 0, 1)) in cnl_cdclk_pll_enable()
Dintel_lspcon.c131 wait_for((current_mode = lspcon_get_current_mode(lspcon)) == mode, 400); in lspcon_wait_mode()
Dintel_tc.c225 if (enable && wait_for(!icl_tc_phy_status_complete(dig_port), 10)) in icl_tc_phy_set_safe_mode()
Dvlv_dsi_pll.c168 if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) & in vlv_dsi_pll_enable()
Dintel_hdcp.c664 if (wait_for(I915_READ(PORT_HDCP_STATUS(port)) & in intel_hdcp_auth()
695 if (!wait_for(I915_READ(PORT_HDCP_STATUS(port)) & in intel_hdcp_auth()
Dintel_gmbus.c345 ret = wait_for((gmbus2 = I915_READ_FW(GMBUS2)) & status, 50); in gmbus_wait()
Dintel_opregion.c337 if (wait_for(C, dslp)) { in swsci()
/drivers/scsi/
Dscsi_lib.c680 unsigned long wait_for = (cmd->allowed + 1) * req->timeout; in scsi_io_completion_action() local
786 time_before(cmd->jiffies_at_alloc + wait_for, jiffies)) in scsi_io_completion_action()
1455 unsigned long wait_for = (cmd->allowed + 1) * rq->timeout; in scsi_softirq_done() local
1466 time_before(cmd->jiffies_at_alloc + wait_for, jiffies)) { in scsi_softirq_done()
1469 wait_for/HZ); in scsi_softirq_done()
/drivers/gpu/drm/i915/
Di915_utils.h325 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) macro
/drivers/gpu/drm/i915/gt/
Dselftest_hangcheck.c296 wait_for(i915_seqno_passed(hws_seqno(h, rq), in wait_until_running()
365 return wait_for(intel_engine_is_idle(engine), IGT_IDLE_TIMEOUT) == 0; in wait_for_idle()
1290 if (wait_for(!list_empty(&rq->fence.cb_list), 10)) { in __igt_reset_evict_vma()

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