| /drivers/gpu/drm/amd/display/dc/dcn21/ |
| D | dcn21_hubbub.c | 135 struct dcn_watermark_set *watermarks, in hubbub21_program_urgent_watermarks() argument
144 if (safe_to_lower || watermarks->a.urgent_ns > hubbub1->watermarks.a.urgent_ns) { in hubbub21_program_urgent_watermarks()
145 hubbub1->watermarks.a.urgent_ns = watermarks->a.urgent_ns; in hubbub21_program_urgent_watermarks()
146 prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns, in hubbub21_program_urgent_watermarks()
154 watermarks->a.urgent_ns, prog_wm_value); in hubbub21_program_urgent_watermarks()
158 if (safe_to_lower || watermarks->a.frac_urg_bw_flip in hubbub21_program_urgent_watermarks()
159 > hubbub1->watermarks.a.frac_urg_bw_flip) { in hubbub21_program_urgent_watermarks()
160 hubbub1->watermarks.a.frac_urg_bw_flip = watermarks->a.frac_urg_bw_flip; in hubbub21_program_urgent_watermarks()
163 DCHUBBUB_ARB_FRAC_URG_BW_FLIP_A, watermarks->a.frac_urg_bw_flip); in hubbub21_program_urgent_watermarks()
166 if (safe_to_lower || watermarks->a.frac_urg_bw_nom in hubbub21_program_urgent_watermarks()
[all …]
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| D | dcn21_hubbub.h | 119 struct dcn_watermark_set *watermarks,
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| D | dcn21_resource.c | 1039 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d, in dcn21_calculate_wm()
1044 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c, in dcn21_calculate_wm()
1049 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b, in dcn21_calculate_wm()
1055 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a, in dcn21_calculate_wm()
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| /drivers/gpu/drm/amd/display/dc/dcn10/ |
| D | dcn10_hubbub.c | 305 struct dcn_watermark_set *watermarks, in hubbub1_program_urgent_watermarks() argument
314 if (safe_to_lower || watermarks->a.urgent_ns > hubbub1->watermarks.a.urgent_ns) { in hubbub1_program_urgent_watermarks()
315 hubbub1->watermarks.a.urgent_ns = watermarks->a.urgent_ns; in hubbub1_program_urgent_watermarks()
316 prog_wm_value = convert_and_clamp(watermarks->a.urgent_ns, in hubbub1_program_urgent_watermarks()
323 watermarks->a.urgent_ns, prog_wm_value); in hubbub1_program_urgent_watermarks()
326 if (safe_to_lower || watermarks->a.pte_meta_urgent_ns > hubbub1->watermarks.a.pte_meta_urgent_ns) { in hubbub1_program_urgent_watermarks()
327 hubbub1->watermarks.a.pte_meta_urgent_ns = watermarks->a.pte_meta_urgent_ns; in hubbub1_program_urgent_watermarks()
328 prog_wm_value = convert_and_clamp(watermarks->a.pte_meta_urgent_ns, in hubbub1_program_urgent_watermarks()
333 watermarks->a.pte_meta_urgent_ns, prog_wm_value); in hubbub1_program_urgent_watermarks()
337 if (safe_to_lower || watermarks->b.urgent_ns > hubbub1->watermarks.b.urgent_ns) { in hubbub1_program_urgent_watermarks()
[all …]
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| D | dcn10_hubbub.h | 307 struct dcn_watermark_set watermarks; member
321 struct dcn_watermark_set *watermarks,
344 struct dcn_watermark_set *watermarks,
349 struct dcn_watermark_set *watermarks,
354 struct dcn_watermark_set *watermarks,
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| D | dcn10_hw_sequencer.c | 2705 &context->bw_ctx.bw.dcn.watermarks, in dcn10_prepare_bandwidth()
2737 &context->bw_ctx.bw.dcn.watermarks, in dcn10_optimize_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/calcs/ |
| D | dcn_calcs.c | 553 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns =
555 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns =
557 context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns =
559 context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
560 context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = v->urgent_watermark * 1000;
567 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns =
569 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns =
571 context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns =
573 context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = v->ptemeta_urgent_watermark * 1000;
574 context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = v->urgent_watermark * 1000;
[all …]
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| /drivers/gpu/drm/amd/display/dc/dcn20/ |
| D | dcn20_hubbub.c | 564 struct dcn_watermark_set *watermarks, in hubbub2_program_watermarks() argument
573 hubbub1_program_urgent_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); in hubbub2_program_watermarks()
574 hubbub1_program_stutter_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); in hubbub2_program_watermarks()
585 hubbub1_program_pstate_watermarks(hubbub, watermarks, refclk_mhz, safe_to_lower); in hubbub2_program_watermarks()
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| D | dcn20_resource.c | 2585 …context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn20_calculate_wm()
2586 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter… in dcn20_calculate_wm()
2587 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->b… in dcn20_calculate_wm()
2588 …context->bw_ctx.bw.dcn.watermarks.b.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&con… in dcn20_calculate_wm()
2589 …context->bw_ctx.bw.dcn.watermarks.b.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn20_calculate_wm()
2596 …context->bw_ctx.bw.dcn.watermarks.c.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn20_calculate_wm()
2597 …context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter… in dcn20_calculate_wm()
2598 …context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(&context->b… in dcn20_calculate_wm()
2599 …context->bw_ctx.bw.dcn.watermarks.c.cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(&con… in dcn20_calculate_wm()
2600 …context->bw_ctx.bw.dcn.watermarks.c.pte_meta_urgent_ns = get_wm_memory_trip(&context->bw_ctx.dml, … in dcn20_calculate_wm()
[all …]
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| D | dcn20_hubbub.h | 82 struct dcn_watermark_set watermarks; member
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| D | dcn20_hwseq.c | 1286 &context->bw_ctx.bw.dcn.watermarks, in dcn20_prepare_bandwidth()
1299 &context->bw_ctx.bw.dcn.watermarks, in dcn20_optimize_bandwidth()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | dchubbub.h | 143 struct dcn_watermark_set *watermarks,
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| /drivers/gpu/drm/amd/display/dc/inc/ |
| D | core_types.h | 355 struct dcn_watermark_set watermarks; member
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| /drivers/gpu/drm/amd/powerplay/hwmgr/ |
| D | smu_helper.h | 45 struct watermarks { struct
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| D | smu_helper.c | 708 struct watermarks *table = wt_table; in smu_set_watermarks_for_clocks_ranges()
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| /drivers/gpu/drm/amd/powerplay/ |
| D | navi10_ppt.c | 1293 void *watermarks, struct in navi10_set_watermarks_table() argument
1298 Watermarks_t *table = watermarks; in navi10_set_watermarks_table()
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| D | smu_v11_0.c | 1337 struct smu_table *watermarks = &smu->smu_table.tables[SMU_TABLE_WATERMARKS]; in smu_v11_0_set_watermarks_for_clock_ranges() local
1338 void *table = watermarks->cpu_addr; in smu_v11_0_set_watermarks_for_clock_ranges()
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| D | vega20_ppt.c | 3061 void *watermarks, struct in vega20_set_watermarks_table() argument
3066 Watermarks_t *table = watermarks; in vega20_set_watermarks_table()
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| /drivers/gpu/drm/amd/powerplay/inc/ |
| D | amdgpu_smu.h | 451 int (*set_watermarks_table)(struct smu_context *smu, void *watermarks,
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