Home
last modified time | relevance | path

Searched refs:we (Results 1 – 25 of 60) sorted by relevance

123

/drivers/block/paride/
DTransition-notes9 ps_spinlock. C is always preceded by B, since we can't reach it
10 other than through B and we don't drop ps_spinlock between them.
14 A and each B is preceded by either A or C. Moments when we enter
37 * in ps_tq_int(): from the moment when we get ps_spinlock() to the
73 we would have to be called for the PIA that got ->claimed_cont
83 it is holding pd_lock. The only place within the area where we
87 we were acquiring the lock, (1) would be already false, since
89 If it was 0 before we tried to acquire pd_lock, (2) would be
96 (4) is done the same way - all places where we release pi_spinlock within
100 in the area, under pi_spinlock and we do not release it until after leaving
[all …]
/drivers/gpu/drm/i915/
DKconfig.profile5 On runtime suspend, as we suspend the device, we have to revoke
8 the GGTT mmap can be very slow and so we impose a small hysteris
20 we may spend some time polling for its completion. As the IRQ may
21 take a non-negligible time to setup, we do a short spin first to
25 May be 0 to disable the initial spin. In practice, we estimate
/drivers/scsi/aic7xxx/
Daic79xx.seq85 * If we have completions stalled waiting for the qfreeze
109 * ENSELO is cleared by a SELDO, so we must test for SELDO
169 * Since this status did not consume a FIFO, we have to
170 * be a bit more dilligent in how we check for FIFOs pertaining
178 * count in the SCB. In this case, we allow the routine servicing
183 * we detect case 1, we will properly defer the post of the SCB
222 * bad SCSI status (currently only for underruns), we
223 * queue the SCB for normal completion. Otherwise, we
258 * If we have relatively few commands outstanding, don't
303 * one byte of lun information we support.
[all …]
Daic7xxx.seq52 * After starting the selection hardware, we check for reconnecting targets
54 * bus arbitration. The problem with this is that we must keep track of the
55 * SCB that we've already pulled from the QINFIFO and started the selection
56 * on just in case the reselection wins so that we can retry the selection at
104 * We have at least one queued SCB now and we don't have any
124 * before we completed the DMA operation. If it was,
211 /* The Target ID we were selected at */
239 * Watch ATN closely now as we pull in messages from the
285 * we've got a failed selection and must transition to bus
333 * Reselection has been initiated by a target. Make a note that we've been
[all …]
/drivers/staging/wusbcore/Documentation/
Dwusb-design-overview.rst202 So let's say we connect a dongle to the system: it is detected and
205 Now we have a real HWA device connected and
225 So assuming we have devices and we have agreed for a channel to connect
226 on (let's say 9), we put the new RC to beacon:
297 ID and tell the HC to use all that. Then we start it. This means the HC
324 the device. First we allocate a /fake port/ and assign an
325 unauthenticated address (128 to 255--what we really do is
329 So now we are in the reset path -- we know we have a non-yet enumerated
330 device with an unauthorized address; we ask user space to authenticate
331 (FIXME: not yet done, similar to bluetooth pairing), then we do the key
[all …]
Dwusb-cbaf39 Get the device ID associated to the HOST-CHID we sent with
44 If we allow the device to connect, set a random new CDID and CK
46 connect wireless. We save them for that next time also so we can
47 authenticate the device (when we see the CDID he uses to id
/drivers/staging/vc04_services/interface/vchi/
DTODO4 some of the ones we want:
16 to manage these buffers as dmabufs so that we can zero-copy import
23 days. Once we have the set of VCHI-using drivers we want in tree, we
62 Most functions use a custom set of return values, we should force proper Linux
/drivers/bcma/
DREADME2 however from programming point of view there is nothing AMBA specific we use.
11 and PIDs (0x103BB369), but we do not use that info for anything. One of that
17 In this situation we decided to introduce separated bus. It can contain up to
/drivers/gpu/drm/i915/gvt/
Dgtt.c1064 struct intel_vgpu *vgpu, struct intel_gvt_gtt_entry *we) in ppgtt_populate_spt_by_guest_entry() argument
1071 GEM_BUG_ON(!gtt_type_is_pt(get_next_pt_type(we->type))); in ppgtt_populate_spt_by_guest_entry()
1073 if (we->type == GTT_TYPE_PPGTT_PDE_ENTRY) in ppgtt_populate_spt_by_guest_entry()
1074 ips = vgpu_ips_enabled(vgpu) && ops->test_ips(we); in ppgtt_populate_spt_by_guest_entry()
1076 spt = intel_vgpu_find_spt_by_gfn(vgpu, ops->get_pfn(we)); in ppgtt_populate_spt_by_guest_entry()
1092 int type = get_next_pt_type(we->type); in ppgtt_populate_spt_by_guest_entry()
1099 spt = ppgtt_alloc_spt_gfn(vgpu, type, ops->get_pfn(we), ips); in ppgtt_populate_spt_by_guest_entry()
1123 spt, we->val64, we->type); in ppgtt_populate_spt_by_guest_entry()
1387 struct intel_gvt_gtt_entry *we, unsigned long index) in ppgtt_handle_guest_entry_add() argument
1395 we->val64, index); in ppgtt_handle_guest_entry_add()
[all …]
/drivers/gpu/drm/msm/
DNOTES3 In the current snapdragon SoC's, we have (at least) 3 different
21 seems like we can do some clever tricks like use GPU to trigger
44 we'll let msm_mdp4_kms provide the irq install/uninstall/etc functions
56 Unlike MDP4, it appears we can get by with a single encoder, rather
68 logistics of finding/mapping io region, irq, etc. Idealy we would
/drivers/gpio/
DTODO25 following ongoing work as well) we can delete the old global
35 the [devm_]gpiod_get() calls we have today that will implicitly go into
52 lookups for polarity inversion, open drain and what not. As we now
95 Currently we set up the irqchip after setting up the gpiochip
130 When this is done, we will delete the old APIs for instatiating
145 creating pin control as its own subsystem was that we could avoid any
/drivers/scsi/
D53c700.scr41 ; The following represent status interrupts we use 3 hex digits for
119 ; SCSI Messages we interpret in the script
190 ; Use this entry if we've just tried to look at the first byte
269 ; Could be we have nothing more to transfer
351 ; we return here after a reselection
364 ; we return here after a reselection
391 ; we return here after a reselection
D53c700_d.h_shipped44 ; The following represent status interrupts we use 3 hex digits for
122 ; SCSI Messages we interpret in the script
256 ; Use this entry if we've just tried to look at the first byte
473 ; Could be we have nothing more to transfer
708 ; we return here after a reselection
736 ; we return here after a reselection
808 ; we return here after a reselection
/drivers/staging/speakup/
DTODO9 Currently, speakup has several issues we know of.
12 ports. Currently, we communicate directly with the hardware
15 such as PCI-based serial ports. Also, there is not a way we can
/drivers/staging/vc04_services/bcm2835-camera/
DTODO4 pipelines, we need to export our buffers through dma-buf so that the
15 hardware can do. If we exposed the native padding requirements
/drivers/gpu/drm/nouveau/nvkm/engine/gr/fuc/
Dhub.fuc95 // the IRQ handler will signal the host if we ever get one.. we
96 // may find out if/why we need to handle these if so..
149 // set mmctx base addresses now so we don't have to do it later,
212 // save context size, and tell host we're ready
222 // sleep until we have something to do
348 // none we handle; report to host and ack
364 // anything we didn't handle, bring it to the host's attention
429 // good description for the bits we turn off? Anyways, without this,
551 // it's definitely needed for NVIDIA's, so we may as well use it for now
586 // disable the mmio list now, we don't need/want to execute it again
Dgpc.fuc149 // how many TPCs do we have?
158 // determine which GPC we are, setup (optional) mmio access offset
192 // set mmctx base addresses now so we don't have to do it later,
285 // save context size, and tell HUB we're done
380 // good description for the bits we turn off? Anyways, without this,
/drivers/gpu/drm/omapdrm/
DTODO2 . Where should we do eviction (detatch_pages())? We aren't necessarily
3 accessing the pages via a GART, so maybe we need some other threshold
/drivers/gpu/drm/nouveau/nvkm/engine/sec/fuc/
Dg98.fuc0s135 // see which interrupts we got
153 // if bit 30 set, it's active, so we have to unload it first.
164 // tell PFIFO we unloaded
171 // no channel loaded - perhaps we're requested to load one
193 // tell PFIFO we're done
208 // shift the addr to proper position if we need to interrupt later
385 // ok, we'll need to pull second one too
/drivers/staging/media/hantro/
DTODO6 For this reason, we are keeping this driver in staging for now.
/drivers/staging/olpc_dcon/
DTODO9 - see if vx855 gpio API can be made similar enough to cs5535 so we can
/drivers/staging/isdn/
DTODO18 If nobody complains, we can remove them entirely in six months,
/drivers/staging/rtl8192u/
Dcopying21 When we speak of free software, we are referring to freedom, not
28 To protect your rights, we need to make restrictions that forbid
43 Also, for each author's protection and ours, we want to make certain
45 software. If the software is modified by someone else and passed on, we
53 program proprietary. To prevent this, we have made it clear that any
253 Software Foundation, write to the Free Software Foundation; we sometimes
/drivers/target/
Dtarget_core_pr.c320 int we = 0; /* Write Exclusive */ in core_scsi3_pr_seq_non_holder() local
339 we = 1; in core_scsi3_pr_seq_non_holder()
347 we = 1; in core_scsi3_pr_seq_non_holder()
356 we = 1; in core_scsi3_pr_seq_non_holder()
374 ret = (we) ? 0 : 1; in core_scsi3_pr_seq_non_holder()
389 ret = (we) ? 0 : 1; /* Allowed Write Exclusive */ in core_scsi3_pr_seq_non_holder()
440 ret = (we) ? 0 : 1; /* Allowed Write Exclusive */ in core_scsi3_pr_seq_non_holder()
452 ret = (we) ? 0 : 1; /* Allowed Write Exclusive */ in core_scsi3_pr_seq_non_holder()
496 if (we && !registered_nexus) { in core_scsi3_pr_seq_non_holder()
540 } else if (we && registered_nexus) { in core_scsi3_pr_seq_non_holder()
/drivers/gpu/drm/amd/display/
DTODO95 subsystem if we try to move as much of that into helpers/core as possible, and
106 retimer that we need to program to pass PHY compliance. Currently that's

123