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Searched refs:xgene_enet_wr_mac (Results 1 – 4 of 4) sorted by relevance

/drivers/net/ethernet/apm/xgene/
Dxgene_enet_sgmac.c120 xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr); in xgene_mii_phy_write()
123 xgene_enet_wr_mac(p, MII_MGMT_CONTROL_ADDR, wr_data); in xgene_mii_phy_write()
141 xgene_enet_wr_mac(p, MII_MGMT_ADDRESS_ADDR, addr); in xgene_mii_phy_read()
142 xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, READ_CYCLE_MASK); in xgene_mii_phy_read()
148 xgene_enet_wr_mac(p, MII_MGMT_COMMAND_ADDR, 0); in xgene_mii_phy_read()
162 xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, SOFT_RESET1); in xgene_sgmac_reset()
163 xgene_enet_wr_mac(p, MAC_CONFIG_1_ADDR, 0); in xgene_sgmac_reset()
173 xgene_enet_wr_mac(p, STATION_ADDR0_ADDR, addr0); in xgene_sgmac_set_mac_addr()
177 xgene_enet_wr_mac(p, STATION_ADDR1_ADDR, addr1); in xgene_sgmac_set_mac_addr()
275 xgene_enet_wr_mac(p, MAC_CONFIG_2_ADDR, mc2); in xgene_sgmac_set_speed()
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Dxgene_enet_xgmac.c193 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, HSTMACRST); in xgene_xgmac_reset()
194 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_0, 0); in xgene_xgmac_reset()
217 xgene_enet_wr_mac(pdata, HSTMACADR_LSW_ADDR, addr0); in xgene_xgmac_set_mac_addr()
218 xgene_enet_wr_mac(pdata, HSTMACADR_MSW_ADDR, addr1); in xgene_xgmac_set_mac_addr()
241 xgene_enet_wr_mac(pdata, HSTMAXFRAME_LENGTH_ADDR, in xgene_xgmac_set_frame_size()
280 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data); in xgene_xgmac_flowctl_tx()
296 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data); in xgene_xgmac_flowctl_rx()
308 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data); in xgene_xgmac_init()
353 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTRFEN); in xgene_xgmac_rx_enable()
361 xgene_enet_wr_mac(pdata, AXGMAC_CONFIG_1, data | HSTTFEN); in xgene_xgmac_tx_enable()
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Dxgene_enet_hw.c255 void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata, u32 wr_addr, u32 wr_data) in xgene_enet_wr_mac() function
388 xgene_enet_wr_mac(pdata, STATION_ADDR0_ADDR, addr0); in xgene_gmac_set_mac_addr()
389 xgene_enet_wr_mac(pdata, STATION_ADDR1_ADDR, addr1); in xgene_gmac_set_mac_addr()
414 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, SOFT_RESET1); in xgene_gmac_reset()
415 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, 0); in xgene_gmac_reset()
501 xgene_enet_wr_mac(pdata, MAC_CONFIG_2_ADDR, mc2); in xgene_gmac_set_speed()
502 xgene_enet_wr_mac(pdata, INTERFACE_CONTROL_ADDR, intf_ctl); in xgene_gmac_set_speed()
512 xgene_enet_wr_mac(pdata, MAX_FRAME_LEN_ADDR, size); in xgene_enet_set_frame_size()
541 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data); in xgene_gmac_flowctl_tx()
557 xgene_enet_wr_mac(pdata, MAC_CONFIG_1_ADDR, data); in xgene_gmac_flowctl_rx()
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Dxgene_enet_hw.h430 void xgene_enet_wr_mac(struct xgene_enet_pdata *pdata, u32 wr_addr,