1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>,
4 * Creative Labs, Inc.
5 * Definitions for EMU10K1 (SB Live!) chips
6 */
7 #ifndef __SOUND_EMU10K1_H
8 #define __SOUND_EMU10K1_H
9
10
11 #include <sound/pcm.h>
12 #include <sound/rawmidi.h>
13 #include <sound/hwdep.h>
14 #include <sound/ac97_codec.h>
15 #include <sound/util_mem.h>
16 #include <sound/pcm-indirect.h>
17 #include <sound/timer.h>
18 #include <linux/interrupt.h>
19 #include <linux/mutex.h>
20 #include <linux/firmware.h>
21 #include <linux/io.h>
22
23 #include <uapi/sound/emu10k1.h>
24
25 /* ------------------- DEFINES -------------------- */
26
27 #define EMUPAGESIZE 4096
28 #define MAXREQVOICES 8
29 #define MAXPAGES0 4096 /* 32 bit mode */
30 #define MAXPAGES1 8192 /* 31 bit mode */
31 #define RESERVED 0
32 #define NUM_MIDI 16
33 #define NUM_G 64 /* use all channels */
34 #define NUM_FXSENDS 4
35 #define NUM_EFX_PLAYBACK 16
36
37 /* FIXME? - according to the OSS driver the EMU10K1 needs a 29 bit DMA mask */
38 #define EMU10K1_DMA_MASK 0x7fffffffUL /* 31bit */
39 #define AUDIGY_DMA_MASK 0xffffffffUL /* 32bit mode */
40
41 #define TMEMSIZE 256*1024
42 #define TMEMSIZEREG 4
43
44 #define IP_TO_CP(ip) ((ip == 0) ? 0 : (((0x00001000uL | (ip & 0x00000FFFL)) << (((ip >> 12) & 0x000FL) + 4)) & 0xFFFF0000uL))
45
46 // Audigy specify registers are prefixed with 'A_'
47
48 /************************************************************************************************/
49 /* PCI function 0 registers, address = <val> + PCIBASE0 */
50 /************************************************************************************************/
51
52 #define PTR 0x00 /* Indexed register set pointer register */
53 /* NOTE: The CHANNELNUM and ADDRESS words can */
54 /* be modified independently of each other. */
55 #define PTR_CHANNELNUM_MASK 0x0000003f /* For each per-channel register, indicates the */
56 /* channel number of the register to be */
57 /* accessed. For non per-channel registers the */
58 /* value should be set to zero. */
59 #define PTR_ADDRESS_MASK 0x07ff0000 /* Register index */
60 #define A_PTR_ADDRESS_MASK 0x0fff0000
61
62 #define DATA 0x04 /* Indexed register set data register */
63
64 #define IPR 0x08 /* Global interrupt pending register */
65 /* Clear pending interrupts by writing a 1 to */
66 /* the relevant bits and zero to the other bits */
67 #define IPR_P16V 0x80000000 /* Bit set when the CA0151 P16V chip wishes
68 to interrupt */
69 #define IPR_GPIOMSG 0x20000000 /* GPIO message interrupt (RE'd, still not sure
70 which INTE bits enable it) */
71
72 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
73 #define IPR_A_MIDITRANSBUFEMPTY2 0x10000000 /* MIDI UART transmit buffer empty */
74 #define IPR_A_MIDIRECVBUFEMPTY2 0x08000000 /* MIDI UART receive buffer empty */
75
76 #define IPR_SPDIFBUFFULL 0x04000000 /* SPDIF capture related, 10k2 only? (RE) */
77 #define IPR_SPDIFBUFHALFFULL 0x02000000 /* SPDIF capture related? (RE) */
78
79 #define IPR_SAMPLERATETRACKER 0x01000000 /* Sample rate tracker lock status change */
80 #define IPR_FXDSP 0x00800000 /* Enable FX DSP interrupts */
81 #define IPR_FORCEINT 0x00400000 /* Force Sound Blaster interrupt */
82 #define IPR_PCIERROR 0x00200000 /* PCI bus error */
83 #define IPR_VOLINCR 0x00100000 /* Volume increment button pressed */
84 #define IPR_VOLDECR 0x00080000 /* Volume decrement button pressed */
85 #define IPR_MUTE 0x00040000 /* Mute button pressed */
86 #define IPR_MICBUFFULL 0x00020000 /* Microphone buffer full */
87 #define IPR_MICBUFHALFFULL 0x00010000 /* Microphone buffer half full */
88 #define IPR_ADCBUFFULL 0x00008000 /* ADC buffer full */
89 #define IPR_ADCBUFHALFFULL 0x00004000 /* ADC buffer half full */
90 #define IPR_EFXBUFFULL 0x00002000 /* Effects buffer full */
91 #define IPR_EFXBUFHALFFULL 0x00001000 /* Effects buffer half full */
92 #define IPR_GPSPDIFSTATUSCHANGE 0x00000800 /* GPSPDIF channel status change */
93 #define IPR_CDROMSTATUSCHANGE 0x00000400 /* CD-ROM channel status change */
94 #define IPR_INTERVALTIMER 0x00000200 /* Interval timer terminal count */
95 #define IPR_MIDITRANSBUFEMPTY 0x00000100 /* MIDI UART transmit buffer empty */
96 #define IPR_MIDIRECVBUFEMPTY 0x00000080 /* MIDI UART receive buffer empty */
97 #define IPR_CHANNELLOOP 0x00000040 /* Channel (half) loop interrupt(s) pending */
98 #define IPR_CHANNELNUMBERMASK 0x0000003f /* When IPR_CHANNELLOOP is set, indicates the */
99 /* highest set channel in CLIPL, CLIPH, HLIPL, */
100 /* or HLIPH. When IP is written with CL set, */
101 /* the bit in H/CLIPL or H/CLIPH corresponding */
102 /* to the CIN value written will be cleared. */
103
104 #define INTE 0x0c /* Interrupt enable register */
105 #define INTE_VIRTUALSB_MASK 0xc0000000 /* Virtual Soundblaster I/O port capture */
106 #define INTE_VIRTUALSB_220 0x00000000 /* Capture at I/O base address 0x220-0x22f */
107 #define INTE_VIRTUALSB_240 0x40000000 /* Capture at I/O base address 0x240 */
108 #define INTE_VIRTUALSB_260 0x80000000 /* Capture at I/O base address 0x260 */
109 #define INTE_VIRTUALSB_280 0xc0000000 /* Capture at I/O base address 0x280 */
110 #define INTE_VIRTUALMPU_MASK 0x30000000 /* Virtual MPU I/O port capture */
111 #define INTE_VIRTUALMPU_300 0x00000000 /* Capture at I/O base address 0x300-0x301 */
112 #define INTE_VIRTUALMPU_310 0x10000000 /* Capture at I/O base address 0x310 */
113 #define INTE_VIRTUALMPU_320 0x20000000 /* Capture at I/O base address 0x320 */
114 #define INTE_VIRTUALMPU_330 0x30000000 /* Capture at I/O base address 0x330 */
115 #define INTE_MASTERDMAENABLE 0x08000000 /* Master DMA emulation at 0x000-0x00f */
116 #define INTE_SLAVEDMAENABLE 0x04000000 /* Slave DMA emulation at 0x0c0-0x0df */
117 #define INTE_MASTERPICENABLE 0x02000000 /* Master PIC emulation at 0x020-0x021 */
118 #define INTE_SLAVEPICENABLE 0x01000000 /* Slave PIC emulation at 0x0a0-0x0a1 */
119 #define INTE_VSBENABLE 0x00800000 /* Enable virtual Soundblaster */
120 #define INTE_ADLIBENABLE 0x00400000 /* Enable AdLib emulation at 0x388-0x38b */
121 #define INTE_MPUENABLE 0x00200000 /* Enable virtual MPU */
122 #define INTE_FORCEINT 0x00100000 /* Continuously assert INTAN */
123
124 #define INTE_MRHANDENABLE 0x00080000 /* Enable the "Mr. Hand" logic */
125 /* NOTE: There is no reason to use this under */
126 /* Linux, and it will cause odd hardware */
127 /* behavior and possibly random segfaults and */
128 /* lockups if enabled. */
129
130 /* The next two interrupts are for the midi port on the Audigy Drive (A_MPU1) */
131 #define INTE_A_MIDITXENABLE2 0x00020000 /* Enable MIDI transmit-buffer-empty interrupts */
132 #define INTE_A_MIDIRXENABLE2 0x00010000 /* Enable MIDI receive-buffer-empty interrupts */
133
134
135 #define INTE_SAMPLERATETRACKER 0x00002000 /* Enable sample rate tracker interrupts */
136 /* NOTE: This bit must always be enabled */
137 #define INTE_FXDSPENABLE 0x00001000 /* Enable FX DSP interrupts */
138 #define INTE_PCIERRORENABLE 0x00000800 /* Enable PCI bus error interrupts */
139 #define INTE_VOLINCRENABLE 0x00000400 /* Enable volume increment button interrupts */
140 #define INTE_VOLDECRENABLE 0x00000200 /* Enable volume decrement button interrupts */
141 #define INTE_MUTEENABLE 0x00000100 /* Enable mute button interrupts */
142 #define INTE_MICBUFENABLE 0x00000080 /* Enable microphone buffer interrupts */
143 #define INTE_ADCBUFENABLE 0x00000040 /* Enable ADC buffer interrupts */
144 #define INTE_EFXBUFENABLE 0x00000020 /* Enable Effects buffer interrupts */
145 #define INTE_GPSPDIFENABLE 0x00000010 /* Enable GPSPDIF status interrupts */
146 #define INTE_CDSPDIFENABLE 0x00000008 /* Enable CDSPDIF status interrupts */
147 #define INTE_INTERVALTIMERENB 0x00000004 /* Enable interval timer interrupts */
148 #define INTE_MIDITXENABLE 0x00000002 /* Enable MIDI transmit-buffer-empty interrupts */
149 #define INTE_MIDIRXENABLE 0x00000001 /* Enable MIDI receive-buffer-empty interrupts */
150
151 #define WC 0x10 /* Wall Clock register */
152 #define WC_SAMPLECOUNTER_MASK 0x03FFFFC0 /* Sample periods elapsed since reset */
153 #define WC_SAMPLECOUNTER 0x14060010
154 #define WC_CURRENTCHANNEL 0x0000003F /* Channel [0..63] currently being serviced */
155 /* NOTE: Each channel takes 1/64th of a sample */
156 /* period to be serviced. */
157
158 #define HCFG 0x14 /* Hardware config register */
159 /* NOTE: There is no reason to use the legacy */
160 /* SoundBlaster emulation stuff described below */
161 /* under Linux, and all kinds of weird hardware */
162 /* behavior can result if you try. Don't. */
163 #define HCFG_LEGACYFUNC_MASK 0xe0000000 /* Legacy function number */
164 #define HCFG_LEGACYFUNC_MPU 0x00000000 /* Legacy MPU */
165 #define HCFG_LEGACYFUNC_SB 0x40000000 /* Legacy SB */
166 #define HCFG_LEGACYFUNC_AD 0x60000000 /* Legacy AD */
167 #define HCFG_LEGACYFUNC_MPIC 0x80000000 /* Legacy MPIC */
168 #define HCFG_LEGACYFUNC_MDMA 0xa0000000 /* Legacy MDMA */
169 #define HCFG_LEGACYFUNC_SPCI 0xc0000000 /* Legacy SPCI */
170 #define HCFG_LEGACYFUNC_SDMA 0xe0000000 /* Legacy SDMA */
171 #define HCFG_IOCAPTUREADDR 0x1f000000 /* The 4 LSBs of the captured I/O address. */
172 #define HCFG_LEGACYWRITE 0x00800000 /* 1 = write, 0 = read */
173 #define HCFG_LEGACYWORD 0x00400000 /* 1 = word, 0 = byte */
174 #define HCFG_LEGACYINT 0x00200000 /* 1 = legacy event captured. Write 1 to clear. */
175 /* NOTE: The rest of the bits in this register */
176 /* _are_ relevant under Linux. */
177 #define HCFG_PUSH_BUTTON_ENABLE 0x00100000 /* Enables Volume Inc/Dec and Mute functions */
178 #define HCFG_BAUD_RATE 0x00080000 /* 0 = 48kHz, 1 = 44.1kHz */
179 #define HCFG_EXPANDED_MEM 0x00040000 /* 1 = any 16M of 4G addr, 0 = 32M of 2G addr */
180 #define HCFG_CODECFORMAT_MASK 0x00030000 /* CODEC format */
181
182 /* Specific to Alice2, CA0102 */
183 #define HCFG_CODECFORMAT_AC97_1 0x00000000 /* AC97 CODEC format -- Ver 1.03 */
184 #define HCFG_CODECFORMAT_AC97_2 0x00010000 /* AC97 CODEC format -- Ver 2.1 */
185 #define HCFG_AUTOMUTE_ASYNC 0x00008000 /* When set, the async sample rate convertors */
186 /* will automatically mute their output when */
187 /* they are not rate-locked to the external */
188 /* async audio source */
189 #define HCFG_AUTOMUTE_SPDIF 0x00004000 /* When set, the async sample rate convertors */
190 /* will automatically mute their output when */
191 /* the SPDIF V-bit indicates invalid audio */
192 #define HCFG_EMU32_SLAVE 0x00002000 /* 0 = Master, 1 = Slave. Slave for EMU1010 */
193 #define HCFG_SLOW_RAMP 0x00001000 /* Increases Send Smoothing time constant */
194 /* 0x00000800 not used on Alice2 */
195 #define HCFG_PHASE_TRACK_MASK 0x00000700 /* When set, forces corresponding input to */
196 /* phase track the previous input. */
197 /* I2S0 can phase track the last S/PDIF input */
198 #define HCFG_I2S_ASRC_ENABLE 0x00000070 /* When set, enables asynchronous sample rate */
199 /* conversion for the corresponding */
200 /* I2S format input */
201 /* Rest of HCFG 0x0000000f same as below. LOCKSOUNDCACHE etc. */
202
203
204
205 /* Older chips */
206 #define HCFG_CODECFORMAT_AC97 0x00000000 /* AC97 CODEC format -- Primary Output */
207 #define HCFG_CODECFORMAT_I2S 0x00010000 /* I2S CODEC format -- Secondary (Rear) Output */
208 #define HCFG_GPINPUT0 0x00004000 /* External pin112 */
209 #define HCFG_GPINPUT1 0x00002000 /* External pin110 */
210 #define HCFG_GPOUTPUT_MASK 0x00001c00 /* External pins which may be controlled */
211 #define HCFG_GPOUT0 0x00001000 /* External pin? (spdif enable on 5.1) */
212 #define HCFG_GPOUT1 0x00000800 /* External pin? (IR) */
213 #define HCFG_GPOUT2 0x00000400 /* External pin? (IR) */
214 #define HCFG_JOYENABLE 0x00000200 /* Internal joystick enable */
215 #define HCFG_PHASETRACKENABLE 0x00000100 /* Phase tracking enable */
216 /* 1 = Force all 3 async digital inputs to use */
217 /* the same async sample rate tracker (ZVIDEO) */
218 #define HCFG_AC3ENABLE_MASK 0x000000e0 /* AC3 async input control - Not implemented */
219 #define HCFG_AC3ENABLE_ZVIDEO 0x00000080 /* Channels 0 and 1 replace ZVIDEO */
220 #define HCFG_AC3ENABLE_CDSPDIF 0x00000040 /* Channels 0 and 1 replace CDSPDIF */
221 #define HCFG_AC3ENABLE_GPSPDIF 0x00000020 /* Channels 0 and 1 replace GPSPDIF */
222 #define HCFG_AUTOMUTE 0x00000010 /* When set, the async sample rate convertors */
223 /* will automatically mute their output when */
224 /* they are not rate-locked to the external */
225 /* async audio source */
226 #define HCFG_LOCKSOUNDCACHE 0x00000008 /* 1 = Cancel bustmaster accesses to soundcache */
227 /* NOTE: This should generally never be used. */
228 #define HCFG_LOCKTANKCACHE_MASK 0x00000004 /* 1 = Cancel bustmaster accesses to tankcache */
229 /* NOTE: This should generally never be used. */
230 #define HCFG_LOCKTANKCACHE 0x01020014
231 #define HCFG_MUTEBUTTONENABLE 0x00000002 /* 1 = Master mute button sets AUDIOENABLE = 0. */
232 /* NOTE: This is a 'cheap' way to implement a */
233 /* master mute function on the mute button, and */
234 /* in general should not be used unless a more */
235 /* sophisticated master mute function has not */
236 /* been written. */
237 #define HCFG_AUDIOENABLE 0x00000001 /* 0 = CODECs transmit zero-valued samples */
238 /* Should be set to 1 when the EMU10K1 is */
239 /* completely initialized. */
240
241 //For Audigy, MPU port move to 0x70-0x74 ptr register
242
243 #define MUDATA 0x18 /* MPU401 data register (8 bits) */
244
245 #define MUCMD 0x19 /* MPU401 command register (8 bits) */
246 #define MUCMD_RESET 0xff /* RESET command */
247 #define MUCMD_ENTERUARTMODE 0x3f /* Enter_UART_mode command */
248 /* NOTE: All other commands are ignored */
249
250 #define MUSTAT MUCMD /* MPU401 status register (8 bits) */
251 #define MUSTAT_IRDYN 0x80 /* 0 = MIDI data or command ACK */
252 #define MUSTAT_ORDYN 0x40 /* 0 = MUDATA can accept a command or data */
253
254 #define A_IOCFG 0x18 /* GPIO on Audigy card (16bits) */
255 #define A_GPINPUT_MASK 0xff00
256 #define A_GPOUTPUT_MASK 0x00ff
257
258 // Audigy output/GPIO stuff taken from the kX drivers
259 #define A_IOCFG_GPOUT0 0x0044 /* analog/digital */
260 #define A_IOCFG_DISABLE_ANALOG 0x0040 /* = 'enable' for Audigy2 (chiprev=4) */
261 #define A_IOCFG_ENABLE_DIGITAL 0x0004
262 #define A_IOCFG_ENABLE_DIGITAL_AUDIGY4 0x0080
263 #define A_IOCFG_UNKNOWN_20 0x0020
264 #define A_IOCFG_DISABLE_AC97_FRONT 0x0080 /* turn off ac97 front -> front (10k2.1) */
265 #define A_IOCFG_GPOUT1 0x0002 /* IR? drive's internal bypass (?) */
266 #define A_IOCFG_GPOUT2 0x0001 /* IR */
267 #define A_IOCFG_MULTIPURPOSE_JACK 0x2000 /* center+lfe+rear_center (a2/a2ex) */
268 /* + digital for generic 10k2 */
269 #define A_IOCFG_DIGITAL_JACK 0x1000 /* digital for a2 platinum */
270 #define A_IOCFG_FRONT_JACK 0x4000
271 #define A_IOCFG_REAR_JACK 0x8000
272 #define A_IOCFG_PHONES_JACK 0x0100 /* LiveDrive */
273
274 /* outputs:
275 * for audigy2 platinum: 0xa00
276 * for a2 platinum ex: 0x1c00
277 * for a1 platinum: 0x0
278 */
279
280 #define TIMER 0x1a /* Timer terminal count register */
281 /* NOTE: After the rate is changed, a maximum */
282 /* of 1024 sample periods should be allowed */
283 /* before the new rate is guaranteed accurate. */
284 #define TIMER_RATE_MASK 0x000003ff /* Timer interrupt rate in sample periods */
285 /* 0 == 1024 periods, [1..4] are not useful */
286 #define TIMER_RATE 0x0a00001a
287
288 #define AC97DATA 0x1c /* AC97 register set data register (16 bit) */
289
290 #define AC97ADDRESS 0x1e /* AC97 register set address register (8 bit) */
291 #define AC97ADDRESS_READY 0x80 /* Read-only bit, reflects CODEC READY signal */
292 #define AC97ADDRESS_ADDRESS 0x7f /* Address of indexed AC97 register */
293
294 /* Available on the Audigy 2 and Audigy 4 only. This is the P16V chip. */
295 #define PTR2 0x20 /* Indexed register set pointer register */
296 #define DATA2 0x24 /* Indexed register set data register */
297 #define IPR2 0x28 /* P16V interrupt pending register */
298 #define IPR2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
299 #define IPR2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
300 #define IPR2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
301 #define IPR2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Capture Channel 0 half loop */
302 /* 0x00000100 Playback. Only in once per period.
303 * 0x00110000 Capture. Int on half buffer.
304 */
305 #define INTE2 0x2c /* P16V Interrupt enable register. */
306 #define INTE2_PLAYBACK_CH_0_LOOP 0x00001000 /* Playback Channel 0 loop */
307 #define INTE2_PLAYBACK_CH_0_HALF_LOOP 0x00000100 /* Playback Channel 0 half loop */
308 #define INTE2_PLAYBACK_CH_1_LOOP 0x00002000 /* Playback Channel 1 loop */
309 #define INTE2_PLAYBACK_CH_1_HALF_LOOP 0x00000200 /* Playback Channel 1 half loop */
310 #define INTE2_PLAYBACK_CH_2_LOOP 0x00004000 /* Playback Channel 2 loop */
311 #define INTE2_PLAYBACK_CH_2_HALF_LOOP 0x00000400 /* Playback Channel 2 half loop */
312 #define INTE2_PLAYBACK_CH_3_LOOP 0x00008000 /* Playback Channel 3 loop */
313 #define INTE2_PLAYBACK_CH_3_HALF_LOOP 0x00000800 /* Playback Channel 3 half loop */
314 #define INTE2_CAPTURE_CH_0_LOOP 0x00100000 /* Capture Channel 0 loop */
315 #define INTE2_CAPTURE_CH_0_HALF_LOOP 0x00010000 /* Caputre Channel 0 half loop */
316 #define HCFG2 0x34 /* Defaults: 0, win2000 sets it to 00004201 */
317 /* 0x00000000 2-channel output. */
318 /* 0x00000200 8-channel output. */
319 /* 0x00000004 pauses stream/irq fail. */
320 /* Rest of bits no nothing to sound output */
321 /* bit 0: Enable P16V audio.
322 * bit 1: Lock P16V record memory cache.
323 * bit 2: Lock P16V playback memory cache.
324 * bit 3: Dummy record insert zero samples.
325 * bit 8: Record 8-channel in phase.
326 * bit 9: Playback 8-channel in phase.
327 * bit 11-12: Playback mixer attenuation: 0=0dB, 1=-6dB, 2=-12dB, 3=Mute.
328 * bit 13: Playback mixer enable.
329 * bit 14: Route SRC48 mixer output to fx engine.
330 * bit 15: Enable IEEE 1394 chip.
331 */
332 #define IPR3 0x38 /* Cdif interrupt pending register */
333 #define INTE3 0x3c /* Cdif interrupt enable register. */
334 /************************************************************************************************/
335 /* PCI function 1 registers, address = <val> + PCIBASE1 */
336 /************************************************************************************************/
337
338 #define JOYSTICK1 0x00 /* Analog joystick port register */
339 #define JOYSTICK2 0x01 /* Analog joystick port register */
340 #define JOYSTICK3 0x02 /* Analog joystick port register */
341 #define JOYSTICK4 0x03 /* Analog joystick port register */
342 #define JOYSTICK5 0x04 /* Analog joystick port register */
343 #define JOYSTICK6 0x05 /* Analog joystick port register */
344 #define JOYSTICK7 0x06 /* Analog joystick port register */
345 #define JOYSTICK8 0x07 /* Analog joystick port register */
346
347 /* When writing, any write causes JOYSTICK_COMPARATOR output enable to be pulsed on write. */
348 /* When reading, use these bitfields: */
349 #define JOYSTICK_BUTTONS 0x0f /* Joystick button data */
350 #define JOYSTICK_COMPARATOR 0xf0 /* Joystick comparator data */
351
352
353 /********************************************************************************************************/
354 /* Emu10k1 pointer-offset register set, accessed through the PTR and DATA registers */
355 /********************************************************************************************************/
356
357 #define CPF 0x00 /* Current pitch and fraction register */
358 #define CPF_CURRENTPITCH_MASK 0xffff0000 /* Current pitch (linear, 0x4000 == unity pitch shift) */
359 #define CPF_CURRENTPITCH 0x10100000
360 #define CPF_STEREO_MASK 0x00008000 /* 1 = Even channel interleave, odd channel locked */
361 #define CPF_STOP_MASK 0x00004000 /* 1 = Current pitch forced to 0 */
362 #define CPF_FRACADDRESS_MASK 0x00003fff /* Linear fractional address of the current channel */
363
364 #define PTRX 0x01 /* Pitch target and send A/B amounts register */
365 #define PTRX_PITCHTARGET_MASK 0xffff0000 /* Pitch target of specified channel */
366 #define PTRX_PITCHTARGET 0x10100001
367 #define PTRX_FXSENDAMOUNT_A_MASK 0x0000ff00 /* Linear level of channel output sent to FX send bus A */
368 #define PTRX_FXSENDAMOUNT_A 0x08080001
369 #define PTRX_FXSENDAMOUNT_B_MASK 0x000000ff /* Linear level of channel output sent to FX send bus B */
370 #define PTRX_FXSENDAMOUNT_B 0x08000001
371
372 #define CVCF 0x02 /* Current volume and filter cutoff register */
373 #define CVCF_CURRENTVOL_MASK 0xffff0000 /* Current linear volume of specified channel */
374 #define CVCF_CURRENTVOL 0x10100002
375 #define CVCF_CURRENTFILTER_MASK 0x0000ffff /* Current filter cutoff frequency of specified channel */
376 #define CVCF_CURRENTFILTER 0x10000002
377
378 #define VTFT 0x03 /* Volume target and filter cutoff target register */
379 #define VTFT_VOLUMETARGET_MASK 0xffff0000 /* Volume target of specified channel */
380 #define VTFT_VOLUMETARGET 0x10100003
381 #define VTFT_FILTERTARGET_MASK 0x0000ffff /* Filter cutoff target of specified channel */
382 #define VTFT_FILTERTARGET 0x10000003
383
384 #define Z1 0x05 /* Filter delay memory 1 register */
385
386 #define Z2 0x04 /* Filter delay memory 2 register */
387
388 #define PSST 0x06 /* Send C amount and loop start address register */
389 #define PSST_FXSENDAMOUNT_C_MASK 0xff000000 /* Linear level of channel output sent to FX send bus C */
390
391 #define PSST_FXSENDAMOUNT_C 0x08180006
392
393 #define PSST_LOOPSTARTADDR_MASK 0x00ffffff /* Loop start address of the specified channel */
394 #define PSST_LOOPSTARTADDR 0x18000006
395
396 #define DSL 0x07 /* Send D amount and loop start address register */
397 #define DSL_FXSENDAMOUNT_D_MASK 0xff000000 /* Linear level of channel output sent to FX send bus D */
398
399 #define DSL_FXSENDAMOUNT_D 0x08180007
400
401 #define DSL_LOOPENDADDR_MASK 0x00ffffff /* Loop end address of the specified channel */
402 #define DSL_LOOPENDADDR 0x18000007
403
404 #define CCCA 0x08 /* Filter Q, interp. ROM, byte size, cur. addr register */
405 #define CCCA_RESONANCE 0xf0000000 /* Lowpass filter resonance (Q) height */
406 #define CCCA_INTERPROMMASK 0x0e000000 /* Selects passband of interpolation ROM */
407 /* 1 == full band, 7 == lowpass */
408 /* ROM 0 is used when pitch shifting downward or less */
409 /* then 3 semitones upward. Increasingly higher ROM */
410 /* numbers are used, typically in steps of 3 semitones, */
411 /* as upward pitch shifting is performed. */
412 #define CCCA_INTERPROM_0 0x00000000 /* Select interpolation ROM 0 */
413 #define CCCA_INTERPROM_1 0x02000000 /* Select interpolation ROM 1 */
414 #define CCCA_INTERPROM_2 0x04000000 /* Select interpolation ROM 2 */
415 #define CCCA_INTERPROM_3 0x06000000 /* Select interpolation ROM 3 */
416 #define CCCA_INTERPROM_4 0x08000000 /* Select interpolation ROM 4 */
417 #define CCCA_INTERPROM_5 0x0a000000 /* Select interpolation ROM 5 */
418 #define CCCA_INTERPROM_6 0x0c000000 /* Select interpolation ROM 6 */
419 #define CCCA_INTERPROM_7 0x0e000000 /* Select interpolation ROM 7 */
420 #define CCCA_8BITSELECT 0x01000000 /* 1 = Sound memory for this channel uses 8-bit samples */
421 #define CCCA_CURRADDR_MASK 0x00ffffff /* Current address of the selected channel */
422 #define CCCA_CURRADDR 0x18000008
423
424 #define CCR 0x09 /* Cache control register */
425 #define CCR_CACHEINVALIDSIZE 0x07190009
426 #define CCR_CACHEINVALIDSIZE_MASK 0xfe000000 /* Number of invalid samples cache for this channel */
427 #define CCR_CACHELOOPFLAG 0x01000000 /* 1 = Cache has a loop service pending */
428 #define CCR_INTERLEAVEDSAMPLES 0x00800000 /* 1 = A cache service will fetch interleaved samples */
429 #define CCR_WORDSIZEDSAMPLES 0x00400000 /* 1 = A cache service will fetch word sized samples */
430 #define CCR_READADDRESS 0x06100009
431 #define CCR_READADDRESS_MASK 0x003f0000 /* Location of cache just beyond current cache service */
432 #define CCR_LOOPINVALSIZE 0x0000fe00 /* Number of invalid samples in cache prior to loop */
433 /* NOTE: This is valid only if CACHELOOPFLAG is set */
434 #define CCR_LOOPFLAG 0x00000100 /* Set for a single sample period when a loop occurs */
435 #define CCR_CACHELOOPADDRHI 0x000000ff /* DSL_LOOPSTARTADDR's hi byte if CACHELOOPFLAG is set */
436
437 #define CLP 0x0a /* Cache loop register (valid if CCR_CACHELOOPFLAG = 1) */
438 /* NOTE: This register is normally not used */
439 #define CLP_CACHELOOPADDR 0x0000ffff /* Cache loop address (DSL_LOOPSTARTADDR [0..15]) */
440
441 #define FXRT 0x0b /* Effects send routing register */
442 /* NOTE: It is illegal to assign the same routing to */
443 /* two effects sends. */
444 #define FXRT_CHANNELA 0x000f0000 /* Effects send bus number for channel's effects send A */
445 #define FXRT_CHANNELB 0x00f00000 /* Effects send bus number for channel's effects send B */
446 #define FXRT_CHANNELC 0x0f000000 /* Effects send bus number for channel's effects send C */
447 #define FXRT_CHANNELD 0xf0000000 /* Effects send bus number for channel's effects send D */
448
449 #define A_HR 0x0b /* High Resolution. 24bit playback from host to DSP. */
450 #define MAPA 0x0c /* Cache map A */
451
452 #define MAPB 0x0d /* Cache map B */
453
454 #define MAP_PTE_MASK0 0xfffff000 /* The 20 MSBs of the PTE indexed by the PTI */
455 #define MAP_PTI_MASK0 0x00000fff /* The 12 bit index to one of the 4096 PTE dwords */
456
457 #define MAP_PTE_MASK1 0xffffe000 /* The 19 MSBs of the PTE indexed by the PTI */
458 #define MAP_PTI_MASK1 0x00001fff /* The 13 bit index to one of the 8192 PTE dwords */
459
460 /* 0x0e, 0x0f: Not used */
461
462 #define ENVVOL 0x10 /* Volume envelope register */
463 #define ENVVOL_MASK 0x0000ffff /* Current value of volume envelope state variable */
464 /* 0x8000-n == 666*n usec delay */
465
466 #define ATKHLDV 0x11 /* Volume envelope hold and attack register */
467 #define ATKHLDV_PHASE0 0x00008000 /* 0 = Begin attack phase */
468 #define ATKHLDV_HOLDTIME_MASK 0x00007f00 /* Envelope hold time (127-n == n*88.2msec) */
469 #define ATKHLDV_ATTACKTIME_MASK 0x0000007f /* Envelope attack time, log encoded */
470 /* 0 = infinite, 1 = 10.9msec, ... 0x7f = 5.5msec */
471
472 #define DCYSUSV 0x12 /* Volume envelope sustain and decay register */
473 #define DCYSUSV_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
474 #define DCYSUSV_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
475 #define DCYSUSV_CHANNELENABLE_MASK 0x00000080 /* 1 = Inhibit envelope engine from writing values in */
476 /* this channel and from writing to pitch, filter and */
477 /* volume targets. */
478 #define DCYSUSV_DECAYTIME_MASK 0x0000007f /* Volume envelope decay time, log encoded */
479 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
480
481 #define LFOVAL1 0x13 /* Modulation LFO value */
482 #define LFOVAL_MASK 0x0000ffff /* Current value of modulation LFO state variable */
483 /* 0x8000-n == 666*n usec delay */
484
485 #define ENVVAL 0x14 /* Modulation envelope register */
486 #define ENVVAL_MASK 0x0000ffff /* Current value of modulation envelope state variable */
487 /* 0x8000-n == 666*n usec delay */
488
489 #define ATKHLDM 0x15 /* Modulation envelope hold and attack register */
490 #define ATKHLDM_PHASE0 0x00008000 /* 0 = Begin attack phase */
491 #define ATKHLDM_HOLDTIME 0x00007f00 /* Envelope hold time (127-n == n*42msec) */
492 #define ATKHLDM_ATTACKTIME 0x0000007f /* Envelope attack time, log encoded */
493 /* 0 = infinite, 1 = 11msec, ... 0x7f = 5.5msec */
494
495 #define DCYSUSM 0x16 /* Modulation envelope decay and sustain register */
496 #define DCYSUSM_PHASE1_MASK 0x00008000 /* 0 = Begin attack phase, 1 = begin release phase */
497 #define DCYSUSM_SUSTAINLEVEL_MASK 0x00007f00 /* 127 = full, 0 = off, 0.75dB increments */
498 #define DCYSUSM_DECAYTIME_MASK 0x0000007f /* Envelope decay time, log encoded */
499 /* 0 = 43.7msec, 1 = 21.8msec, 0x7f = 22msec */
500
501 #define LFOVAL2 0x17 /* Vibrato LFO register */
502 #define LFOVAL2_MASK 0x0000ffff /* Current value of vibrato LFO state variable */
503 /* 0x8000-n == 666*n usec delay */
504
505 #define IP 0x18 /* Initial pitch register */
506 #define IP_MASK 0x0000ffff /* Exponential initial pitch shift */
507 /* 4 bits of octave, 12 bits of fractional octave */
508 #define IP_UNITY 0x0000e000 /* Unity pitch shift */
509
510 #define IFATN 0x19 /* Initial filter cutoff and attenuation register */
511 #define IFATN_FILTERCUTOFF_MASK 0x0000ff00 /* Initial filter cutoff frequency in exponential units */
512 /* 6 most significant bits are semitones */
513 /* 2 least significant bits are fractions */
514 #define IFATN_FILTERCUTOFF 0x08080019
515 #define IFATN_ATTENUATION_MASK 0x000000ff /* Initial attenuation in 0.375dB steps */
516 #define IFATN_ATTENUATION 0x08000019
517
518
519 #define PEFE 0x1a /* Pitch envelope and filter envelope amount register */
520 #define PEFE_PITCHAMOUNT_MASK 0x0000ff00 /* Pitch envlope amount */
521 /* Signed 2's complement, +/- one octave peak extremes */
522 #define PEFE_PITCHAMOUNT 0x0808001a
523 #define PEFE_FILTERAMOUNT_MASK 0x000000ff /* Filter envlope amount */
524 /* Signed 2's complement, +/- six octaves peak extremes */
525 #define PEFE_FILTERAMOUNT 0x0800001a
526 #define FMMOD 0x1b /* Vibrato/filter modulation from LFO register */
527 #define FMMOD_MODVIBRATO 0x0000ff00 /* Vibrato LFO modulation depth */
528 /* Signed 2's complement, +/- one octave extremes */
529 #define FMMOD_MOFILTER 0x000000ff /* Filter LFO modulation depth */
530 /* Signed 2's complement, +/- three octave extremes */
531
532
533 #define TREMFRQ 0x1c /* Tremolo amount and modulation LFO frequency register */
534 #define TREMFRQ_DEPTH 0x0000ff00 /* Tremolo depth */
535 /* Signed 2's complement, with +/- 12dB extremes */
536
537 #define TREMFRQ_FREQUENCY 0x000000ff /* Tremolo LFO frequency */
538 /* ??Hz steps, maximum of ?? Hz. */
539 #define FM2FRQ2 0x1d /* Vibrato amount and vibrato LFO frequency register */
540 #define FM2FRQ2_DEPTH 0x0000ff00 /* Vibrato LFO vibrato depth */
541 /* Signed 2's complement, +/- one octave extremes */
542 #define FM2FRQ2_FREQUENCY 0x000000ff /* Vibrato LFO frequency */
543 /* 0.039Hz steps, maximum of 9.85 Hz. */
544
545 #define TEMPENV 0x1e /* Tempory envelope register */
546 #define TEMPENV_MASK 0x0000ffff /* 16-bit value */
547 /* NOTE: All channels contain internal variables; do */
548 /* not write to these locations. */
549
550 /* 0x1f: not used */
551
552 #define CD0 0x20 /* Cache data 0 register */
553 #define CD1 0x21 /* Cache data 1 register */
554 #define CD2 0x22 /* Cache data 2 register */
555 #define CD3 0x23 /* Cache data 3 register */
556 #define CD4 0x24 /* Cache data 4 register */
557 #define CD5 0x25 /* Cache data 5 register */
558 #define CD6 0x26 /* Cache data 6 register */
559 #define CD7 0x27 /* Cache data 7 register */
560 #define CD8 0x28 /* Cache data 8 register */
561 #define CD9 0x29 /* Cache data 9 register */
562 #define CDA 0x2a /* Cache data A register */
563 #define CDB 0x2b /* Cache data B register */
564 #define CDC 0x2c /* Cache data C register */
565 #define CDD 0x2d /* Cache data D register */
566 #define CDE 0x2e /* Cache data E register */
567 #define CDF 0x2f /* Cache data F register */
568
569 /* 0x30-3f seem to be the same as 0x20-2f */
570
571 #define PTB 0x40 /* Page table base register */
572 #define PTB_MASK 0xfffff000 /* Physical address of the page table in host memory */
573
574 #define TCB 0x41 /* Tank cache base register */
575 #define TCB_MASK 0xfffff000 /* Physical address of the bottom of host based TRAM */
576
577 #define ADCCR 0x42 /* ADC sample rate/stereo control register */
578 #define ADCCR_RCHANENABLE 0x00000010 /* Enables right channel for writing to the host */
579 #define ADCCR_LCHANENABLE 0x00000008 /* Enables left channel for writing to the host */
580 /* NOTE: To guarantee phase coherency, both channels */
581 /* must be disabled prior to enabling both channels. */
582 #define A_ADCCR_RCHANENABLE 0x00000020
583 #define A_ADCCR_LCHANENABLE 0x00000010
584
585 #define A_ADCCR_SAMPLERATE_MASK 0x0000000F /* Audigy sample rate convertor output rate */
586 #define ADCCR_SAMPLERATE_MASK 0x00000007 /* Sample rate convertor output rate */
587 #define ADCCR_SAMPLERATE_48 0x00000000 /* 48kHz sample rate */
588 #define ADCCR_SAMPLERATE_44 0x00000001 /* 44.1kHz sample rate */
589 #define ADCCR_SAMPLERATE_32 0x00000002 /* 32kHz sample rate */
590 #define ADCCR_SAMPLERATE_24 0x00000003 /* 24kHz sample rate */
591 #define ADCCR_SAMPLERATE_22 0x00000004 /* 22.05kHz sample rate */
592 #define ADCCR_SAMPLERATE_16 0x00000005 /* 16kHz sample rate */
593 #define ADCCR_SAMPLERATE_11 0x00000006 /* 11.025kHz sample rate */
594 #define ADCCR_SAMPLERATE_8 0x00000007 /* 8kHz sample rate */
595 #define A_ADCCR_SAMPLERATE_12 0x00000006 /* 12kHz sample rate */
596 #define A_ADCCR_SAMPLERATE_11 0x00000007 /* 11.025kHz sample rate */
597 #define A_ADCCR_SAMPLERATE_8 0x00000008 /* 8kHz sample rate */
598
599 #define FXWC 0x43 /* FX output write channels register */
600 /* When set, each bit enables the writing of the */
601 /* corresponding FX output channel (internal registers */
602 /* 0x20-0x3f) to host memory. This mode of recording */
603 /* is 16bit, 48KHz only. All 32 channels can be enabled */
604 /* simultaneously. */
605
606 #define FXWC_DEFAULTROUTE_C (1<<0) /* left emu out? */
607 #define FXWC_DEFAULTROUTE_B (1<<1) /* right emu out? */
608 #define FXWC_DEFAULTROUTE_A (1<<12)
609 #define FXWC_DEFAULTROUTE_D (1<<13)
610 #define FXWC_ADCLEFT (1<<18)
611 #define FXWC_CDROMSPDIFLEFT (1<<18)
612 #define FXWC_ADCRIGHT (1<<19)
613 #define FXWC_CDROMSPDIFRIGHT (1<<19)
614 #define FXWC_MIC (1<<20)
615 #define FXWC_ZOOMLEFT (1<<20)
616 #define FXWC_ZOOMRIGHT (1<<21)
617 #define FXWC_SPDIFLEFT (1<<22) /* 0x00400000 */
618 #define FXWC_SPDIFRIGHT (1<<23) /* 0x00800000 */
619
620 #define A_TBLSZ 0x43 /* Effects Tank Internal Table Size. Only low byte or register used */
621
622 #define TCBS 0x44 /* Tank cache buffer size register */
623 #define TCBS_MASK 0x00000007 /* Tank cache buffer size field */
624 #define TCBS_BUFFSIZE_16K 0x00000000
625 #define TCBS_BUFFSIZE_32K 0x00000001
626 #define TCBS_BUFFSIZE_64K 0x00000002
627 #define TCBS_BUFFSIZE_128K 0x00000003
628 #define TCBS_BUFFSIZE_256K 0x00000004
629 #define TCBS_BUFFSIZE_512K 0x00000005
630 #define TCBS_BUFFSIZE_1024K 0x00000006
631 #define TCBS_BUFFSIZE_2048K 0x00000007
632
633 #define MICBA 0x45 /* AC97 microphone buffer address register */
634 #define MICBA_MASK 0xfffff000 /* 20 bit base address */
635
636 #define ADCBA 0x46 /* ADC buffer address register */
637 #define ADCBA_MASK 0xfffff000 /* 20 bit base address */
638
639 #define FXBA 0x47 /* FX Buffer Address */
640 #define FXBA_MASK 0xfffff000 /* 20 bit base address */
641
642 #define A_HWM 0x48 /* High PCI Water Mark - word access, defaults to 3f */
643
644 #define MICBS 0x49 /* Microphone buffer size register */
645
646 #define ADCBS 0x4a /* ADC buffer size register */
647
648 #define FXBS 0x4b /* FX buffer size register */
649
650 /* register: 0x4c..4f: ffff-ffff current amounts, per-channel */
651
652 /* The following mask values define the size of the ADC, MIX and FX buffers in bytes */
653 #define ADCBS_BUFSIZE_NONE 0x00000000
654 #define ADCBS_BUFSIZE_384 0x00000001
655 #define ADCBS_BUFSIZE_448 0x00000002
656 #define ADCBS_BUFSIZE_512 0x00000003
657 #define ADCBS_BUFSIZE_640 0x00000004
658 #define ADCBS_BUFSIZE_768 0x00000005
659 #define ADCBS_BUFSIZE_896 0x00000006
660 #define ADCBS_BUFSIZE_1024 0x00000007
661 #define ADCBS_BUFSIZE_1280 0x00000008
662 #define ADCBS_BUFSIZE_1536 0x00000009
663 #define ADCBS_BUFSIZE_1792 0x0000000a
664 #define ADCBS_BUFSIZE_2048 0x0000000b
665 #define ADCBS_BUFSIZE_2560 0x0000000c
666 #define ADCBS_BUFSIZE_3072 0x0000000d
667 #define ADCBS_BUFSIZE_3584 0x0000000e
668 #define ADCBS_BUFSIZE_4096 0x0000000f
669 #define ADCBS_BUFSIZE_5120 0x00000010
670 #define ADCBS_BUFSIZE_6144 0x00000011
671 #define ADCBS_BUFSIZE_7168 0x00000012
672 #define ADCBS_BUFSIZE_8192 0x00000013
673 #define ADCBS_BUFSIZE_10240 0x00000014
674 #define ADCBS_BUFSIZE_12288 0x00000015
675 #define ADCBS_BUFSIZE_14366 0x00000016
676 #define ADCBS_BUFSIZE_16384 0x00000017
677 #define ADCBS_BUFSIZE_20480 0x00000018
678 #define ADCBS_BUFSIZE_24576 0x00000019
679 #define ADCBS_BUFSIZE_28672 0x0000001a
680 #define ADCBS_BUFSIZE_32768 0x0000001b
681 #define ADCBS_BUFSIZE_40960 0x0000001c
682 #define ADCBS_BUFSIZE_49152 0x0000001d
683 #define ADCBS_BUFSIZE_57344 0x0000001e
684 #define ADCBS_BUFSIZE_65536 0x0000001f
685
686 /* Current Send B, A Amounts */
687 #define A_CSBA 0x4c
688
689 /* Current Send D, C Amounts */
690 #define A_CSDC 0x4d
691
692 /* Current Send F, E Amounts */
693 #define A_CSFE 0x4e
694
695 /* Current Send H, G Amounts */
696 #define A_CSHG 0x4f
697
698
699 #define CDCS 0x50 /* CD-ROM digital channel status register */
700
701 #define GPSCS 0x51 /* General Purpose SPDIF channel status register*/
702
703 #define DBG 0x52 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
704
705 /* S/PDIF Input C Channel Status */
706 #define A_SPSC 0x52
707
708 #define REG53 0x53 /* DO NOT PROGRAM THIS REGISTER!!! MAY DESTROY CHIP */
709
710 #define A_DBG 0x53
711 #define A_DBG_SINGLE_STEP 0x00020000 /* Set to zero to start dsp */
712 #define A_DBG_ZC 0x40000000 /* zero tram counter */
713 #define A_DBG_STEP_ADDR 0x000003ff
714 #define A_DBG_SATURATION_OCCURED 0x20000000
715 #define A_DBG_SATURATION_ADDR 0x0ffc0000
716
717 // NOTE: 0x54,55,56: 64-bit
718 #define SPCS0 0x54 /* SPDIF output Channel Status 0 register */
719
720 #define SPCS1 0x55 /* SPDIF output Channel Status 1 register */
721
722 #define SPCS2 0x56 /* SPDIF output Channel Status 2 register */
723
724 #define SPCS_CLKACCYMASK 0x30000000 /* Clock accuracy */
725 #define SPCS_CLKACCY_1000PPM 0x00000000 /* 1000 parts per million */
726 #define SPCS_CLKACCY_50PPM 0x10000000 /* 50 parts per million */
727 #define SPCS_CLKACCY_VARIABLE 0x20000000 /* Variable accuracy */
728 #define SPCS_SAMPLERATEMASK 0x0f000000 /* Sample rate */
729 #define SPCS_SAMPLERATE_44 0x00000000 /* 44.1kHz sample rate */
730 #define SPCS_SAMPLERATE_48 0x02000000 /* 48kHz sample rate */
731 #define SPCS_SAMPLERATE_32 0x03000000 /* 32kHz sample rate */
732 #define SPCS_CHANNELNUMMASK 0x00f00000 /* Channel number */
733 #define SPCS_CHANNELNUM_UNSPEC 0x00000000 /* Unspecified channel number */
734 #define SPCS_CHANNELNUM_LEFT 0x00100000 /* Left channel */
735 #define SPCS_CHANNELNUM_RIGHT 0x00200000 /* Right channel */
736 #define SPCS_SOURCENUMMASK 0x000f0000 /* Source number */
737 #define SPCS_SOURCENUM_UNSPEC 0x00000000 /* Unspecified source number */
738 #define SPCS_GENERATIONSTATUS 0x00008000 /* Originality flag (see IEC-958 spec) */
739 #define SPCS_CATEGORYCODEMASK 0x00007f00 /* Category code (see IEC-958 spec) */
740 #define SPCS_MODEMASK 0x000000c0 /* Mode (see IEC-958 spec) */
741 #define SPCS_EMPHASISMASK 0x00000038 /* Emphasis */
742 #define SPCS_EMPHASIS_NONE 0x00000000 /* No emphasis */
743 #define SPCS_EMPHASIS_50_15 0x00000008 /* 50/15 usec 2 channel */
744 #define SPCS_COPYRIGHT 0x00000004 /* Copyright asserted flag -- do not modify */
745 #define SPCS_NOTAUDIODATA 0x00000002 /* 0 = Digital audio, 1 = not audio */
746 #define SPCS_PROFESSIONAL 0x00000001 /* 0 = Consumer (IEC-958), 1 = pro (AES3-1992) */
747
748 /* 0x57: Not used */
749
750 /* The 32-bit CLIx and SOLx registers all have one bit per channel control/status */
751 #define CLIEL 0x58 /* Channel loop interrupt enable low register */
752
753 #define CLIEH 0x59 /* Channel loop interrupt enable high register */
754
755 #define CLIPL 0x5a /* Channel loop interrupt pending low register */
756
757 #define CLIPH 0x5b /* Channel loop interrupt pending high register */
758
759 #define SOLEL 0x5c /* Stop on loop enable low register */
760
761 #define SOLEH 0x5d /* Stop on loop enable high register */
762
763 #define SPBYPASS 0x5e /* SPDIF BYPASS mode register */
764 #define SPBYPASS_SPDIF0_MASK 0x00000003 /* SPDIF 0 bypass mode */
765 #define SPBYPASS_SPDIF1_MASK 0x0000000c /* SPDIF 1 bypass mode */
766 /* bypass mode: 0 - DSP; 1 - SPDIF A, 2 - SPDIF B, 3 - SPDIF C */
767 #define SPBYPASS_FORMAT 0x00000f00 /* If 1, SPDIF XX uses 24 bit, if 0 - 20 bit */
768
769 #define AC97SLOT 0x5f /* additional AC97 slots enable bits */
770 #define AC97SLOT_REAR_RIGHT 0x01 /* Rear left */
771 #define AC97SLOT_REAR_LEFT 0x02 /* Rear right */
772 #define AC97SLOT_CNTR 0x10 /* Center enable */
773 #define AC97SLOT_LFE 0x20 /* LFE enable */
774
775 /* PCB Revision */
776 #define A_PCB 0x5f
777
778 // NOTE: 0x60,61,62: 64-bit
779 #define CDSRCS 0x60 /* CD-ROM Sample Rate Converter status register */
780
781 #define GPSRCS 0x61 /* General Purpose SPDIF sample rate cvt status */
782
783 #define ZVSRCS 0x62 /* ZVideo sample rate converter status */
784 /* NOTE: This one has no SPDIFLOCKED field */
785 /* Assumes sample lock */
786
787 /* These three bitfields apply to CDSRCS, GPSRCS, and (except as noted) ZVSRCS. */
788 #define SRCS_SPDIFVALID 0x04000000 /* SPDIF stream valid */
789 #define SRCS_SPDIFLOCKED 0x02000000 /* SPDIF stream locked */
790 #define SRCS_RATELOCKED 0x01000000 /* Sample rate locked */
791 #define SRCS_ESTSAMPLERATE 0x0007ffff /* Do not modify this field. */
792
793 /* Note that these values can vary +/- by a small amount */
794 #define SRCS_SPDIFRATE_44 0x0003acd9
795 #define SRCS_SPDIFRATE_48 0x00040000
796 #define SRCS_SPDIFRATE_96 0x00080000
797
798 #define MICIDX 0x63 /* Microphone recording buffer index register */
799 #define MICIDX_MASK 0x0000ffff /* 16-bit value */
800 #define MICIDX_IDX 0x10000063
801
802 #define ADCIDX 0x64 /* ADC recording buffer index register */
803 #define ADCIDX_MASK 0x0000ffff /* 16 bit index field */
804 #define ADCIDX_IDX 0x10000064
805
806 #define A_ADCIDX 0x63
807 #define A_ADCIDX_IDX 0x10000063
808
809 #define A_MICIDX 0x64
810 #define A_MICIDX_IDX 0x10000064
811
812 #define FXIDX 0x65 /* FX recording buffer index register */
813 #define FXIDX_MASK 0x0000ffff /* 16-bit value */
814 #define FXIDX_IDX 0x10000065
815
816 /* The 32-bit HLIx and HLIPx registers all have one bit per channel control/status */
817 #define HLIEL 0x66 /* Channel half loop interrupt enable low register */
818
819 #define HLIEH 0x67 /* Channel half loop interrupt enable high register */
820
821 #define HLIPL 0x68 /* Channel half loop interrupt pending low register */
822
823 #define HLIPH 0x69 /* Channel half loop interrupt pending high register */
824
825 /* S/PDIF Host Record Index (bypasses SRC) */
826 #define A_SPRI 0x6a
827 /* S/PDIF Host Record Address */
828 #define A_SPRA 0x6b
829 /* S/PDIF Host Record Control */
830 #define A_SPRC 0x6c
831 /* Delayed Interrupt Counter & Enable */
832 #define A_DICE 0x6d
833 /* Tank Table Base */
834 #define A_TTB 0x6e
835 /* Tank Delay Offset */
836 #define A_TDOF 0x6f
837
838 /* This is the MPU port on the card (via the game port) */
839 #define A_MUDATA1 0x70
840 #define A_MUCMD1 0x71
841 #define A_MUSTAT1 A_MUCMD1
842
843 /* This is the MPU port on the Audigy Drive */
844 #define A_MUDATA2 0x72
845 #define A_MUCMD2 0x73
846 #define A_MUSTAT2 A_MUCMD2
847
848 /* The next two are the Audigy equivalent of FXWC */
849 /* the Audigy can record any output (16bit, 48kHz, up to 64 channel simultaneously) */
850 /* Each bit selects a channel for recording */
851 #define A_FXWC1 0x74 /* Selects 0x7f-0x60 for FX recording */
852 #define A_FXWC2 0x75 /* Selects 0x9f-0x80 for FX recording */
853
854 /* Extended Hardware Control */
855 #define A_SPDIF_SAMPLERATE 0x76 /* Set the sample rate of SPDIF output */
856 #define A_SAMPLE_RATE 0x76 /* Various sample rate settings. */
857 #define A_SAMPLE_RATE_NOT_USED 0x0ffc111e /* Bits that are not used and cannot be set. */
858 #define A_SAMPLE_RATE_UNKNOWN 0xf0030001 /* Bits that can be set, but have unknown use. */
859 #define A_SPDIF_RATE_MASK 0x000000e0 /* Any other values for rates, just use 48000 */
860 #define A_SPDIF_48000 0x00000000
861 #define A_SPDIF_192000 0x00000020
862 #define A_SPDIF_96000 0x00000040
863 #define A_SPDIF_44100 0x00000080
864
865 #define A_I2S_CAPTURE_RATE_MASK 0x00000e00 /* This sets the capture PCM rate, but it is */
866 #define A_I2S_CAPTURE_48000 0x00000000 /* unclear if this sets the ADC rate as well. */
867 #define A_I2S_CAPTURE_192000 0x00000200
868 #define A_I2S_CAPTURE_96000 0x00000400
869 #define A_I2S_CAPTURE_44100 0x00000800
870
871 #define A_PCM_RATE_MASK 0x0000e000 /* This sets the playback PCM rate on the P16V */
872 #define A_PCM_48000 0x00000000
873 #define A_PCM_192000 0x00002000
874 #define A_PCM_96000 0x00004000
875 #define A_PCM_44100 0x00008000
876
877 /* I2S0 Sample Rate Tracker Status */
878 #define A_SRT3 0x77
879
880 /* I2S1 Sample Rate Tracker Status */
881 #define A_SRT4 0x78
882
883 /* I2S2 Sample Rate Tracker Status */
884 #define A_SRT5 0x79
885 /* - default to 0x01080000 on my audigy 2 ZS --rlrevell */
886
887 /* Tank Table DMA Address */
888 #define A_TTDA 0x7a
889 /* Tank Table DMA Data */
890 #define A_TTDD 0x7b
891
892 #define A_FXRT2 0x7c
893 #define A_FXRT_CHANNELE 0x0000003f /* Effects send bus number for channel's effects send E */
894 #define A_FXRT_CHANNELF 0x00003f00 /* Effects send bus number for channel's effects send F */
895 #define A_FXRT_CHANNELG 0x003f0000 /* Effects send bus number for channel's effects send G */
896 #define A_FXRT_CHANNELH 0x3f000000 /* Effects send bus number for channel's effects send H */
897
898 #define A_SENDAMOUNTS 0x7d
899 #define A_FXSENDAMOUNT_E_MASK 0xFF000000
900 #define A_FXSENDAMOUNT_F_MASK 0x00FF0000
901 #define A_FXSENDAMOUNT_G_MASK 0x0000FF00
902 #define A_FXSENDAMOUNT_H_MASK 0x000000FF
903 /* 0x7c, 0x7e "high bit is used for filtering" */
904
905 /* The send amounts for this one are the same as used with the emu10k1 */
906 #define A_FXRT1 0x7e
907 #define A_FXRT_CHANNELA 0x0000003f
908 #define A_FXRT_CHANNELB 0x00003f00
909 #define A_FXRT_CHANNELC 0x003f0000
910 #define A_FXRT_CHANNELD 0x3f000000
911
912 /* 0x7f: Not used */
913 /* Each FX general purpose register is 32 bits in length, all bits are used */
914 #define FXGPREGBASE 0x100 /* FX general purpose registers base */
915 #define A_FXGPREGBASE 0x400 /* Audigy GPRs, 0x400 to 0x5ff */
916
917 #define A_TANKMEMCTLREGBASE 0x100 /* Tank memory control registers base - only for Audigy */
918 #define A_TANKMEMCTLREG_MASK 0x1f /* only 5 bits used - only for Audigy */
919
920 /* Tank audio data is logarithmically compressed down to 16 bits before writing to TRAM and is */
921 /* decompressed back to 20 bits on a read. There are a total of 160 locations, the last 32 */
922 /* locations are for external TRAM. */
923 #define TANKMEMDATAREGBASE 0x200 /* Tank memory data registers base */
924 #define TANKMEMDATAREG_MASK 0x000fffff /* 20 bit tank audio data field */
925
926 /* Combined address field and memory opcode or flag field. 160 locations, last 32 are external */
927 #define TANKMEMADDRREGBASE 0x300 /* Tank memory address registers base */
928 #define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */
929 #define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */
930 #define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */
931 #define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */
932 #define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */
933
934 #define MICROCODEBASE 0x400 /* Microcode data base address */
935
936 /* Each DSP microcode instruction is mapped into 2 doublewords */
937 /* NOTE: When writing, always write the LO doubleword first. Reads can be in either order. */
938 #define LOWORD_OPX_MASK 0x000ffc00 /* Instruction operand X */
939 #define LOWORD_OPY_MASK 0x000003ff /* Instruction operand Y */
940 #define HIWORD_OPCODE_MASK 0x00f00000 /* Instruction opcode */
941 #define HIWORD_RESULT_MASK 0x000ffc00 /* Instruction result */
942 #define HIWORD_OPA_MASK 0x000003ff /* Instruction operand A */
943
944
945 /* Audigy Soundcard have a different instruction format */
946 #define A_MICROCODEBASE 0x600
947 #define A_LOWORD_OPY_MASK 0x000007ff
948 #define A_LOWORD_OPX_MASK 0x007ff000
949 #define A_HIWORD_OPCODE_MASK 0x0f000000
950 #define A_HIWORD_RESULT_MASK 0x007ff000
951 #define A_HIWORD_OPA_MASK 0x000007ff
952
953 /************************************************************************************************/
954 /* EMU1010m HANA FPGA registers */
955 /************************************************************************************************/
956 #define EMU_HANA_DESTHI 0x00 /* 0000xxx 3 bits Link Destination */
957 #define EMU_HANA_DESTLO 0x01 /* 00xxxxx 5 bits */
958 #define EMU_HANA_SRCHI 0x02 /* 0000xxx 3 bits Link Source */
959 #define EMU_HANA_SRCLO 0x03 /* 00xxxxx 5 bits */
960 #define EMU_HANA_DOCK_PWR 0x04 /* 000000x 1 bits Audio Dock power */
961 #define EMU_HANA_DOCK_PWR_ON 0x01 /* Audio Dock power on */
962 #define EMU_HANA_WCLOCK 0x05 /* 0000xxx 3 bits Word Clock source select */
963 /* Must be written after power on to reset DLL */
964 /* One is unable to detect the Audio dock without this */
965 #define EMU_HANA_WCLOCK_SRC_MASK 0x07
966 #define EMU_HANA_WCLOCK_INT_48K 0x00
967 #define EMU_HANA_WCLOCK_INT_44_1K 0x01
968 #define EMU_HANA_WCLOCK_HANA_SPDIF_IN 0x02
969 #define EMU_HANA_WCLOCK_HANA_ADAT_IN 0x03
970 #define EMU_HANA_WCLOCK_SYNC_BNCN 0x04
971 #define EMU_HANA_WCLOCK_2ND_HANA 0x05
972 #define EMU_HANA_WCLOCK_SRC_RESERVED 0x06
973 #define EMU_HANA_WCLOCK_OFF 0x07 /* For testing, forces fallback to DEFCLOCK */
974 #define EMU_HANA_WCLOCK_MULT_MASK 0x18
975 #define EMU_HANA_WCLOCK_1X 0x00
976 #define EMU_HANA_WCLOCK_2X 0x08
977 #define EMU_HANA_WCLOCK_4X 0x10
978 #define EMU_HANA_WCLOCK_MULT_RESERVED 0x18
979
980 #define EMU_HANA_DEFCLOCK 0x06 /* 000000x 1 bits Default Word Clock */
981 #define EMU_HANA_DEFCLOCK_48K 0x00
982 #define EMU_HANA_DEFCLOCK_44_1K 0x01
983
984 #define EMU_HANA_UNMUTE 0x07 /* 000000x 1 bits Mute all audio outputs */
985 #define EMU_MUTE 0x00
986 #define EMU_UNMUTE 0x01
987
988 #define EMU_HANA_FPGA_CONFIG 0x08 /* 00000xx 2 bits Config control of FPGAs */
989 #define EMU_HANA_FPGA_CONFIG_AUDIODOCK 0x01 /* Set in order to program FPGA on Audio Dock */
990 #define EMU_HANA_FPGA_CONFIG_HANA 0x02 /* Set in order to program FPGA on Hana */
991
992 #define EMU_HANA_IRQ_ENABLE 0x09 /* 000xxxx 4 bits IRQ Enable */
993 #define EMU_HANA_IRQ_WCLK_CHANGED 0x01
994 #define EMU_HANA_IRQ_ADAT 0x02
995 #define EMU_HANA_IRQ_DOCK 0x04
996 #define EMU_HANA_IRQ_DOCK_LOST 0x08
997
998 #define EMU_HANA_SPDIF_MODE 0x0a /* 00xxxxx 5 bits SPDIF MODE */
999 #define EMU_HANA_SPDIF_MODE_TX_COMSUMER 0x00
1000 #define EMU_HANA_SPDIF_MODE_TX_PRO 0x01
1001 #define EMU_HANA_SPDIF_MODE_TX_NOCOPY 0x02
1002 #define EMU_HANA_SPDIF_MODE_RX_COMSUMER 0x00
1003 #define EMU_HANA_SPDIF_MODE_RX_PRO 0x04
1004 #define EMU_HANA_SPDIF_MODE_RX_NOCOPY 0x08
1005 #define EMU_HANA_SPDIF_MODE_RX_INVALID 0x10
1006
1007 #define EMU_HANA_OPTICAL_TYPE 0x0b /* 00000xx 2 bits ADAT or SPDIF in/out */
1008 #define EMU_HANA_OPTICAL_IN_SPDIF 0x00
1009 #define EMU_HANA_OPTICAL_IN_ADAT 0x01
1010 #define EMU_HANA_OPTICAL_OUT_SPDIF 0x00
1011 #define EMU_HANA_OPTICAL_OUT_ADAT 0x02
1012
1013 #define EMU_HANA_MIDI_IN 0x0c /* 000000x 1 bit Control MIDI */
1014 #define EMU_HANA_MIDI_IN_FROM_HAMOA 0x00 /* HAMOA MIDI in to Alice 2 MIDI B */
1015 #define EMU_HANA_MIDI_IN_FROM_DOCK 0x01 /* Audio Dock MIDI in to Alice 2 MIDI B */
1016
1017 #define EMU_HANA_DOCK_LEDS_1 0x0d /* 000xxxx 4 bit Audio Dock LEDs */
1018 #define EMU_HANA_DOCK_LEDS_1_MIDI1 0x01 /* MIDI 1 LED on */
1019 #define EMU_HANA_DOCK_LEDS_1_MIDI2 0x02 /* MIDI 2 LED on */
1020 #define EMU_HANA_DOCK_LEDS_1_SMPTE_IN 0x04 /* SMPTE IN LED on */
1021 #define EMU_HANA_DOCK_LEDS_1_SMPTE_OUT 0x08 /* SMPTE OUT LED on */
1022
1023 #define EMU_HANA_DOCK_LEDS_2 0x0e /* 0xxxxxx 6 bit Audio Dock LEDs */
1024 #define EMU_HANA_DOCK_LEDS_2_44K 0x01 /* 44.1 kHz LED on */
1025 #define EMU_HANA_DOCK_LEDS_2_48K 0x02 /* 48 kHz LED on */
1026 #define EMU_HANA_DOCK_LEDS_2_96K 0x04 /* 96 kHz LED on */
1027 #define EMU_HANA_DOCK_LEDS_2_192K 0x08 /* 192 kHz LED on */
1028 #define EMU_HANA_DOCK_LEDS_2_LOCK 0x10 /* LOCK LED on */
1029 #define EMU_HANA_DOCK_LEDS_2_EXT 0x20 /* EXT LED on */
1030
1031 #define EMU_HANA_DOCK_LEDS_3 0x0f /* 0xxxxxx 6 bit Audio Dock LEDs */
1032 #define EMU_HANA_DOCK_LEDS_3_CLIP_A 0x01 /* Mic A Clip LED on */
1033 #define EMU_HANA_DOCK_LEDS_3_CLIP_B 0x02 /* Mic B Clip LED on */
1034 #define EMU_HANA_DOCK_LEDS_3_SIGNAL_A 0x04 /* Signal A Clip LED on */
1035 #define EMU_HANA_DOCK_LEDS_3_SIGNAL_B 0x08 /* Signal B Clip LED on */
1036 #define EMU_HANA_DOCK_LEDS_3_MANUAL_CLIP 0x10 /* Manual Clip detection */
1037 #define EMU_HANA_DOCK_LEDS_3_MANUAL_SIGNAL 0x20 /* Manual Signal detection */
1038
1039 #define EMU_HANA_ADC_PADS 0x10 /* 0000xxx 3 bit Audio Dock ADC 14dB pads */
1040 #define EMU_HANA_DOCK_ADC_PAD1 0x01 /* 14dB Attenuation on Audio Dock ADC 1 */
1041 #define EMU_HANA_DOCK_ADC_PAD2 0x02 /* 14dB Attenuation on Audio Dock ADC 2 */
1042 #define EMU_HANA_DOCK_ADC_PAD3 0x04 /* 14dB Attenuation on Audio Dock ADC 3 */
1043 #define EMU_HANA_0202_ADC_PAD1 0x08 /* 14dB Attenuation on 0202 ADC 1 */
1044
1045 #define EMU_HANA_DOCK_MISC 0x11 /* 0xxxxxx 6 bit Audio Dock misc bits */
1046 #define EMU_HANA_DOCK_DAC1_MUTE 0x01 /* DAC 1 Mute */
1047 #define EMU_HANA_DOCK_DAC2_MUTE 0x02 /* DAC 2 Mute */
1048 #define EMU_HANA_DOCK_DAC3_MUTE 0x04 /* DAC 3 Mute */
1049 #define EMU_HANA_DOCK_DAC4_MUTE 0x08 /* DAC 4 Mute */
1050 #define EMU_HANA_DOCK_PHONES_192_DAC1 0x00 /* DAC 1 Headphones source at 192kHz */
1051 #define EMU_HANA_DOCK_PHONES_192_DAC2 0x10 /* DAC 2 Headphones source at 192kHz */
1052 #define EMU_HANA_DOCK_PHONES_192_DAC3 0x20 /* DAC 3 Headphones source at 192kHz */
1053 #define EMU_HANA_DOCK_PHONES_192_DAC4 0x30 /* DAC 4 Headphones source at 192kHz */
1054
1055 #define EMU_HANA_MIDI_OUT 0x12 /* 00xxxxx 5 bit Source for each MIDI out port */
1056 #define EMU_HANA_MIDI_OUT_0202 0x01 /* 0202 MIDI from Alice 2. 0 = A, 1 = B */
1057 #define EMU_HANA_MIDI_OUT_DOCK1 0x02 /* Audio Dock MIDI1 front, from Alice 2. 0 = A, 1 = B */
1058 #define EMU_HANA_MIDI_OUT_DOCK2 0x04 /* Audio Dock MIDI2 rear, from Alice 2. 0 = A, 1 = B */
1059 #define EMU_HANA_MIDI_OUT_SYNC2 0x08 /* Sync card. Not the actual MIDI out jack. 0 = A, 1 = B */
1060 #define EMU_HANA_MIDI_OUT_LOOP 0x10 /* 0 = bits (3:0) normal. 1 = MIDI loopback enabled. */
1061
1062 #define EMU_HANA_DAC_PADS 0x13 /* 00xxxxx 5 bit DAC 14dB attenuation pads */
1063 #define EMU_HANA_DOCK_DAC_PAD1 0x01 /* 14dB Attenuation on AudioDock DAC 1. Left and Right */
1064 #define EMU_HANA_DOCK_DAC_PAD2 0x02 /* 14dB Attenuation on AudioDock DAC 2. Left and Right */
1065 #define EMU_HANA_DOCK_DAC_PAD3 0x04 /* 14dB Attenuation on AudioDock DAC 3. Left and Right */
1066 #define EMU_HANA_DOCK_DAC_PAD4 0x08 /* 14dB Attenuation on AudioDock DAC 4. Left and Right */
1067 #define EMU_HANA_0202_DAC_PAD1 0x10 /* 14dB Attenuation on 0202 DAC 1. Left and Right */
1068
1069 /* 0x14 - 0x1f Unused R/W registers */
1070 #define EMU_HANA_IRQ_STATUS 0x20 /* 000xxxx 4 bits IRQ Status */
1071 #if 0 /* Already defined for reg 0x09 IRQ_ENABLE */
1072 #define EMU_HANA_IRQ_WCLK_CHANGED 0x01
1073 #define EMU_HANA_IRQ_ADAT 0x02
1074 #define EMU_HANA_IRQ_DOCK 0x04
1075 #define EMU_HANA_IRQ_DOCK_LOST 0x08
1076 #endif
1077
1078 #define EMU_HANA_OPTION_CARDS 0x21 /* 000xxxx 4 bits Presence of option cards */
1079 #define EMU_HANA_OPTION_HAMOA 0x01 /* HAMOA card present */
1080 #define EMU_HANA_OPTION_SYNC 0x02 /* Sync card present */
1081 #define EMU_HANA_OPTION_DOCK_ONLINE 0x04 /* Audio Dock online and FPGA configured */
1082 #define EMU_HANA_OPTION_DOCK_OFFLINE 0x08 /* Audio Dock online and FPGA not configured */
1083
1084 #define EMU_HANA_ID 0x22 /* 1010101 7 bits ID byte & 0x7f = 0x55 */
1085
1086 #define EMU_HANA_MAJOR_REV 0x23 /* 0000xxx 3 bit Hana FPGA Major rev */
1087 #define EMU_HANA_MINOR_REV 0x24 /* 0000xxx 3 bit Hana FPGA Minor rev */
1088
1089 #define EMU_DOCK_MAJOR_REV 0x25 /* 0000xxx 3 bit Audio Dock FPGA Major rev */
1090 #define EMU_DOCK_MINOR_REV 0x26 /* 0000xxx 3 bit Audio Dock FPGA Minor rev */
1091
1092 #define EMU_DOCK_BOARD_ID 0x27 /* 00000xx 2 bits Audio Dock ID pins */
1093 #define EMU_DOCK_BOARD_ID0 0x00 /* ID bit 0 */
1094 #define EMU_DOCK_BOARD_ID1 0x03 /* ID bit 1 */
1095
1096 #define EMU_HANA_WC_SPDIF_HI 0x28 /* 0xxxxxx 6 bit SPDIF IN Word clock, upper 6 bits */
1097 #define EMU_HANA_WC_SPDIF_LO 0x29 /* 0xxxxxx 6 bit SPDIF IN Word clock, lower 6 bits */
1098
1099 #define EMU_HANA_WC_ADAT_HI 0x2a /* 0xxxxxx 6 bit ADAT IN Word clock, upper 6 bits */
1100 #define EMU_HANA_WC_ADAT_LO 0x2b /* 0xxxxxx 6 bit ADAT IN Word clock, lower 6 bits */
1101
1102 #define EMU_HANA_WC_BNC_LO 0x2c /* 0xxxxxx 6 bit BNC IN Word clock, lower 6 bits */
1103 #define EMU_HANA_WC_BNC_HI 0x2d /* 0xxxxxx 6 bit BNC IN Word clock, upper 6 bits */
1104
1105 #define EMU_HANA2_WC_SPDIF_HI 0x2e /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, upper 6 bits */
1106 #define EMU_HANA2_WC_SPDIF_LO 0x2f /* 0xxxxxx 6 bit HANA2 SPDIF IN Word clock, lower 6 bits */
1107 /* 0x30 - 0x3f Unused Read only registers */
1108
1109 /************************************************************************************************/
1110 /* EMU1010m HANA Destinations */
1111 /************************************************************************************************/
1112 /* Hana, original 1010,1212,1820 using Alice2
1113 * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1114 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1115 * 0x01, 0x10-0x1f: 32 Elink channels to Audio Dock
1116 * 0x01, 0x00: Dock DAC 1 Left
1117 * 0x01, 0x04: Dock DAC 1 Right
1118 * 0x01, 0x08: Dock DAC 2 Left
1119 * 0x01, 0x0c: Dock DAC 2 Right
1120 * 0x01, 0x10: Dock DAC 3 Left
1121 * 0x01, 0x12: PHONES Left
1122 * 0x01, 0x14: Dock DAC 3 Right
1123 * 0x01, 0x16: PHONES Right
1124 * 0x01, 0x18: Dock DAC 4 Left
1125 * 0x01, 0x1a: S/PDIF Left
1126 * 0x01, 0x1c: Dock DAC 4 Right
1127 * 0x01, 0x1e: S/PDIF Right
1128 * 0x02, 0x00: Hana S/PDIF Left
1129 * 0x02, 0x01: Hana S/PDIF Right
1130 * 0x03, 0x00: Hanoa DAC Left
1131 * 0x03, 0x01: Hanoa DAC Right
1132 * 0x04, 0x00-0x07: Hana ADAT
1133 * 0x05, 0x00: I2S0 Left to Alice2
1134 * 0x05, 0x01: I2S0 Right to Alice2
1135 * 0x06, 0x00: I2S0 Left to Alice2
1136 * 0x06, 0x01: I2S0 Right to Alice2
1137 * 0x07, 0x00: I2S0 Left to Alice2
1138 * 0x07, 0x01: I2S0 Right to Alice2
1139 *
1140 * Hana2 never released, but used Tina
1141 * Not needed.
1142 *
1143 * Hana3, rev2 1010,1212,1616 using Tina
1144 * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1145 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina
1146 * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock
1147 * 0x01, 0x00: Dock DAC 1 Left
1148 * 0x01, 0x04: Dock DAC 1 Right
1149 * 0x01, 0x08: Dock DAC 2 Left
1150 * 0x01, 0x0c: Dock DAC 2 Right
1151 * 0x01, 0x10: Dock DAC 3 Left
1152 * 0x01, 0x12: Dock S/PDIF Left
1153 * 0x01, 0x14: Dock DAC 3 Right
1154 * 0x01, 0x16: Dock S/PDIF Right
1155 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1156 * 0x02, 0x00: Hana3 S/PDIF Left
1157 * 0x02, 0x01: Hana3 S/PDIF Right
1158 * 0x03, 0x00: Hanoa DAC Left
1159 * 0x03, 0x01: Hanoa DAC Right
1160 * 0x04, 0x00-0x07: Hana3 ADAT 0-7
1161 * 0x05, 0x00-0x0f: 16 EMU32B channels to Tina
1162 * 0x06-0x07: Not used
1163 *
1164 * HanaLite, rev1 0404 using Alice2
1165 * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1166 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1167 * 0x01: Not used
1168 * 0x02, 0x00: S/PDIF Left
1169 * 0x02, 0x01: S/PDIF Right
1170 * 0x03, 0x00: DAC Left
1171 * 0x03, 0x01: DAC Right
1172 * 0x04-0x07: Not used
1173 *
1174 * HanaLiteLite, rev2 0404 using Alice2
1175 * Destiniations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1176 * 0x00, 0x00-0x0f: 16 EMU32 channels to Alice2
1177 * 0x01: Not used
1178 * 0x02, 0x00: S/PDIF Left
1179 * 0x02, 0x01: S/PDIF Right
1180 * 0x03, 0x00: DAC Left
1181 * 0x03, 0x01: DAC Right
1182 * 0x04-0x07: Not used
1183 *
1184 * Mana, Cardbus 1616 using Tina2
1185 * Destinations for SRATEX = 1X rates: 44.1 kHz or 48 kHz
1186 * 0x00, 0x00-0x0f: 16 EMU32A channels to Tina2
1187 * 0x01, 0x10-0x1f: 32 EDI channels to Micro Dock
1188 * 0x01, 0x00: Dock DAC 1 Left
1189 * 0x01, 0x04: Dock DAC 1 Right
1190 * 0x01, 0x08: Dock DAC 2 Left
1191 * 0x01, 0x0c: Dock DAC 2 Right
1192 * 0x01, 0x10: Dock DAC 3 Left
1193 * 0x01, 0x12: Dock S/PDIF Left
1194 * 0x01, 0x14: Dock DAC 3 Right
1195 * 0x01, 0x16: Dock S/PDIF Right
1196 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1197 * 0x02: Not used
1198 * 0x03, 0x00: Mana DAC Left
1199 * 0x03, 0x01: Mana DAC Right
1200 * 0x04, 0x00-0x0f: 16 EMU32B channels to Tina2
1201 * 0x05-0x07: Not used
1202 *
1203 *
1204 */
1205 /* 32-bit destinations of signal in the Hana FPGA. Destinations are either
1206 * physical outputs of Hana, or outputs going to Alice2 (audigy) for capture
1207 * - 16 x EMU_DST_ALICE2_EMU32_X.
1208 */
1209 /* EMU32 = 32-bit serial channel between Alice2 (audigy) and Hana (FPGA) */
1210 /* EMU_DST_ALICE2_EMU32_X - data channels from Hana to Alice2 used for capture.
1211 * Which data is fed into a EMU_DST_ALICE2_EMU32_X channel in Hana depends on
1212 * setup of mixer control for each destination - see emumixer.c -
1213 * snd_emu1010_output_enum_ctls[], snd_emu1010_input_enum_ctls[]
1214 */
1215 #define EMU_DST_ALICE2_EMU32_0 0x000f /* 16 EMU32 channels to Alice2 +0 to +0xf */
1216 #define EMU_DST_ALICE2_EMU32_1 0x0000 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1217 #define EMU_DST_ALICE2_EMU32_2 0x0001 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1218 #define EMU_DST_ALICE2_EMU32_3 0x0002 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1219 #define EMU_DST_ALICE2_EMU32_4 0x0003 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1220 #define EMU_DST_ALICE2_EMU32_5 0x0004 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1221 #define EMU_DST_ALICE2_EMU32_6 0x0005 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1222 #define EMU_DST_ALICE2_EMU32_7 0x0006 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1223 #define EMU_DST_ALICE2_EMU32_8 0x0007 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1224 #define EMU_DST_ALICE2_EMU32_9 0x0008 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1225 #define EMU_DST_ALICE2_EMU32_A 0x0009 /* 16 EMU32 channels to Alice2 +0 to +0xf */
1226 #define EMU_DST_ALICE2_EMU32_B 0x000a /* 16 EMU32 channels to Alice2 +0 to +0xf */
1227 #define EMU_DST_ALICE2_EMU32_C 0x000b /* 16 EMU32 channels to Alice2 +0 to +0xf */
1228 #define EMU_DST_ALICE2_EMU32_D 0x000c /* 16 EMU32 channels to Alice2 +0 to +0xf */
1229 #define EMU_DST_ALICE2_EMU32_E 0x000d /* 16 EMU32 channels to Alice2 +0 to +0xf */
1230 #define EMU_DST_ALICE2_EMU32_F 0x000e /* 16 EMU32 channels to Alice2 +0 to +0xf */
1231 #define EMU_DST_DOCK_DAC1_LEFT1 0x0100 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1232 #define EMU_DST_DOCK_DAC1_LEFT2 0x0101 /* Audio Dock DAC1 Left, 2nd or 96kHz */
1233 #define EMU_DST_DOCK_DAC1_LEFT3 0x0102 /* Audio Dock DAC1 Left, 3rd or 192kHz */
1234 #define EMU_DST_DOCK_DAC1_LEFT4 0x0103 /* Audio Dock DAC1 Left, 4th or 192kHz */
1235 #define EMU_DST_DOCK_DAC1_RIGHT1 0x0104 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1236 #define EMU_DST_DOCK_DAC1_RIGHT2 0x0105 /* Audio Dock DAC1 Right, 2nd or 96kHz */
1237 #define EMU_DST_DOCK_DAC1_RIGHT3 0x0106 /* Audio Dock DAC1 Right, 3rd or 192kHz */
1238 #define EMU_DST_DOCK_DAC1_RIGHT4 0x0107 /* Audio Dock DAC1 Right, 4th or 192kHz */
1239 #define EMU_DST_DOCK_DAC2_LEFT1 0x0108 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1240 #define EMU_DST_DOCK_DAC2_LEFT2 0x0109 /* Audio Dock DAC2 Left, 2nd or 96kHz */
1241 #define EMU_DST_DOCK_DAC2_LEFT3 0x010a /* Audio Dock DAC2 Left, 3rd or 192kHz */
1242 #define EMU_DST_DOCK_DAC2_LEFT4 0x010b /* Audio Dock DAC2 Left, 4th or 192kHz */
1243 #define EMU_DST_DOCK_DAC2_RIGHT1 0x010c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1244 #define EMU_DST_DOCK_DAC2_RIGHT2 0x010d /* Audio Dock DAC2 Right, 2nd or 96kHz */
1245 #define EMU_DST_DOCK_DAC2_RIGHT3 0x010e /* Audio Dock DAC2 Right, 3rd or 192kHz */
1246 #define EMU_DST_DOCK_DAC2_RIGHT4 0x010f /* Audio Dock DAC2 Right, 4th or 192kHz */
1247 #define EMU_DST_DOCK_DAC3_LEFT1 0x0110 /* Audio Dock DAC1 Left, 1st or 48kHz only */
1248 #define EMU_DST_DOCK_DAC3_LEFT2 0x0111 /* Audio Dock DAC1 Left, 2nd or 96kHz */
1249 #define EMU_DST_DOCK_DAC3_LEFT3 0x0112 /* Audio Dock DAC1 Left, 3rd or 192kHz */
1250 #define EMU_DST_DOCK_DAC3_LEFT4 0x0113 /* Audio Dock DAC1 Left, 4th or 192kHz */
1251 #define EMU_DST_DOCK_PHONES_LEFT1 0x0112 /* Audio Dock PHONES Left, 1st or 48kHz only */
1252 #define EMU_DST_DOCK_PHONES_LEFT2 0x0113 /* Audio Dock PHONES Left, 2nd or 96kHz */
1253 #define EMU_DST_DOCK_DAC3_RIGHT1 0x0114 /* Audio Dock DAC1 Right, 1st or 48kHz only */
1254 #define EMU_DST_DOCK_DAC3_RIGHT2 0x0115 /* Audio Dock DAC1 Right, 2nd or 96kHz */
1255 #define EMU_DST_DOCK_DAC3_RIGHT3 0x0116 /* Audio Dock DAC1 Right, 3rd or 192kHz */
1256 #define EMU_DST_DOCK_DAC3_RIGHT4 0x0117 /* Audio Dock DAC1 Right, 4th or 192kHz */
1257 #define EMU_DST_DOCK_PHONES_RIGHT1 0x0116 /* Audio Dock PHONES Right, 1st or 48kHz only */
1258 #define EMU_DST_DOCK_PHONES_RIGHT2 0x0117 /* Audio Dock PHONES Right, 2nd or 96kHz */
1259 #define EMU_DST_DOCK_DAC4_LEFT1 0x0118 /* Audio Dock DAC2 Left, 1st or 48kHz only */
1260 #define EMU_DST_DOCK_DAC4_LEFT2 0x0119 /* Audio Dock DAC2 Left, 2nd or 96kHz */
1261 #define EMU_DST_DOCK_DAC4_LEFT3 0x011a /* Audio Dock DAC2 Left, 3rd or 192kHz */
1262 #define EMU_DST_DOCK_DAC4_LEFT4 0x011b /* Audio Dock DAC2 Left, 4th or 192kHz */
1263 #define EMU_DST_DOCK_SPDIF_LEFT1 0x011a /* Audio Dock SPDIF Left, 1st or 48kHz only */
1264 #define EMU_DST_DOCK_SPDIF_LEFT2 0x011b /* Audio Dock SPDIF Left, 2nd or 96kHz */
1265 #define EMU_DST_DOCK_DAC4_RIGHT1 0x011c /* Audio Dock DAC2 Right, 1st or 48kHz only */
1266 #define EMU_DST_DOCK_DAC4_RIGHT2 0x011d /* Audio Dock DAC2 Right, 2nd or 96kHz */
1267 #define EMU_DST_DOCK_DAC4_RIGHT3 0x011e /* Audio Dock DAC2 Right, 3rd or 192kHz */
1268 #define EMU_DST_DOCK_DAC4_RIGHT4 0x011f /* Audio Dock DAC2 Right, 4th or 192kHz */
1269 #define EMU_DST_DOCK_SPDIF_RIGHT1 0x011e /* Audio Dock SPDIF Right, 1st or 48kHz only */
1270 #define EMU_DST_DOCK_SPDIF_RIGHT2 0x011f /* Audio Dock SPDIF Right, 2nd or 96kHz */
1271 #define EMU_DST_HANA_SPDIF_LEFT1 0x0200 /* Hana SPDIF Left, 1st or 48kHz only */
1272 #define EMU_DST_HANA_SPDIF_LEFT2 0x0202 /* Hana SPDIF Left, 2nd or 96kHz */
1273 #define EMU_DST_HANA_SPDIF_RIGHT1 0x0201 /* Hana SPDIF Right, 1st or 48kHz only */
1274 #define EMU_DST_HANA_SPDIF_RIGHT2 0x0203 /* Hana SPDIF Right, 2nd or 96kHz */
1275 #define EMU_DST_HAMOA_DAC_LEFT1 0x0300 /* Hamoa DAC Left, 1st or 48kHz only */
1276 #define EMU_DST_HAMOA_DAC_LEFT2 0x0302 /* Hamoa DAC Left, 2nd or 96kHz */
1277 #define EMU_DST_HAMOA_DAC_LEFT3 0x0304 /* Hamoa DAC Left, 3rd or 192kHz */
1278 #define EMU_DST_HAMOA_DAC_LEFT4 0x0306 /* Hamoa DAC Left, 4th or 192kHz */
1279 #define EMU_DST_HAMOA_DAC_RIGHT1 0x0301 /* Hamoa DAC Right, 1st or 48kHz only */
1280 #define EMU_DST_HAMOA_DAC_RIGHT2 0x0303 /* Hamoa DAC Right, 2nd or 96kHz */
1281 #define EMU_DST_HAMOA_DAC_RIGHT3 0x0305 /* Hamoa DAC Right, 3rd or 192kHz */
1282 #define EMU_DST_HAMOA_DAC_RIGHT4 0x0307 /* Hamoa DAC Right, 4th or 192kHz */
1283 #define EMU_DST_HANA_ADAT 0x0400 /* Hana ADAT 8 channel out +0 to +7 */
1284 #define EMU_DST_ALICE_I2S0_LEFT 0x0500 /* Alice2 I2S0 Left */
1285 #define EMU_DST_ALICE_I2S0_RIGHT 0x0501 /* Alice2 I2S0 Right */
1286 #define EMU_DST_ALICE_I2S1_LEFT 0x0600 /* Alice2 I2S1 Left */
1287 #define EMU_DST_ALICE_I2S1_RIGHT 0x0601 /* Alice2 I2S1 Right */
1288 #define EMU_DST_ALICE_I2S2_LEFT 0x0700 /* Alice2 I2S2 Left */
1289 #define EMU_DST_ALICE_I2S2_RIGHT 0x0701 /* Alice2 I2S2 Right */
1290
1291 /* Additional destinations for 1616(M)/Microdock */
1292 /* Microdock S/PDIF OUT Left, 1st or 48kHz only */
1293 #define EMU_DST_MDOCK_SPDIF_LEFT1 0x0112
1294 /* Microdock S/PDIF OUT Left, 2nd or 96kHz */
1295 #define EMU_DST_MDOCK_SPDIF_LEFT2 0x0113
1296 /* Microdock S/PDIF OUT Right, 1st or 48kHz only */
1297 #define EMU_DST_MDOCK_SPDIF_RIGHT1 0x0116
1298 /* Microdock S/PDIF OUT Right, 2nd or 96kHz */
1299 #define EMU_DST_MDOCK_SPDIF_RIGHT2 0x0117
1300 /* Microdock S/PDIF ADAT 8 channel out +8 to +f */
1301 #define EMU_DST_MDOCK_ADAT 0x0118
1302
1303 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1304 #define EMU_DST_MANA_DAC_LEFT 0x0300
1305 /* Headphone jack on 1010 cardbus? 44.1/48kHz only? */
1306 #define EMU_DST_MANA_DAC_RIGHT 0x0301
1307
1308 /************************************************************************************************/
1309 /* EMU1010m HANA Sources */
1310 /************************************************************************************************/
1311 /* Hana, original 1010,1212,1820 using Alice2
1312 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1313 * 0x00,0x00-0x1f: Silence
1314 * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1315 * 0x01, 0x00: Dock Mic A
1316 * 0x01, 0x04: Dock Mic B
1317 * 0x01, 0x08: Dock ADC 1 Left
1318 * 0x01, 0x0c: Dock ADC 1 Right
1319 * 0x01, 0x10: Dock ADC 2 Left
1320 * 0x01, 0x14: Dock ADC 2 Right
1321 * 0x01, 0x18: Dock ADC 3 Left
1322 * 0x01, 0x1c: Dock ADC 3 Right
1323 * 0x02, 0x00: Hana ADC Left
1324 * 0x02, 0x01: Hana ADC Right
1325 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1326 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1327 * 0x04, 0x00-0x07: Hana ADAT
1328 * 0x05, 0x00: Hana S/PDIF Left
1329 * 0x05, 0x01: Hana S/PDIF Right
1330 * 0x06-0x07: Not used
1331 *
1332 * Hana2 never released, but used Tina
1333 * Not needed.
1334 *
1335 * Hana3, rev2 1010,1212,1616 using Tina
1336 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1337 * 0x00,0x00-0x1f: Silence
1338 * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1339 * 0x01, 0x00: Dock Mic A
1340 * 0x01, 0x04: Dock Mic B
1341 * 0x01, 0x08: Dock ADC 1 Left
1342 * 0x01, 0x0c: Dock ADC 1 Right
1343 * 0x01, 0x10: Dock ADC 2 Left
1344 * 0x01, 0x12: Dock S/PDIF Left
1345 * 0x01, 0x14: Dock ADC 2 Right
1346 * 0x01, 0x16: Dock S/PDIF Right
1347 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1348 * 0x01, 0x18: Dock ADC 3 Left
1349 * 0x01, 0x1c: Dock ADC 3 Right
1350 * 0x02, 0x00: Hanoa ADC Left
1351 * 0x02, 0x01: Hanoa ADC Right
1352 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
1353 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
1354 * 0x04, 0x00-0x07: Hana3 ADAT
1355 * 0x05, 0x00: Hana3 S/PDIF Left
1356 * 0x05, 0x01: Hana3 S/PDIF Right
1357 * 0x06-0x07: Not used
1358 *
1359 * HanaLite, rev1 0404 using Alice2
1360 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1361 * 0x00,0x00-0x1f: Silence
1362 * 0x01: Not used
1363 * 0x02, 0x00: ADC Left
1364 * 0x02, 0x01: ADC Right
1365 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1366 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1367 * 0x04: Not used
1368 * 0x05, 0x00: S/PDIF Left
1369 * 0x05, 0x01: S/PDIF Right
1370 * 0x06-0x07: Not used
1371 *
1372 * HanaLiteLite, rev2 0404 using Alice2
1373 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1374 * 0x00,0x00-0x1f: Silence
1375 * 0x01: Not used
1376 * 0x02, 0x00: ADC Left
1377 * 0x02, 0x01: ADC Right
1378 * 0x03, 0x00-0x0f: 16 inputs from Alice2 Emu32A output
1379 * 0x03, 0x10-0x1f: 16 inputs from Alice2 Emu32B output
1380 * 0x04: Not used
1381 * 0x05, 0x00: S/PDIF Left
1382 * 0x05, 0x01: S/PDIF Right
1383 * 0x06-0x07: Not used
1384 *
1385 * Mana, Cardbus 1616 using Tina2
1386 * Sources SRATEX = 1X rates: 44.1 kHz or 48 kHz
1387 * 0x00,0x00-0x1f: Silence
1388 * 0x01, 0x10-0x1f: 32 Elink channels from Audio Dock
1389 * 0x01, 0x00: Dock Mic A
1390 * 0x01, 0x04: Dock Mic B
1391 * 0x01, 0x08: Dock ADC 1 Left
1392 * 0x01, 0x0c: Dock ADC 1 Right
1393 * 0x01, 0x10: Dock ADC 2 Left
1394 * 0x01, 0x12: Dock S/PDIF Left
1395 * 0x01, 0x14: Dock ADC 2 Right
1396 * 0x01, 0x16: Dock S/PDIF Right
1397 * 0x01, 0x18-0x1f: Dock ADAT 0-7
1398 * 0x01, 0x18: Dock ADC 3 Left
1399 * 0x01, 0x1c: Dock ADC 3 Right
1400 * 0x02: Not used
1401 * 0x03, 0x00-0x0f: 16 inputs from Tina Emu32A output
1402 * 0x03, 0x10-0x1f: 16 inputs from Tina Emu32B output
1403 * 0x04-0x07: Not used
1404 *
1405 */
1406
1407 /* 32-bit sources of signal in the Hana FPGA. The sources are routed to
1408 * destinations using mixer control for each destination - see emumixer.c
1409 * Sources are either physical inputs of FPGA,
1410 * or outputs from Alice (audigy) - 16 x EMU_SRC_ALICE_EMU32A +
1411 * 16 x EMU_SRC_ALICE_EMU32B
1412 */
1413 #define EMU_SRC_SILENCE 0x0000 /* Silence */
1414 #define EMU_SRC_DOCK_MIC_A1 0x0100 /* Audio Dock Mic A, 1st or 48kHz only */
1415 #define EMU_SRC_DOCK_MIC_A2 0x0101 /* Audio Dock Mic A, 2nd or 96kHz */
1416 #define EMU_SRC_DOCK_MIC_A3 0x0102 /* Audio Dock Mic A, 3rd or 192kHz */
1417 #define EMU_SRC_DOCK_MIC_A4 0x0103 /* Audio Dock Mic A, 4th or 192kHz */
1418 #define EMU_SRC_DOCK_MIC_B1 0x0104 /* Audio Dock Mic B, 1st or 48kHz only */
1419 #define EMU_SRC_DOCK_MIC_B2 0x0105 /* Audio Dock Mic B, 2nd or 96kHz */
1420 #define EMU_SRC_DOCK_MIC_B3 0x0106 /* Audio Dock Mic B, 3rd or 192kHz */
1421 #define EMU_SRC_DOCK_MIC_B4 0x0107 /* Audio Dock Mic B, 4th or 192kHz */
1422 #define EMU_SRC_DOCK_ADC1_LEFT1 0x0108 /* Audio Dock ADC1 Left, 1st or 48kHz only */
1423 #define EMU_SRC_DOCK_ADC1_LEFT2 0x0109 /* Audio Dock ADC1 Left, 2nd or 96kHz */
1424 #define EMU_SRC_DOCK_ADC1_LEFT3 0x010a /* Audio Dock ADC1 Left, 3rd or 192kHz */
1425 #define EMU_SRC_DOCK_ADC1_LEFT4 0x010b /* Audio Dock ADC1 Left, 4th or 192kHz */
1426 #define EMU_SRC_DOCK_ADC1_RIGHT1 0x010c /* Audio Dock ADC1 Right, 1st or 48kHz only */
1427 #define EMU_SRC_DOCK_ADC1_RIGHT2 0x010d /* Audio Dock ADC1 Right, 2nd or 96kHz */
1428 #define EMU_SRC_DOCK_ADC1_RIGHT3 0x010e /* Audio Dock ADC1 Right, 3rd or 192kHz */
1429 #define EMU_SRC_DOCK_ADC1_RIGHT4 0x010f /* Audio Dock ADC1 Right, 4th or 192kHz */
1430 #define EMU_SRC_DOCK_ADC2_LEFT1 0x0110 /* Audio Dock ADC2 Left, 1st or 48kHz only */
1431 #define EMU_SRC_DOCK_ADC2_LEFT2 0x0111 /* Audio Dock ADC2 Left, 2nd or 96kHz */
1432 #define EMU_SRC_DOCK_ADC2_LEFT3 0x0112 /* Audio Dock ADC2 Left, 3rd or 192kHz */
1433 #define EMU_SRC_DOCK_ADC2_LEFT4 0x0113 /* Audio Dock ADC2 Left, 4th or 192kHz */
1434 #define EMU_SRC_DOCK_ADC2_RIGHT1 0x0114 /* Audio Dock ADC2 Right, 1st or 48kHz only */
1435 #define EMU_SRC_DOCK_ADC2_RIGHT2 0x0115 /* Audio Dock ADC2 Right, 2nd or 96kHz */
1436 #define EMU_SRC_DOCK_ADC2_RIGHT3 0x0116 /* Audio Dock ADC2 Right, 3rd or 192kHz */
1437 #define EMU_SRC_DOCK_ADC2_RIGHT4 0x0117 /* Audio Dock ADC2 Right, 4th or 192kHz */
1438 #define EMU_SRC_DOCK_ADC3_LEFT1 0x0118 /* Audio Dock ADC3 Left, 1st or 48kHz only */
1439 #define EMU_SRC_DOCK_ADC3_LEFT2 0x0119 /* Audio Dock ADC3 Left, 2nd or 96kHz */
1440 #define EMU_SRC_DOCK_ADC3_LEFT3 0x011a /* Audio Dock ADC3 Left, 3rd or 192kHz */
1441 #define EMU_SRC_DOCK_ADC3_LEFT4 0x011b /* Audio Dock ADC3 Left, 4th or 192kHz */
1442 #define EMU_SRC_DOCK_ADC3_RIGHT1 0x011c /* Audio Dock ADC3 Right, 1st or 48kHz only */
1443 #define EMU_SRC_DOCK_ADC3_RIGHT2 0x011d /* Audio Dock ADC3 Right, 2nd or 96kHz */
1444 #define EMU_SRC_DOCK_ADC3_RIGHT3 0x011e /* Audio Dock ADC3 Right, 3rd or 192kHz */
1445 #define EMU_SRC_DOCK_ADC3_RIGHT4 0x011f /* Audio Dock ADC3 Right, 4th or 192kHz */
1446 #define EMU_SRC_HAMOA_ADC_LEFT1 0x0200 /* Hamoa ADC Left, 1st or 48kHz only */
1447 #define EMU_SRC_HAMOA_ADC_LEFT2 0x0202 /* Hamoa ADC Left, 2nd or 96kHz */
1448 #define EMU_SRC_HAMOA_ADC_LEFT3 0x0204 /* Hamoa ADC Left, 3rd or 192kHz */
1449 #define EMU_SRC_HAMOA_ADC_LEFT4 0x0206 /* Hamoa ADC Left, 4th or 192kHz */
1450 #define EMU_SRC_HAMOA_ADC_RIGHT1 0x0201 /* Hamoa ADC Right, 1st or 48kHz only */
1451 #define EMU_SRC_HAMOA_ADC_RIGHT2 0x0203 /* Hamoa ADC Right, 2nd or 96kHz */
1452 #define EMU_SRC_HAMOA_ADC_RIGHT3 0x0205 /* Hamoa ADC Right, 3rd or 192kHz */
1453 #define EMU_SRC_HAMOA_ADC_RIGHT4 0x0207 /* Hamoa ADC Right, 4th or 192kHz */
1454 #define EMU_SRC_ALICE_EMU32A 0x0300 /* Alice2 EMU32a 16 outputs. +0 to +0xf */
1455 #define EMU_SRC_ALICE_EMU32B 0x0310 /* Alice2 EMU32b 16 outputs. +0 to +0xf */
1456 #define EMU_SRC_HANA_ADAT 0x0400 /* Hana ADAT 8 channel in +0 to +7 */
1457 #define EMU_SRC_HANA_SPDIF_LEFT1 0x0500 /* Hana SPDIF Left, 1st or 48kHz only */
1458 #define EMU_SRC_HANA_SPDIF_LEFT2 0x0502 /* Hana SPDIF Left, 2nd or 96kHz */
1459 #define EMU_SRC_HANA_SPDIF_RIGHT1 0x0501 /* Hana SPDIF Right, 1st or 48kHz only */
1460 #define EMU_SRC_HANA_SPDIF_RIGHT2 0x0503 /* Hana SPDIF Right, 2nd or 96kHz */
1461
1462 /* Additional inputs for 1616(M)/Microdock */
1463 /* Microdock S/PDIF Left, 1st or 48kHz only */
1464 #define EMU_SRC_MDOCK_SPDIF_LEFT1 0x0112
1465 /* Microdock S/PDIF Left, 2nd or 96kHz */
1466 #define EMU_SRC_MDOCK_SPDIF_LEFT2 0x0113
1467 /* Microdock S/PDIF Right, 1st or 48kHz only */
1468 #define EMU_SRC_MDOCK_SPDIF_RIGHT1 0x0116
1469 /* Microdock S/PDIF Right, 2nd or 96kHz */
1470 #define EMU_SRC_MDOCK_SPDIF_RIGHT2 0x0117
1471 /* Microdock ADAT 8 channel in +8 to +f */
1472 #define EMU_SRC_MDOCK_ADAT 0x0118
1473
1474 /* 0x600 and 0x700 no used */
1475
1476 /* ------------------- STRUCTURES -------------------- */
1477
1478 enum {
1479 EMU10K1_EFX,
1480 EMU10K1_PCM,
1481 EMU10K1_SYNTH,
1482 EMU10K1_MIDI
1483 };
1484
1485 struct snd_emu10k1;
1486
1487 struct snd_emu10k1_voice {
1488 struct snd_emu10k1 *emu;
1489 int number;
1490 unsigned int use: 1,
1491 pcm: 1,
1492 efx: 1,
1493 synth: 1,
1494 midi: 1;
1495 void (*interrupt)(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1496
1497 struct snd_emu10k1_pcm *epcm;
1498 };
1499
1500 enum {
1501 PLAYBACK_EMUVOICE,
1502 PLAYBACK_EFX,
1503 CAPTURE_AC97ADC,
1504 CAPTURE_AC97MIC,
1505 CAPTURE_EFX
1506 };
1507
1508 struct snd_emu10k1_pcm {
1509 struct snd_emu10k1 *emu;
1510 int type;
1511 struct snd_pcm_substream *substream;
1512 struct snd_emu10k1_voice *voices[NUM_EFX_PLAYBACK];
1513 struct snd_emu10k1_voice *extra;
1514 unsigned short running;
1515 unsigned short first_ptr;
1516 struct snd_util_memblk *memblk;
1517 unsigned int start_addr;
1518 unsigned int ccca_start_addr;
1519 unsigned int capture_ipr; /* interrupt acknowledge mask */
1520 unsigned int capture_inte; /* interrupt enable mask */
1521 unsigned int capture_ba_reg; /* buffer address register */
1522 unsigned int capture_bs_reg; /* buffer size register */
1523 unsigned int capture_idx_reg; /* buffer index register */
1524 unsigned int capture_cr_val; /* control value */
1525 unsigned int capture_cr_val2; /* control value2 (for audigy) */
1526 unsigned int capture_bs_val; /* buffer size value */
1527 unsigned int capture_bufsize; /* buffer size in bytes */
1528 };
1529
1530 struct snd_emu10k1_pcm_mixer {
1531 /* mono, left, right x 8 sends (4 on emu10k1) */
1532 unsigned char send_routing[3][8];
1533 unsigned char send_volume[3][8];
1534 unsigned short attn[3];
1535 struct snd_emu10k1_pcm *epcm;
1536 };
1537
1538 #define snd_emu10k1_compose_send_routing(route) \
1539 ((route[0] | (route[1] << 4) | (route[2] << 8) | (route[3] << 12)) << 16)
1540
1541 #define snd_emu10k1_compose_audigy_fxrt1(route) \
1542 ((unsigned int)route[0] | ((unsigned int)route[1] << 8) | ((unsigned int)route[2] << 16) | ((unsigned int)route[3] << 24))
1543
1544 #define snd_emu10k1_compose_audigy_fxrt2(route) \
1545 ((unsigned int)route[4] | ((unsigned int)route[5] << 8) | ((unsigned int)route[6] << 16) | ((unsigned int)route[7] << 24))
1546
1547 struct snd_emu10k1_memblk {
1548 struct snd_util_memblk mem;
1549 /* private part */
1550 int first_page, last_page, pages, mapped_page;
1551 unsigned int map_locked;
1552 struct list_head mapped_link;
1553 struct list_head mapped_order_link;
1554 };
1555
1556 #define snd_emu10k1_memblk_offset(blk) (((blk)->mapped_page << PAGE_SHIFT) | ((blk)->mem.offset & (PAGE_SIZE - 1)))
1557
1558 #define EMU10K1_MAX_TRAM_BLOCKS_PER_CODE 16
1559
1560 struct snd_emu10k1_fx8010_ctl {
1561 struct list_head list; /* list link container */
1562 unsigned int vcount;
1563 unsigned int count; /* count of GPR (1..16) */
1564 unsigned short gpr[32]; /* GPR number(s) */
1565 unsigned int value[32];
1566 unsigned int min; /* minimum range */
1567 unsigned int max; /* maximum range */
1568 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */
1569 struct snd_kcontrol *kcontrol;
1570 };
1571
1572 typedef void (snd_fx8010_irq_handler_t)(struct snd_emu10k1 *emu, void *private_data);
1573
1574 struct snd_emu10k1_fx8010_irq {
1575 struct snd_emu10k1_fx8010_irq *next;
1576 snd_fx8010_irq_handler_t *handler;
1577 unsigned short gpr_running;
1578 void *private_data;
1579 };
1580
1581 struct snd_emu10k1_fx8010_pcm {
1582 unsigned int valid: 1,
1583 opened: 1,
1584 active: 1;
1585 unsigned int channels; /* 16-bit channels count */
1586 unsigned int tram_start; /* initial ring buffer position in TRAM (in samples) */
1587 unsigned int buffer_size; /* count of buffered samples */
1588 unsigned short gpr_size; /* GPR containing size of ring buffer in samples (host) */
1589 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */
1590 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */
1591 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */
1592 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */
1593 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */
1594 unsigned char etram[32]; /* external TRAM address & data */
1595 struct snd_pcm_indirect pcm_rec;
1596 unsigned int tram_pos;
1597 unsigned int tram_shift;
1598 struct snd_emu10k1_fx8010_irq irq;
1599 };
1600
1601 struct snd_emu10k1_fx8010 {
1602 unsigned short fxbus_mask; /* used FX buses (bitmask) */
1603 unsigned short extin_mask; /* used external inputs (bitmask) */
1604 unsigned short extout_mask; /* used external outputs (bitmask) */
1605 unsigned short pad1;
1606 unsigned int itram_size; /* internal TRAM size in samples */
1607 struct snd_dma_buffer etram_pages; /* external TRAM pages and size */
1608 unsigned int dbg; /* FX debugger register */
1609 unsigned char name[128];
1610 int gpr_size; /* size of allocated GPR controls */
1611 int gpr_count; /* count of used kcontrols */
1612 struct list_head gpr_ctl; /* GPR controls */
1613 struct mutex lock;
1614 struct snd_emu10k1_fx8010_pcm pcm[8];
1615 spinlock_t irq_lock;
1616 struct snd_emu10k1_fx8010_irq *irq_handlers;
1617 };
1618
1619 struct snd_emu10k1_midi {
1620 struct snd_emu10k1 *emu;
1621 struct snd_rawmidi *rmidi;
1622 struct snd_rawmidi_substream *substream_input;
1623 struct snd_rawmidi_substream *substream_output;
1624 unsigned int midi_mode;
1625 spinlock_t input_lock;
1626 spinlock_t output_lock;
1627 spinlock_t open_lock;
1628 int tx_enable, rx_enable;
1629 int port;
1630 int ipr_tx, ipr_rx;
1631 void (*interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1632 };
1633
1634 enum {
1635 EMU_MODEL_SB,
1636 EMU_MODEL_EMU1010,
1637 EMU_MODEL_EMU1010B,
1638 EMU_MODEL_EMU1616,
1639 EMU_MODEL_EMU0404,
1640 };
1641
1642 struct snd_emu_chip_details {
1643 u32 vendor;
1644 u32 device;
1645 u32 subsystem;
1646 unsigned char revision;
1647 unsigned char emu10k1_chip; /* Original SB Live. Not SB Live 24bit. */
1648 unsigned char emu10k2_chip; /* Audigy 1 or Audigy 2. */
1649 unsigned char ca0102_chip; /* Audigy 1 or Audigy 2. Not SB Audigy 2 Value. */
1650 unsigned char ca0108_chip; /* Audigy 2 Value */
1651 unsigned char ca_cardbus_chip; /* Audigy 2 ZS Notebook */
1652 unsigned char ca0151_chip; /* P16V */
1653 unsigned char spk71; /* Has 7.1 speakers */
1654 unsigned char sblive51; /* SBLive! 5.1 - extout 0x11 -> center, 0x12 -> lfe */
1655 unsigned char spdif_bug; /* Has Spdif phasing bug */
1656 unsigned char ac97_chip; /* Has an AC97 chip: 1 = mandatory, 2 = optional */
1657 unsigned char ecard; /* APS EEPROM */
1658 unsigned char emu_model; /* EMU model type */
1659 unsigned char spi_dac; /* SPI interface for DAC */
1660 unsigned char i2c_adc; /* I2C interface for ADC */
1661 unsigned char adc_1361t; /* Use Philips 1361T ADC */
1662 unsigned char invert_shared_spdif; /* analog/digital switch inverted */
1663 const char *driver;
1664 const char *name;
1665 const char *id; /* for backward compatibility - can be NULL if not needed */
1666 };
1667
1668 struct snd_emu1010 {
1669 unsigned int output_source[64];
1670 unsigned int input_source[64];
1671 unsigned int adc_pads; /* bit mask */
1672 unsigned int dac_pads; /* bit mask */
1673 unsigned int internal_clock; /* 44100 or 48000 */
1674 unsigned int optical_in; /* 0:SPDIF, 1:ADAT */
1675 unsigned int optical_out; /* 0:SPDIF, 1:ADAT */
1676 struct delayed_work firmware_work;
1677 u32 last_reg;
1678 };
1679
1680 struct snd_emu10k1 {
1681 int irq;
1682
1683 unsigned long port; /* I/O port number */
1684 unsigned int tos_link: 1, /* tos link detected */
1685 rear_ac97: 1, /* rear channels are on AC'97 */
1686 enable_ir: 1;
1687 unsigned int support_tlv :1;
1688 /* Contains profile of card capabilities */
1689 const struct snd_emu_chip_details *card_capabilities;
1690 unsigned int audigy; /* is Audigy? */
1691 unsigned int revision; /* chip revision */
1692 unsigned int serial; /* serial number */
1693 unsigned short model; /* subsystem id */
1694 unsigned int card_type; /* EMU10K1_CARD_* */
1695 unsigned int ecard_ctrl; /* ecard control bits */
1696 unsigned int address_mode; /* address mode */
1697 unsigned long dma_mask; /* PCI DMA mask */
1698 bool iommu_workaround; /* IOMMU workaround needed */
1699 unsigned int delay_pcm_irq; /* in samples */
1700 int max_cache_pages; /* max memory size / PAGE_SIZE */
1701 struct snd_dma_buffer silent_page; /* silent page */
1702 struct snd_dma_buffer ptb_pages; /* page table pages */
1703 struct snd_dma_device p16v_dma_dev;
1704 struct snd_dma_buffer p16v_buffer;
1705
1706 struct snd_util_memhdr *memhdr; /* page allocation list */
1707
1708 struct list_head mapped_link_head;
1709 struct list_head mapped_order_link_head;
1710 void **page_ptr_table;
1711 unsigned long *page_addr_table;
1712 spinlock_t memblk_lock;
1713
1714 unsigned int spdif_bits[3]; /* s/pdif out setup */
1715 unsigned int i2c_capture_source;
1716 u8 i2c_capture_volume[4][2];
1717
1718 struct snd_emu10k1_fx8010 fx8010; /* FX8010 info */
1719 int gpr_base;
1720
1721 struct snd_ac97 *ac97;
1722
1723 struct pci_dev *pci;
1724 struct snd_card *card;
1725 struct snd_pcm *pcm;
1726 struct snd_pcm *pcm_mic;
1727 struct snd_pcm *pcm_efx;
1728 struct snd_pcm *pcm_multi;
1729 struct snd_pcm *pcm_p16v;
1730
1731 spinlock_t synth_lock;
1732 void *synth;
1733 int (*get_synth_voice)(struct snd_emu10k1 *emu);
1734
1735 spinlock_t reg_lock;
1736 spinlock_t emu_lock;
1737 spinlock_t voice_lock;
1738 spinlock_t spi_lock; /* serialises access to spi port */
1739 spinlock_t i2c_lock; /* serialises access to i2c port */
1740
1741 struct snd_emu10k1_voice voices[NUM_G];
1742 struct snd_emu10k1_voice p16v_voices[4];
1743 struct snd_emu10k1_voice p16v_capture_voice;
1744 int p16v_device_offset;
1745 u32 p16v_capture_source;
1746 u32 p16v_capture_channel;
1747 struct snd_emu1010 emu1010;
1748 struct snd_emu10k1_pcm_mixer pcm_mixer[32];
1749 struct snd_emu10k1_pcm_mixer efx_pcm_mixer[NUM_EFX_PLAYBACK];
1750 struct snd_kcontrol *ctl_send_routing;
1751 struct snd_kcontrol *ctl_send_volume;
1752 struct snd_kcontrol *ctl_attn;
1753 struct snd_kcontrol *ctl_efx_send_routing;
1754 struct snd_kcontrol *ctl_efx_send_volume;
1755 struct snd_kcontrol *ctl_efx_attn;
1756
1757 void (*hwvol_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1758 void (*capture_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1759 void (*capture_mic_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1760 void (*capture_efx_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1761 void (*spdif_interrupt)(struct snd_emu10k1 *emu, unsigned int status);
1762 void (*dsp_interrupt)(struct snd_emu10k1 *emu);
1763
1764 struct snd_pcm_substream *pcm_capture_substream;
1765 struct snd_pcm_substream *pcm_capture_mic_substream;
1766 struct snd_pcm_substream *pcm_capture_efx_substream;
1767 struct snd_pcm_substream *pcm_playback_efx_substream;
1768
1769 struct snd_timer *timer;
1770
1771 struct snd_emu10k1_midi midi;
1772 struct snd_emu10k1_midi midi2; /* for audigy */
1773
1774 unsigned int efx_voices_mask[2];
1775 unsigned int next_free_voice;
1776
1777 const struct firmware *firmware;
1778 const struct firmware *dock_fw;
1779
1780 #ifdef CONFIG_PM_SLEEP
1781 unsigned int *saved_ptr;
1782 unsigned int *saved_gpr;
1783 unsigned int *tram_val_saved;
1784 unsigned int *tram_addr_saved;
1785 unsigned int *saved_icode;
1786 unsigned int *p16v_saved;
1787 unsigned int saved_a_iocfg, saved_hcfg;
1788 bool suspend;
1789 #endif
1790
1791 };
1792
1793 int snd_emu10k1_create(struct snd_card *card,
1794 struct pci_dev *pci,
1795 unsigned short extin_mask,
1796 unsigned short extout_mask,
1797 long max_cache_bytes,
1798 int enable_ir,
1799 uint subsystem,
1800 struct snd_emu10k1 ** remu);
1801
1802 int snd_emu10k1_pcm(struct snd_emu10k1 *emu, int device);
1803 int snd_emu10k1_pcm_mic(struct snd_emu10k1 *emu, int device);
1804 int snd_emu10k1_pcm_efx(struct snd_emu10k1 *emu, int device);
1805 int snd_p16v_pcm(struct snd_emu10k1 *emu, int device);
1806 int snd_p16v_free(struct snd_emu10k1 * emu);
1807 int snd_p16v_mixer(struct snd_emu10k1 * emu);
1808 int snd_emu10k1_pcm_multi(struct snd_emu10k1 *emu, int device);
1809 int snd_emu10k1_fx8010_pcm(struct snd_emu10k1 *emu, int device);
1810 int snd_emu10k1_mixer(struct snd_emu10k1 * emu, int pcm_device, int multi_device);
1811 int snd_emu10k1_timer(struct snd_emu10k1 * emu, int device);
1812 int snd_emu10k1_fx8010_new(struct snd_emu10k1 *emu, int device);
1813
1814 irqreturn_t snd_emu10k1_interrupt(int irq, void *dev_id);
1815
1816 void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int voice);
1817 int snd_emu10k1_init_efx(struct snd_emu10k1 *emu);
1818 void snd_emu10k1_free_efx(struct snd_emu10k1 *emu);
1819 int snd_emu10k1_fx8010_tram_setup(struct snd_emu10k1 *emu, u32 size);
1820 int snd_emu10k1_done(struct snd_emu10k1 * emu);
1821
1822 /* I/O functions */
1823 unsigned int snd_emu10k1_ptr_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
1824 void snd_emu10k1_ptr_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
1825 unsigned int snd_emu10k1_ptr20_read(struct snd_emu10k1 * emu, unsigned int reg, unsigned int chn);
1826 void snd_emu10k1_ptr20_write(struct snd_emu10k1 *emu, unsigned int reg, unsigned int chn, unsigned int data);
1827 int snd_emu10k1_spi_write(struct snd_emu10k1 * emu, unsigned int data);
1828 int snd_emu10k1_i2c_write(struct snd_emu10k1 *emu, u32 reg, u32 value);
1829 int snd_emu1010_fpga_write(struct snd_emu10k1 * emu, u32 reg, u32 value);
1830 int snd_emu1010_fpga_read(struct snd_emu10k1 * emu, u32 reg, u32 *value);
1831 int snd_emu1010_fpga_link_dst_src_write(struct snd_emu10k1 * emu, u32 dst, u32 src);
1832 unsigned int snd_emu10k1_efx_read(struct snd_emu10k1 *emu, unsigned int pc);
1833 void snd_emu10k1_intr_enable(struct snd_emu10k1 *emu, unsigned int intrenb);
1834 void snd_emu10k1_intr_disable(struct snd_emu10k1 *emu, unsigned int intrenb);
1835 void snd_emu10k1_voice_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
1836 void snd_emu10k1_voice_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
1837 void snd_emu10k1_voice_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
1838 void snd_emu10k1_voice_half_loop_intr_enable(struct snd_emu10k1 *emu, unsigned int voicenum);
1839 void snd_emu10k1_voice_half_loop_intr_disable(struct snd_emu10k1 *emu, unsigned int voicenum);
1840 void snd_emu10k1_voice_half_loop_intr_ack(struct snd_emu10k1 *emu, unsigned int voicenum);
1841 void snd_emu10k1_voice_set_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
1842 void snd_emu10k1_voice_clear_loop_stop(struct snd_emu10k1 *emu, unsigned int voicenum);
1843 void snd_emu10k1_wait(struct snd_emu10k1 *emu, unsigned int wait);
snd_emu10k1_wc(struct snd_emu10k1 * emu)1844 static inline unsigned int snd_emu10k1_wc(struct snd_emu10k1 *emu) { return (inl(emu->port + WC) >> 6) & 0xfffff; }
1845 unsigned short snd_emu10k1_ac97_read(struct snd_ac97 *ac97, unsigned short reg);
1846 void snd_emu10k1_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short data);
1847 unsigned int snd_emu10k1_rate_to_pitch(unsigned int rate);
1848
1849 #ifdef CONFIG_PM_SLEEP
1850 void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu);
1851 void snd_emu10k1_resume_init(struct snd_emu10k1 *emu);
1852 void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu);
1853 int snd_emu10k1_efx_alloc_pm_buffer(struct snd_emu10k1 *emu);
1854 void snd_emu10k1_efx_free_pm_buffer(struct snd_emu10k1 *emu);
1855 void snd_emu10k1_efx_suspend(struct snd_emu10k1 *emu);
1856 void snd_emu10k1_efx_resume(struct snd_emu10k1 *emu);
1857 int snd_p16v_alloc_pm_buffer(struct snd_emu10k1 *emu);
1858 void snd_p16v_free_pm_buffer(struct snd_emu10k1 *emu);
1859 void snd_p16v_suspend(struct snd_emu10k1 *emu);
1860 void snd_p16v_resume(struct snd_emu10k1 *emu);
1861 #endif
1862
1863 /* memory allocation */
1864 struct snd_util_memblk *snd_emu10k1_alloc_pages(struct snd_emu10k1 *emu, struct snd_pcm_substream *substream);
1865 int snd_emu10k1_free_pages(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
1866 int snd_emu10k1_alloc_pages_maybe_wider(struct snd_emu10k1 *emu, size_t size,
1867 struct snd_dma_buffer *dmab);
1868 struct snd_util_memblk *snd_emu10k1_synth_alloc(struct snd_emu10k1 *emu, unsigned int size);
1869 int snd_emu10k1_synth_free(struct snd_emu10k1 *emu, struct snd_util_memblk *blk);
1870 int snd_emu10k1_synth_bzero(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, int size);
1871 int snd_emu10k1_synth_copy_from_user(struct snd_emu10k1 *emu, struct snd_util_memblk *blk, int offset, const char __user *data, int size);
1872 int snd_emu10k1_memblk_map(struct snd_emu10k1 *emu, struct snd_emu10k1_memblk *blk);
1873
1874 /* voice allocation */
1875 int snd_emu10k1_voice_alloc(struct snd_emu10k1 *emu, int type, int pair, struct snd_emu10k1_voice **rvoice);
1876 int snd_emu10k1_voice_free(struct snd_emu10k1 *emu, struct snd_emu10k1_voice *pvoice);
1877
1878 /* MIDI uart */
1879 int snd_emu10k1_midi(struct snd_emu10k1 * emu);
1880 int snd_emu10k1_audigy_midi(struct snd_emu10k1 * emu);
1881
1882 /* proc interface */
1883 int snd_emu10k1_proc_init(struct snd_emu10k1 * emu);
1884
1885 /* fx8010 irq handler */
1886 int snd_emu10k1_fx8010_register_irq_handler(struct snd_emu10k1 *emu,
1887 snd_fx8010_irq_handler_t *handler,
1888 unsigned char gpr_running,
1889 void *private_data,
1890 struct snd_emu10k1_fx8010_irq *irq);
1891 int snd_emu10k1_fx8010_unregister_irq_handler(struct snd_emu10k1 *emu,
1892 struct snd_emu10k1_fx8010_irq *irq);
1893
1894 #endif /* __SOUND_EMU10K1_H */
1895