Searched refs:GENMASK (Results 1 – 25 of 42) sorted by relevance
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90 #define HSIO_PLL5G_CFG0_SELBGV820(x) (((x) << 23) & GENMASK(26, 23))91 #define HSIO_PLL5G_CFG0_SELBGV820_M GENMASK(26, 23)92 #define HSIO_PLL5G_CFG0_SELBGV820_X(x) (((x) & GENMASK(26, 23)) >> 23)93 #define HSIO_PLL5G_CFG0_LOOP_BW_RES(x) (((x) << 18) & GENMASK(22, 18))94 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_M GENMASK(22, 18)95 #define HSIO_PLL5G_CFG0_LOOP_BW_RES_X(x) (((x) & GENMASK(22, 18)) >> 18)96 #define HSIO_PLL5G_CFG0_SELCPI(x) (((x) << 16) & GENMASK(17, 16))97 #define HSIO_PLL5G_CFG0_SELCPI_M GENMASK(17, 16)98 #define HSIO_PLL5G_CFG0_SELCPI_X(x) (((x) & GENMASK(17, 16)) >> 16)103 #define HSIO_PLL5G_CFG0_CPU_CLK_DIV(x) (((x) << 6) & GENMASK(11, 6))[all …]
57 #define TPS68470_REG_RESET_MASK GENMASK(7, 0)58 #define TPS68470_VAVAL_AVOLT_MASK GENMASK(6, 0)60 #define TPS68470_VDVAL_DVOLT_MASK GENMASK(5, 0)61 #define TPS68470_VCMVAL_VCVOLT_MASK GENMASK(6, 0)62 #define TPS68470_VIOVAL_IOVOLT_MASK GENMASK(6, 0)63 #define TPS68470_VSIOVAL_IOVOLT_MASK GENMASK(6, 0)64 #define TPS68470_VAUX1VAL_AUX1VOLT_MASK GENMASK(6, 0)65 #define TPS68470_VAUX2VAL_AUX2VOLT_MASK GENMASK(6, 0)67 #define TPS68470_VACTL_EN_MASK GENMASK(0, 0)68 #define TPS68470_VDCTL_EN_MASK GENMASK(0, 0)[all …]
12 #define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY(x) ((GENMASK(7, 0) & (x)) << 24)15 #define SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(x) ((GENMASK(1, 0) & (x)) << 20)16 #define SUN4I_GPADC_CTRL0_FS_DIV(x) ((GENMASK(3, 0) & (x)) << 16)17 #define SUN4I_GPADC_CTRL0_T_ACQ(x) (GENMASK(15, 0) & (x))21 #define SUN4I_GPADC_CTRL1_STYLUS_UP_DEBOUNCE(x) ((GENMASK(7, 0) & (x)) << 12)27 #define SUN4I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(2, 0) & (x))28 #define SUN4I_GPADC_CTRL1_ADC_CHAN_MASK GENMASK(2, 0)35 #define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(3, 0) & BIT(x))36 #define SUN6I_GPADC_CTRL1_ADC_CHAN_MASK GENMASK(3, 0)44 #define SUN4I_GPADC_CTRL2_TP_SENSITIVE_ADJUST(x) ((GENMASK(3, 0) & (x)) << 28)[all …]
101 #define LDO_VOLTAGE_MASK GENMASK(6, 2)102 #define BUCK_VOLTAGE_MASK GENMASK(7, 2)113 #define BUCKS_PD_CR_REG_MASK GENMASK(7, 0)114 #define BUCK_MASK_RANK_REGISTER_MASK GENMASK(3, 0)115 #define BUCK_MASK_RESET_REGISTER_MASK GENMASK(3, 0)116 #define LDO1234_PULL_DOWN_REGISTER_MASK GENMASK(7, 0)117 #define LDO56_VREF_PD_CR_REG_MASK GENMASK(5, 0)118 #define LDO_MASK_RANK_REGISTER_MASK GENMASK(5, 0)119 #define LDO_MASK_RESET_REGISTER_MASK GENMASK(5, 0)145 #define BUCKS_ICCTO_CR_REG_MASK GENMASK(6, 0)[all …]
87 #define TPS65086_DEVICEID_PART_MASK GENMASK(3, 0)88 #define TPS65086_DEVICEID_OTP_MASK GENMASK(5, 4)89 #define TPS65086_DEVICEID_REV_MASK GENMASK(7, 6)92 #define BUCK_VID_MASK GENMASK(7, 1)93 #define VDOA1_VID_MASK GENMASK(4, 1)94 #define VDOA23_VID_MASK GENMASK(3, 0)
25 #define STM32_LPTIM_CMPOK_ARROK GENMASK(4, 3)30 #define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3)40 #define STM32_LPTIM_PRESC GENMASK(11, 9)41 #define STM32_LPTIM_CKPOL GENMASK(2, 1)
31 #define MX25_TGCR_PDBTIME_MASK GENMASK(31, 25)37 #define MX25_TGCR_POWERMODE_MASK GENMASK(9, 8)65 #define MX25_ADCQ_CR_RWAIT_MASK GENMASK(15, 12)67 #define MX25_ADCQ_CR_WMRK_MASK GENMASK(11, 8)73 #define MX25_ADCQ_CR_QSM_MASK GENMASK(1, 0)106 #define MX25_ADCQ_CFG_NOS_MASK GENMASK(19, 16)123 #define MX25_ADCQ_CFG_REFP_MASK GENMASK(8, 7)138 #define MX25_ADCQ_CFG_REFN_MASK GENMASK(3, 2)
24 #define ATMEL_HLCDC_MODE_MASK GENMASK(9, 8)28 #define ATMEL_HLCDC_GUARDTIME_MASK GENMASK(20, 16)43 #define ATMEL_HLCDC_CLKDIV_MASK GENMASK(23, 16)
15 #define BCOVE_ID_MINREV0 GENMASK(2, 0)16 #define BCOVE_ID_MAJREV0 GENMASK(5, 3)17 #define BCOVE_ID_VENDID0 GENMASK(7, 6)
39 #define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */55 #define TIM_CCMR_IC1PSC GENMASK(3, 2) /* Input capture 1 prescaler */57 #define TIM_CCMR_IC2PSC GENMASK(11, 10) /* Input capture 2 prescaler */81 #define TIM_DCR_DBA GENMASK(4, 0) /* DMA base addr */82 #define TIM_DCR_DBL GENMASK(12, 8) /* DMA burst len */
21 #define AT91_MC_ABTSZ GENMASK(9, 8)25 #define AT91_MC_ABTTYP GENMASK(11, 10)35 #define AT91_MPR_MSTP(n) GENMASK(2 + ((x) * 4), ((x) * 4))47 #define AT91_MC_SMC_NWS GENMASK(6, 0)50 #define AT91_MC_SMC_TDF GENMASK(11, 8)54 #define AT91_MC_SMC_DBW GENMASK(14, 13)58 #define AT91_MC_SMC_ACSS GENMASK(17, 16)61 #define AT91_MC_SMC_RWSETUP GENMASK(26, 24)63 #define AT91_MC_SMC_RWHOLD GENMASK(30, 28)69 #define AT91_MC_SDRAMC_MODE GENMASK(3, 0)[all …]
64 #define AT91_MATRIX_ULBT GENMASK(2, 0)72 #define AT91_MATRIX_SLOT_CYCLE GENMASK(7, 0)73 #define AT91_MATRIX_DEFMSTR_TYPE GENMASK(17, 16)77 #define AT91_MATRIX_FIXED_DEFMSTR GENMASK(20, 18)78 #define AT91_MATRIX_ARBT GENMASK(25, 24)82 #define AT91_MATRIX_ITCM_SIZE GENMASK(3, 0)87 #define AT91_MATRIX_DTCM_SIZE GENMASK(7, 4)95 #define AT91_MATRIX_MPR(x) GENMASK(((x) * 0x4) + 1, ((x) * 0x4))
41 #define ATMEL_SMC_MODE_EXNWMODE_MASK GENMASK(5, 4)48 #define ATMEL_SMC_MODE_DBW_MASK GENMASK(13, 12)52 #define ATMEL_SMC_MODE_TDF_MASK GENMASK(19, 16)58 #define ATMEL_SMC_MODE_PS_MASK GENMASK(29, 28)
70 #define PL080_LLI_ADDR_MASK GENMASK(31, 2)75 #define PL080_CONTROL_PROT_MASK GENMASK(30, 28)84 #define PL080_CONTROL_DWIDTH_MASK GENMASK(23, 21)86 #define PL080_CONTROL_SWIDTH_MASK GENMASK(20, 18)88 #define PL080_CONTROL_DB_SIZE_MASK GENMASK(17, 15)90 #define PL080_CONTROL_SB_SIZE_MASK GENMASK(14, 12)92 #define PL080_CONTROL_TRANSFER_SIZE_MASK GENMASK(11, 0)93 #define PL080S_CONTROL_TRANSFER_SIZE_MASK GENMASK(24, 0)116 #define PL080_CONFIG_FLOW_CONTROL_MASK GENMASK(13, 11)118 #define PL080_CONFIG_DST_SEL_MASK GENMASK(9, 6)[all …]
42 #define TIM2_PCD_LO_MASK GENMASK(4, 0)45 #define TIM2_ACB_MASK GENMASK(10, 6)51 #define TIM2_PCD_HI_MASK GENMASK(31, 27)
100 #define CX25840_VCONFIG_FMT_MASK GENMASK(2, 0)103 #define CX25840_VCONFIG_FMT_VIP11 GENMASK(1, 0)107 #define CX25840_VCONFIG_RES_MASK GENMASK(4, 3)112 #define CX25840_VCONFIG_VBIRAW_MASK GENMASK(6, 5)117 #define CX25840_VCONFIG_ANCDATA_MASK GENMASK(8, 7)122 #define CX25840_VCONFIG_TASKBIT_MASK GENMASK(10, 9)127 #define CX25840_VCONFIG_ACTIVE_MASK GENMASK(12, 11)132 #define CX25840_VCONFIG_VALID_MASK GENMASK(14, 13)137 #define CX25840_VCONFIG_HRESETW_MASK GENMASK(16, 15)142 #define CX25840_VCONFIG_CLKGATE_MASK GENMASK(18, 17)[all …]
17 #define SDW_REGADDR GENMASK(14, 0)18 #define SDW_SCP_ADDRPAGE2_MASK GENMASK(22, 15)19 #define SDW_SCP_ADDRPAGE1_MASK GENMASK(30, 23)50 #define SDW_DP0_PORTCTRL_DATAMODE GENMASK(3, 2)52 #define SDW_DP0_PORTCTRL_BPT_PAYLD GENMASK(7, 6)70 #define SDW_SCP_INT1_PORT0_3 GENMASK(6, 3)74 #define SDW_SCP_INTSTAT2_PORT4_10 GENMASK(6, 0)77 #define SDW_SCP_INTSTAT3_PORT11_14 GENMASK(3, 0)137 #define SDW_DPN_PORTCTRL_FLOWMODE GENMASK(1, 0)138 #define SDW_DPN_PORTCTRL_DATAMODE GENMASK(3, 2)[all …]
90 #define CLK_DIV_MSK GENMASK(15, 4)94 #define FW_REV_PROTOCOL_MSK GENMASK(15, 8)98 #define CLK_SEL_MSK GENMASK(2, 0)104 #define M_OPCODE_MSK GENMASK(31, 27)106 #define M_PARAMS_MSK GENMASK(26, 0)114 #define S_OPCODE_MSK GENMASK(31, 27)116 #define S_PARAMS_MSK GENMASK(26, 0)149 #define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \175 #define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \179 #define WATERMARK_MSK GENMASK(5, 0)[all …]
281 #define CPER_ARM_ERR_TRANSACTION_MASK GENMASK(1,0)283 #define CPER_ARM_ERR_OPERATION_MASK GENMASK(3,0)285 #define CPER_ARM_ERR_LEVEL_MASK GENMASK(2,0)287 #define CPER_ARM_ERR_PC_CORRUPT_MASK GENMASK(0,0)289 #define CPER_ARM_ERR_CORRECTED_MASK GENMASK(0,0)291 #define CPER_ARM_ERR_PRECISE_PC_MASK GENMASK(0,0)293 #define CPER_ARM_ERR_RESTARTABLE_PC_MASK GENMASK(0,0)295 #define CPER_ARM_ERR_PARTICIPATION_TYPE_MASK GENMASK(1,0)297 #define CPER_ARM_ERR_TIME_OUT_MASK GENMASK(0,0)299 #define CPER_ARM_ERR_ADDRESS_SPACE_MASK GENMASK(1,0)[all …]
21 #define GENMASK(h, l) \ macro
74 #define DP_CAP_DFP_D_PIN_ASSIGN(_cap_) (((_cap_) & GENMASK(15, 8)) >> 8)75 #define DP_CAP_UFP_D_PIN_ASSIGN(_cap_) (((_cap_) & GENMASK(23, 16)) >> 16)98 #define DP_CONF_PIN_ASSIGNEMENT_MASK GENMASK(15, 8)102 #define DP_CONF_GET_PIN_ASSIGN(_conf_) (((_conf_) & GENMASK(15, 8)) >> 8)
37 #define AT91_OHCIICR_USB_SUSPEND GENMASK(10, 8)41 #define AT91_UTMICKTRIM_FREQ GENMASK(1, 0)49 #define AT91_SFR_WPMR_WPKEY_MASK GENMASK(31, 8)
154 #define SNOR_PROTO_INST_MASK GENMASK(23, 16)160 #define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)166 #define SNOR_PROTO_DATA_MASK GENMASK(7, 0)352 #define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)357 #define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)363 #define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)369 #define SNOR_HWCAPS_READ_OCTAL GENMASK(14, 11)384 #define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)387 #define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)392 #define SNOR_HWCAPS_PP_OCTAL GENMASK(22, 20)
62 #define CHAN_PROTCTL_MASK GENMASK(2, 0)
200 #define I3C_CCC_STATUS_PENDING_INT(status) ((status) & GENMASK(3, 0))203 (((status) & GENMASK(7, 6)) >> 6)268 #define I3C_CCC_MAX_SDR_FSCL_MASK GENMASK(2, 0)