1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Texas Instruments System Control Interface Protocol
4 *
5 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
6 * Nishanth Menon
7 */
8
9 #ifndef __TISCI_PROTOCOL_H
10 #define __TISCI_PROTOCOL_H
11
12 /**
13 * struct ti_sci_version_info - version information structure
14 * @abi_major: Major ABI version. Change here implies risk of backward
15 * compatibility break.
16 * @abi_minor: Minor ABI version. Change here implies new feature addition,
17 * or compatible change in ABI.
18 * @firmware_revision: Firmware revision (not usually used).
19 * @firmware_description: Firmware description (not usually used).
20 */
21 struct ti_sci_version_info {
22 u8 abi_major;
23 u8 abi_minor;
24 u16 firmware_revision;
25 char firmware_description[32];
26 };
27
28 struct ti_sci_handle;
29
30 /**
31 * struct ti_sci_core_ops - SoC Core Operations
32 * @reboot_device: Reboot the SoC
33 * Returns 0 for successful request(ideally should never return),
34 * else returns corresponding error value.
35 */
36 struct ti_sci_core_ops {
37 int (*reboot_device)(const struct ti_sci_handle *handle);
38 };
39
40 /**
41 * struct ti_sci_dev_ops - Device control operations
42 * @get_device: Command to request for device managed by TISCI
43 * Returns 0 for successful exclusive request, else returns
44 * corresponding error message.
45 * @idle_device: Command to idle a device managed by TISCI
46 * Returns 0 for successful exclusive request, else returns
47 * corresponding error message.
48 * @put_device: Command to release a device managed by TISCI
49 * Returns 0 for successful release, else returns corresponding
50 * error message.
51 * @is_valid: Check if the device ID is a valid ID.
52 * Returns 0 if the ID is valid, else returns corresponding error.
53 * @get_context_loss_count: Command to retrieve context loss counter - this
54 * increments every time the device looses context. Overflow
55 * is possible.
56 * - count: pointer to u32 which will retrieve counter
57 * Returns 0 for successful information request and count has
58 * proper data, else returns corresponding error message.
59 * @is_idle: Reports back about device idle state
60 * - req_state: Returns requested idle state
61 * Returns 0 for successful information request and req_state and
62 * current_state has proper data, else returns corresponding error
63 * message.
64 * @is_stop: Reports back about device stop state
65 * - req_state: Returns requested stop state
66 * - current_state: Returns current stop state
67 * Returns 0 for successful information request and req_state and
68 * current_state has proper data, else returns corresponding error
69 * message.
70 * @is_on: Reports back about device ON(or active) state
71 * - req_state: Returns requested ON state
72 * - current_state: Returns current ON state
73 * Returns 0 for successful information request and req_state and
74 * current_state has proper data, else returns corresponding error
75 * message.
76 * @is_transitioning: Reports back if the device is in the middle of transition
77 * of state.
78 * -current_state: Returns 'true' if currently transitioning.
79 * @set_device_resets: Command to configure resets for device managed by TISCI.
80 * -reset_state: Device specific reset bit field
81 * Returns 0 for successful request, else returns
82 * corresponding error message.
83 * @get_device_resets: Command to read state of resets for device managed
84 * by TISCI.
85 * -reset_state: pointer to u32 which will retrieve resets
86 * Returns 0 for successful request, else returns
87 * corresponding error message.
88 *
89 * NOTE: for all these functions, the following parameters are generic in
90 * nature:
91 * -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
92 * -id: Device Identifier
93 *
94 * Request for the device - NOTE: the client MUST maintain integrity of
95 * usage count by balancing get_device with put_device. No refcounting is
96 * managed by driver for that purpose.
97 */
98 struct ti_sci_dev_ops {
99 int (*get_device)(const struct ti_sci_handle *handle, u32 id);
100 int (*get_device_exclusive)(const struct ti_sci_handle *handle, u32 id);
101 int (*idle_device)(const struct ti_sci_handle *handle, u32 id);
102 int (*idle_device_exclusive)(const struct ti_sci_handle *handle,
103 u32 id);
104 int (*put_device)(const struct ti_sci_handle *handle, u32 id);
105 int (*is_valid)(const struct ti_sci_handle *handle, u32 id);
106 int (*get_context_loss_count)(const struct ti_sci_handle *handle,
107 u32 id, u32 *count);
108 int (*is_idle)(const struct ti_sci_handle *handle, u32 id,
109 bool *requested_state);
110 int (*is_stop)(const struct ti_sci_handle *handle, u32 id,
111 bool *req_state, bool *current_state);
112 int (*is_on)(const struct ti_sci_handle *handle, u32 id,
113 bool *req_state, bool *current_state);
114 int (*is_transitioning)(const struct ti_sci_handle *handle, u32 id,
115 bool *current_state);
116 int (*set_device_resets)(const struct ti_sci_handle *handle, u32 id,
117 u32 reset_state);
118 int (*get_device_resets)(const struct ti_sci_handle *handle, u32 id,
119 u32 *reset_state);
120 };
121
122 /**
123 * struct ti_sci_clk_ops - Clock control operations
124 * @get_clock: Request for activation of clock and manage by processor
125 * - needs_ssc: 'true' if Spread Spectrum clock is desired.
126 * - can_change_freq: 'true' if frequency change is desired.
127 * - enable_input_term: 'true' if input termination is desired.
128 * @idle_clock: Request for Idling a clock managed by processor
129 * @put_clock: Release the clock to be auto managed by TISCI
130 * @is_auto: Is the clock being auto managed
131 * - req_state: state indicating if the clock is auto managed
132 * @is_on: Is the clock ON
133 * - req_state: if the clock is requested to be forced ON
134 * - current_state: if the clock is currently ON
135 * @is_off: Is the clock OFF
136 * - req_state: if the clock is requested to be forced OFF
137 * - current_state: if the clock is currently Gated
138 * @set_parent: Set the clock source of a specific device clock
139 * - parent_id: Parent clock identifier to set.
140 * @get_parent: Get the current clock source of a specific device clock
141 * - parent_id: Parent clock identifier which is the parent.
142 * @get_num_parents: Get the number of parents of the current clock source
143 * - num_parents: returns the number of parent clocks.
144 * @get_best_match_freq: Find a best matching frequency for a frequency
145 * range.
146 * - match_freq: Best matching frequency in Hz.
147 * @set_freq: Set the Clock frequency
148 * @get_freq: Get the Clock frequency
149 * - current_freq: Frequency in Hz that the clock is at.
150 *
151 * NOTE: for all these functions, the following parameters are generic in
152 * nature:
153 * -handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
154 * -did: Device identifier this request is for
155 * -cid: Clock identifier for the device for this request.
156 * Each device has it's own set of clock inputs. This indexes
157 * which clock input to modify.
158 * -min_freq: The minimum allowable frequency in Hz. This is the minimum
159 * allowable programmed frequency and does not account for clock
160 * tolerances and jitter.
161 * -target_freq: The target clock frequency in Hz. A frequency will be
162 * processed as close to this target frequency as possible.
163 * -max_freq: The maximum allowable frequency in Hz. This is the maximum
164 * allowable programmed frequency and does not account for clock
165 * tolerances and jitter.
166 *
167 * Request for the clock - NOTE: the client MUST maintain integrity of
168 * usage count by balancing get_clock with put_clock. No refcounting is
169 * managed by driver for that purpose.
170 */
171 struct ti_sci_clk_ops {
172 int (*get_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid,
173 bool needs_ssc, bool can_change_freq,
174 bool enable_input_term);
175 int (*idle_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid);
176 int (*put_clock)(const struct ti_sci_handle *handle, u32 did, u32 cid);
177 int (*is_auto)(const struct ti_sci_handle *handle, u32 did, u32 cid,
178 bool *req_state);
179 int (*is_on)(const struct ti_sci_handle *handle, u32 did, u32 cid,
180 bool *req_state, bool *current_state);
181 int (*is_off)(const struct ti_sci_handle *handle, u32 did, u32 cid,
182 bool *req_state, bool *current_state);
183 int (*set_parent)(const struct ti_sci_handle *handle, u32 did, u32 cid,
184 u32 parent_id);
185 int (*get_parent)(const struct ti_sci_handle *handle, u32 did, u32 cid,
186 u32 *parent_id);
187 int (*get_num_parents)(const struct ti_sci_handle *handle, u32 did,
188 u32 cid, u32 *num_parents);
189 int (*get_best_match_freq)(const struct ti_sci_handle *handle, u32 did,
190 u32 cid, u64 min_freq, u64 target_freq,
191 u64 max_freq, u64 *match_freq);
192 int (*set_freq)(const struct ti_sci_handle *handle, u32 did, u32 cid,
193 u64 min_freq, u64 target_freq, u64 max_freq);
194 int (*get_freq)(const struct ti_sci_handle *handle, u32 did, u32 cid,
195 u64 *current_freq);
196 };
197
198 /**
199 * struct ti_sci_rm_core_ops - Resource management core operations
200 * @get_range: Get a range of resources belonging to ti sci host.
201 * @get_rage_from_shost: Get a range of resources belonging to
202 * specified host id.
203 * - s_host: Host processing entity to which the
204 * resources are allocated
205 *
206 * NOTE: for these functions, all the parameters are consolidated and defined
207 * as below:
208 * - handle: Pointer to TISCI handle as retrieved by *ti_sci_get_handle
209 * - dev_id: TISCI device ID.
210 * - subtype: Resource assignment subtype that is being requested
211 * from the given device.
212 * - range_start: Start index of the resource range
213 * - range_end: Number of resources in the range
214 */
215 struct ti_sci_rm_core_ops {
216 int (*get_range)(const struct ti_sci_handle *handle, u32 dev_id,
217 u8 subtype, u16 *range_start, u16 *range_num);
218 int (*get_range_from_shost)(const struct ti_sci_handle *handle,
219 u32 dev_id, u8 subtype, u8 s_host,
220 u16 *range_start, u16 *range_num);
221 };
222
223 /**
224 * struct ti_sci_rm_irq_ops: IRQ management operations
225 * @set_irq: Set an IRQ route between the requested source
226 * and destination
227 * @set_event_map: Set an Event based peripheral irq to Interrupt
228 * Aggregator.
229 * @free_irq: Free an an IRQ route between the requested source
230 * destination.
231 * @free_event_map: Free an event based peripheral irq to Interrupt
232 * Aggregator.
233 */
234 struct ti_sci_rm_irq_ops {
235 int (*set_irq)(const struct ti_sci_handle *handle, u16 src_id,
236 u16 src_index, u16 dst_id, u16 dst_host_irq);
237 int (*set_event_map)(const struct ti_sci_handle *handle, u16 src_id,
238 u16 src_index, u16 ia_id, u16 vint,
239 u16 global_event, u8 vint_status_bit);
240 int (*free_irq)(const struct ti_sci_handle *handle, u16 src_id,
241 u16 src_index, u16 dst_id, u16 dst_host_irq);
242 int (*free_event_map)(const struct ti_sci_handle *handle, u16 src_id,
243 u16 src_index, u16 ia_id, u16 vint,
244 u16 global_event, u8 vint_status_bit);
245 };
246
247 /* RA config.addr_lo parameter is valid for RM ring configure TI_SCI message */
248 #define TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID BIT(0)
249 /* RA config.addr_hi parameter is valid for RM ring configure TI_SCI message */
250 #define TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID BIT(1)
251 /* RA config.count parameter is valid for RM ring configure TI_SCI message */
252 #define TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID BIT(2)
253 /* RA config.mode parameter is valid for RM ring configure TI_SCI message */
254 #define TI_SCI_MSG_VALUE_RM_RING_MODE_VALID BIT(3)
255 /* RA config.size parameter is valid for RM ring configure TI_SCI message */
256 #define TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID BIT(4)
257 /* RA config.order_id parameter is valid for RM ring configure TISCI message */
258 #define TI_SCI_MSG_VALUE_RM_RING_ORDER_ID_VALID BIT(5)
259
260 #define TI_SCI_MSG_VALUE_RM_ALL_NO_ORDER \
261 (TI_SCI_MSG_VALUE_RM_RING_ADDR_LO_VALID | \
262 TI_SCI_MSG_VALUE_RM_RING_ADDR_HI_VALID | \
263 TI_SCI_MSG_VALUE_RM_RING_COUNT_VALID | \
264 TI_SCI_MSG_VALUE_RM_RING_MODE_VALID | \
265 TI_SCI_MSG_VALUE_RM_RING_SIZE_VALID)
266
267 /**
268 * struct ti_sci_rm_ringacc_ops - Ring Accelerator Management operations
269 * @config: configure the SoC Navigator Subsystem Ring Accelerator ring
270 * @get_config: get the SoC Navigator Subsystem Ring Accelerator ring
271 * configuration
272 */
273 struct ti_sci_rm_ringacc_ops {
274 int (*config)(const struct ti_sci_handle *handle,
275 u32 valid_params, u16 nav_id, u16 index,
276 u32 addr_lo, u32 addr_hi, u32 count, u8 mode,
277 u8 size, u8 order_id
278 );
279 int (*get_config)(const struct ti_sci_handle *handle,
280 u32 nav_id, u32 index, u8 *mode,
281 u32 *addr_lo, u32 *addr_hi, u32 *count,
282 u8 *size, u8 *order_id);
283 };
284
285 /**
286 * struct ti_sci_rm_psil_ops - PSI-L thread operations
287 * @pair: pair PSI-L source thread to a destination thread.
288 * If the src_thread is mapped to UDMA tchan, the corresponding channel's
289 * TCHAN_THRD_ID register is updated.
290 * If the dst_thread is mapped to UDMA rchan, the corresponding channel's
291 * RCHAN_THRD_ID register is updated.
292 * @unpair: unpair PSI-L source thread from a destination thread.
293 * If the src_thread is mapped to UDMA tchan, the corresponding channel's
294 * TCHAN_THRD_ID register is cleared.
295 * If the dst_thread is mapped to UDMA rchan, the corresponding channel's
296 * RCHAN_THRD_ID register is cleared.
297 */
298 struct ti_sci_rm_psil_ops {
299 int (*pair)(const struct ti_sci_handle *handle, u32 nav_id,
300 u32 src_thread, u32 dst_thread);
301 int (*unpair)(const struct ti_sci_handle *handle, u32 nav_id,
302 u32 src_thread, u32 dst_thread);
303 };
304
305 /* UDMAP channel types */
306 #define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR 2
307 #define TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR_SB 3 /* RX only */
308 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBRR 10
309 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_PBVR 11
310 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR 12
311 #define TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBVR 13
312
313 #define TI_SCI_RM_UDMAP_RX_FLOW_DESC_HOST 0
314 #define TI_SCI_RM_UDMAP_RX_FLOW_DESC_MONO 2
315
316 #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_64_BYTES 1
317 #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_128_BYTES 2
318 #define TI_SCI_RM_UDMAP_CHAN_BURST_SIZE_256_BYTES 3
319
320 /* UDMAP TX/RX channel valid_params common declarations */
321 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PAUSE_ON_ERR_VALID BIT(0)
322 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ATYPE_VALID BIT(1)
323 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CHAN_TYPE_VALID BIT(2)
324 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_FETCH_SIZE_VALID BIT(3)
325 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_CQ_QNUM_VALID BIT(4)
326 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_PRIORITY_VALID BIT(5)
327 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_QOS_VALID BIT(6)
328 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_ORDER_ID_VALID BIT(7)
329 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_SCHED_PRIORITY_VALID BIT(8)
330 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_BURST_SIZE_VALID BIT(14)
331
332 /**
333 * Configures a Navigator Subsystem UDMAP transmit channel
334 *
335 * Configures a Navigator Subsystem UDMAP transmit channel registers.
336 * See @ti_sci_msg_rm_udmap_tx_ch_cfg_req
337 */
338 struct ti_sci_msg_rm_udmap_tx_ch_cfg {
339 u32 valid_params;
340 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_EINFO_VALID BIT(9)
341 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FILT_PSWORDS_VALID BIT(10)
342 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_SUPR_TDPKT_VALID BIT(11)
343 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_CREDIT_COUNT_VALID BIT(12)
344 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_TX_FDEPTH_VALID BIT(13)
345 u16 nav_id;
346 u16 index;
347 u8 tx_pause_on_err;
348 u8 tx_filt_einfo;
349 u8 tx_filt_pswords;
350 u8 tx_atype;
351 u8 tx_chan_type;
352 u8 tx_supr_tdpkt;
353 u16 tx_fetch_size;
354 u8 tx_credit_count;
355 u16 txcq_qnum;
356 u8 tx_priority;
357 u8 tx_qos;
358 u8 tx_orderid;
359 u16 fdepth;
360 u8 tx_sched_priority;
361 u8 tx_burst_size;
362 };
363
364 /**
365 * Configures a Navigator Subsystem UDMAP receive channel
366 *
367 * Configures a Navigator Subsystem UDMAP receive channel registers.
368 * See @ti_sci_msg_rm_udmap_rx_ch_cfg_req
369 */
370 struct ti_sci_msg_rm_udmap_rx_ch_cfg {
371 u32 valid_params;
372 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_START_VALID BIT(9)
373 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_FLOWID_CNT_VALID BIT(10)
374 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_SHORT_VALID BIT(11)
375 #define TI_SCI_MSG_VALUE_RM_UDMAP_CH_RX_IGNORE_LONG_VALID BIT(12)
376 u16 nav_id;
377 u16 index;
378 u16 rx_fetch_size;
379 u16 rxcq_qnum;
380 u8 rx_priority;
381 u8 rx_qos;
382 u8 rx_orderid;
383 u8 rx_sched_priority;
384 u16 flowid_start;
385 u16 flowid_cnt;
386 u8 rx_pause_on_err;
387 u8 rx_atype;
388 u8 rx_chan_type;
389 u8 rx_ignore_short;
390 u8 rx_ignore_long;
391 u8 rx_burst_size;
392 };
393
394 /**
395 * Configures a Navigator Subsystem UDMAP receive flow
396 *
397 * Configures a Navigator Subsystem UDMAP receive flow's registers.
398 * See @tis_ci_msg_rm_udmap_flow_cfg_req
399 */
400 struct ti_sci_msg_rm_udmap_flow_cfg {
401 u32 valid_params;
402 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_EINFO_PRESENT_VALID BIT(0)
403 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PSINFO_PRESENT_VALID BIT(1)
404 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_ERROR_HANDLING_VALID BIT(2)
405 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DESC_TYPE_VALID BIT(3)
406 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SOP_OFFSET_VALID BIT(4)
407 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_QNUM_VALID BIT(5)
408 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_VALID BIT(6)
409 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_VALID BIT(7)
410 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_VALID BIT(8)
411 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_VALID BIT(9)
412 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_HI_SEL_VALID BIT(10)
413 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_SRC_TAG_LO_SEL_VALID BIT(11)
414 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_HI_SEL_VALID BIT(12)
415 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_DEST_TAG_LO_SEL_VALID BIT(13)
416 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ0_SZ0_QNUM_VALID BIT(14)
417 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ1_QNUM_VALID BIT(15)
418 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ2_QNUM_VALID BIT(16)
419 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_FDQ3_QNUM_VALID BIT(17)
420 #define TI_SCI_MSG_VALUE_RM_UDMAP_FLOW_PS_LOCATION_VALID BIT(18)
421 u16 nav_id;
422 u16 flow_index;
423 u8 rx_einfo_present;
424 u8 rx_psinfo_present;
425 u8 rx_error_handling;
426 u8 rx_desc_type;
427 u16 rx_sop_offset;
428 u16 rx_dest_qnum;
429 u8 rx_src_tag_hi;
430 u8 rx_src_tag_lo;
431 u8 rx_dest_tag_hi;
432 u8 rx_dest_tag_lo;
433 u8 rx_src_tag_hi_sel;
434 u8 rx_src_tag_lo_sel;
435 u8 rx_dest_tag_hi_sel;
436 u8 rx_dest_tag_lo_sel;
437 u16 rx_fdq0_sz0_qnum;
438 u16 rx_fdq1_qnum;
439 u16 rx_fdq2_qnum;
440 u16 rx_fdq3_qnum;
441 u8 rx_ps_location;
442 };
443
444 /**
445 * struct ti_sci_rm_udmap_ops - UDMA Management operations
446 * @tx_ch_cfg: configure SoC Navigator Subsystem UDMA transmit channel.
447 * @rx_ch_cfg: configure SoC Navigator Subsystem UDMA receive channel.
448 * @rx_flow_cfg1: configure SoC Navigator Subsystem UDMA receive flow.
449 */
450 struct ti_sci_rm_udmap_ops {
451 int (*tx_ch_cfg)(const struct ti_sci_handle *handle,
452 const struct ti_sci_msg_rm_udmap_tx_ch_cfg *params);
453 int (*rx_ch_cfg)(const struct ti_sci_handle *handle,
454 const struct ti_sci_msg_rm_udmap_rx_ch_cfg *params);
455 int (*rx_flow_cfg)(const struct ti_sci_handle *handle,
456 const struct ti_sci_msg_rm_udmap_flow_cfg *params);
457 };
458
459 /**
460 * struct ti_sci_proc_ops - Processor Control operations
461 * @request: Request to control a physical processor. The requesting host
462 * should be in the processor access list
463 * @release: Relinquish a physical processor control
464 * @handover: Handover a physical processor control to another host
465 * in the permitted list
466 * @set_config: Set base configuration of a processor
467 * @set_control: Setup limited control flags in specific cases
468 * @get_status: Get the state of physical processor
469 *
470 * NOTE: The following paramteres are generic in nature for all these ops,
471 * -handle: Pointer to TI SCI handle as retrieved by *ti_sci_get_handle
472 * -pid: Processor ID
473 * -hid: Host ID
474 */
475 struct ti_sci_proc_ops {
476 int (*request)(const struct ti_sci_handle *handle, u8 pid);
477 int (*release)(const struct ti_sci_handle *handle, u8 pid);
478 int (*handover)(const struct ti_sci_handle *handle, u8 pid, u8 hid);
479 int (*set_config)(const struct ti_sci_handle *handle, u8 pid,
480 u64 boot_vector, u32 cfg_set, u32 cfg_clr);
481 int (*set_control)(const struct ti_sci_handle *handle, u8 pid,
482 u32 ctrl_set, u32 ctrl_clr);
483 int (*get_status)(const struct ti_sci_handle *handle, u8 pid,
484 u64 *boot_vector, u32 *cfg_flags, u32 *ctrl_flags,
485 u32 *status_flags);
486 };
487
488 /**
489 * struct ti_sci_ops - Function support for TI SCI
490 * @dev_ops: Device specific operations
491 * @clk_ops: Clock specific operations
492 * @rm_core_ops: Resource management core operations.
493 * @rm_irq_ops: IRQ management specific operations
494 * @proc_ops: Processor Control specific operations
495 */
496 struct ti_sci_ops {
497 struct ti_sci_core_ops core_ops;
498 struct ti_sci_dev_ops dev_ops;
499 struct ti_sci_clk_ops clk_ops;
500 struct ti_sci_rm_core_ops rm_core_ops;
501 struct ti_sci_rm_irq_ops rm_irq_ops;
502 struct ti_sci_rm_ringacc_ops rm_ring_ops;
503 struct ti_sci_rm_psil_ops rm_psil_ops;
504 struct ti_sci_rm_udmap_ops rm_udmap_ops;
505 struct ti_sci_proc_ops proc_ops;
506 };
507
508 /**
509 * struct ti_sci_handle - Handle returned to TI SCI clients for usage.
510 * @version: structure containing version information
511 * @ops: operations that are made available to TI SCI clients
512 */
513 struct ti_sci_handle {
514 struct ti_sci_version_info version;
515 struct ti_sci_ops ops;
516 };
517
518 #define TI_SCI_RESOURCE_NULL 0xffff
519
520 /**
521 * struct ti_sci_resource_desc - Description of TI SCI resource instance range.
522 * @start: Start index of the resource.
523 * @num: Number of resources.
524 * @res_map: Bitmap to manage the allocation of these resources.
525 */
526 struct ti_sci_resource_desc {
527 u16 start;
528 u16 num;
529 unsigned long *res_map;
530 };
531
532 /**
533 * struct ti_sci_resource - Structure representing a resource assigned
534 * to a device.
535 * @sets: Number of sets available from this resource type
536 * @lock: Lock to guard the res map in each set.
537 * @desc: Array of resource descriptors.
538 */
539 struct ti_sci_resource {
540 u16 sets;
541 raw_spinlock_t lock;
542 struct ti_sci_resource_desc *desc;
543 };
544
545 #if IS_ENABLED(CONFIG_TI_SCI_PROTOCOL)
546 const struct ti_sci_handle *ti_sci_get_handle(struct device *dev);
547 int ti_sci_put_handle(const struct ti_sci_handle *handle);
548 const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev);
549 const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
550 const char *property);
551 const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
552 const char *property);
553 u16 ti_sci_get_free_resource(struct ti_sci_resource *res);
554 void ti_sci_release_resource(struct ti_sci_resource *res, u16 id);
555 u32 ti_sci_get_num_resources(struct ti_sci_resource *res);
556 struct ti_sci_resource *
557 devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
558 struct device *dev, u32 dev_id, char *of_prop);
559
560 #else /* CONFIG_TI_SCI_PROTOCOL */
561
ti_sci_get_handle(struct device * dev)562 static inline const struct ti_sci_handle *ti_sci_get_handle(struct device *dev)
563 {
564 return ERR_PTR(-EINVAL);
565 }
566
ti_sci_put_handle(const struct ti_sci_handle * handle)567 static inline int ti_sci_put_handle(const struct ti_sci_handle *handle)
568 {
569 return -EINVAL;
570 }
571
572 static inline
devm_ti_sci_get_handle(struct device * dev)573 const struct ti_sci_handle *devm_ti_sci_get_handle(struct device *dev)
574 {
575 return ERR_PTR(-EINVAL);
576 }
577
578 static inline
ti_sci_get_by_phandle(struct device_node * np,const char * property)579 const struct ti_sci_handle *ti_sci_get_by_phandle(struct device_node *np,
580 const char *property)
581 {
582 return ERR_PTR(-EINVAL);
583 }
584
585 static inline
devm_ti_sci_get_by_phandle(struct device * dev,const char * property)586 const struct ti_sci_handle *devm_ti_sci_get_by_phandle(struct device *dev,
587 const char *property)
588 {
589 return ERR_PTR(-EINVAL);
590 }
591
ti_sci_get_free_resource(struct ti_sci_resource * res)592 static inline u16 ti_sci_get_free_resource(struct ti_sci_resource *res)
593 {
594 return TI_SCI_RESOURCE_NULL;
595 }
596
ti_sci_release_resource(struct ti_sci_resource * res,u16 id)597 static inline void ti_sci_release_resource(struct ti_sci_resource *res, u16 id)
598 {
599 }
600
ti_sci_get_num_resources(struct ti_sci_resource * res)601 static inline u32 ti_sci_get_num_resources(struct ti_sci_resource *res)
602 {
603 return 0;
604 }
605
606 static inline struct ti_sci_resource *
devm_ti_sci_get_of_resource(const struct ti_sci_handle * handle,struct device * dev,u32 dev_id,char * of_prop)607 devm_ti_sci_get_of_resource(const struct ti_sci_handle *handle,
608 struct device *dev, u32 dev_id, char *of_prop)
609 {
610 return ERR_PTR(-EINVAL);
611 }
612 #endif /* CONFIG_TI_SCI_PROTOCOL */
613
614 #endif /* __TISCI_PROTOCOL_H */
615