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/Documentation/hwmon/
Dlochnagar.rst31 power1_average_interval Power averaging time input valid from 1 to 1708mS
33 in1_input Measured voltage for 1V8 DSP (milliVolts)
34 in1_label "1V8 DSP"
35 curr2_input Measured current for 1V8 DSP (milliAmps)
36 curr2_label "1V8 DSP"
37 power2_average Measured average power for 1V8 DSP (microWatts)
38 power2_average_interval Power averaging time input valid from 1 to 1708mS
39 power2_label "1V8 DSP"
40 in2_input Measured voltage for 1V8 CDC (milliVolts)
41 in2_label "1V8 CDC"
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/Documentation/devicetree/bindings/mmc/
Dnvidia,tegra20-sdhci.txt44 - pinctrl-names, pinctrl-0, pinctrl-1 : Specify pad voltage
45 configurations. Valid pinctrl-names are "sdmmc-3v3" and "sdmmc-1v8"
48 pinctrl-1.
49 - pinctrl-names : "sdmmc-3v3-drv" and "sdmmc-1v8-drv" are applicable for
52 using pads at 3V3 and 1V8 levels.
53 - nvidia,only-1-8-v : The presence of this property indicates that the
58 - nvidia,pad-autocal-pull-up-offset-1v8,
59 nvidia,pad-autocal-pull-down-offset-1v8 : Specify drive strength
65 - nvidia,pad-autocal-pull-up-offset-1v8-timeout,
66 nvidia,pad-autocal-pull-down-offset-1v8-timeout : Specify drive
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/Documentation/devicetree/bindings/media/
Ds5p-mfc.txt14 (d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC
15 (e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC
55 #address-cells = <1>;
56 #size-cells = <1>;
/Documentation/devicetree/bindings/regulator/
Dfixed-regulator.yaml40 maxItems: 1
47 maxItems: 1
75 reg_1v8: regulator-1v8 {
77 regulator-name = "1v8";
Dst,stm32mp1-pwr-reg.txt5 - reg11 for regulator 1V1
6 - reg18 for regulator 1V8
Das3722-regulator.txt34 controlling this rail. Valid values are 0, 1, 2 ad 3.
36 1: Rail is controlled by ENABLE1 input pin.
66 ams,ext-control = <1>;
84 regulator-name = "vdd-1v8";
Dregulator-max77620.txt22 in-ldo0-1-supply: Input supply for LDO0 and LDO1.
125 in-ldo0-1-supply = <&max77620_sd2>;
153 regulator-name = "vdd-1v8";
/Documentation/devicetree/bindings/arm/tegra/
Dnvidia,tegra186-pmc.txt101 sdmmc1_1v8: sdmmc1-1v8 {
120 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
122 pinctrl-1 = <&sdmmc1_1v8>;
130 pinctrl-1 = <&hdmi_on>;
Dnvidia,tegra20-pmc.txt32 Valid values are 0, 1 and 2:
34 1 (LP1): CPU voltage off and DRAM in self-refresh
89 nvidia,suspend-mode = <1>;
113 #address-cells = <1>;
139 3d1 3D Graphics 1 Tegra30
271 sdmmc1_1v8: sdmmc1-1v8 {
290 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
292 pinctrl-1 = <&sdmmc1_1v8>;
298 pinctrl-1 = <&hdmi_on>;
/Documentation/devicetree/bindings/watchdog/
Dsbsa-gwdt.txt14 1: Watchdog control frame;
23 Example for FVP Foundation Model v8:
/Documentation/devicetree/bindings/clock/
Dti,cdce925.txt4 This binding uses the common clock binding[1].
6 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
16 - "ti,cdce913": 1-PLL, 3 Outputs
22 - #clock-cells: From common clock bindings: Shall be 1.
44 #clock-cells = <1>;
46 vdd-supply = <&1v8-reg>;
48 /* PLL options to get SSC 1% centered */
Dsilabs,si5341.txt4 [1] Si5341 Data Sheet
33 The first value is "0" for outputs, "1" for synthesizers.
55 - #address-cells: shall be set to 1.
74 1 = differential (defaults to LVDS levels)
99 #address-cells = <1>;
110 silabs,format = <1>; /* LVDS 3v3 */
118 * LVDS 1v8
122 silabs,format = <1>; /* LVDS 1v8 */
146 assigned-clocks = <&si5341 0 7>, <&si5341 1 3>;
147 assigned-clock-parents = <&si5341 1 3>;
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/Documentation/devicetree/bindings/phy/
Dphy-stm32-usbphyc.txt11 |_ PHY port#1 _________________ HOST controller
13 | / 1|________________|
26 - #address-cells: number of address cells for phys sub-nodes, must be <1>
43 - vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY
44 - vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY
46 port#1 and must be <1> for PHY port#2, to select USB controller
55 #address-cells = <1>;
66 usbphyc_port1: usb-phy@1 {
67 reg = <1>;
71 #phy-cells = <1>;
/Documentation/devicetree/bindings/arm/
Dcpus.yaml43 maxItems: 1
68 On ARM v8 64-bit systems this property is required
79 * If cpus node's #address-cells property is set to 1
166 # On ARM v8 64-bit this property is required
210 On ARM v8 64-bit systems must be a two cell
286 #address-cells = <1>;
294 cpu@1 {
317 #address-cells = <1>;
330 #address-cells = <1>;
353 cpu@1 {
Didle-states.txt6 1 - Introduction
59 Diagram 1: CPU idle state execution phases
139 0| 1 time(ms)
141 Graph 1: Energy vs time example
143 The graph is split in two parts delimited by time 1ms on the X-axis.
144 The graph curve with X-axis values = { x | 0 < x < 1ms } has a steep slope
147 The graph curve in the area delimited by X-axis values = {x | x > 1ms } has
210 a direct child of the cpus node [1] and provides a container where the
239 # On ARM v8 64-bit this property is required and must
264 rules ([5], 2.2.1 "Node names"), in particular state nodes which
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/Documentation/arm64/
Dsve.rst20 1. General
123 delivery. [1]
138 size and layout. Macros SVE_SIG_* are defined [1] to facilitate access to
148 extra space. Refer to [1] for further details about this mechanism.
389 vector length of the init process (PID 1).
415 A.1. Registers
428 * 1 VL-bit special-purpose predicate register FFR (the "first-fault register")
449 8VL-1 128 0 bit index
454 Z8 | : * V8 |
462 VL-1 0 +-------+
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/Documentation/devicetree/bindings/mfd/
Das3722.txt113 controlling this rail. Valid values are 0, 1, 2 ad 3.
115 1: Rail is controlled by ENABLE1 input pin.
189 ams,ext-control = <1>;
207 regulator-name = "vdd-1v8";