Searched +full:cortex +full:- +full:a15 +full:- +full:gic (Results 1 – 2 of 2) sorted by relevance
1 # SPDX-License-Identifier: GPL-2.03 ---4 $id: http://devicetree.org/schemas/interrupt-controller/arm,gic.yaml#5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Marc Zyngier <marc.zyngier@arm.com>13 ARM SMP cores are often associated with a GIC, providing per processor17 Primary GIC is attached directly to the CPU and typically has PPIs and SGIs.22 - $ref: /schemas/interrupt-controller.yaml#27 - items:28 - enum:[all …]
1 # SPDX-License-Identifier: GPL-2.03 ---5 $schema: http://devicetree.org/meta-schemas/core.yaml#10 - Marc Zyngier <marc.zyngier@arm.com>11 - Mark Rutland <mark.rutland@arm.com>13 ARM cores may have a per-core architected timer, which provides per-cpu timers,17 The per-core architected timer is attached to a GIC to deliver its18 per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC24 - items:25 - enum:[all …]