Searched +full:fixed +full:- +full:clock (Results 1 – 25 of 173) sorted by relevance
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| /Documentation/devicetree/bindings/clock/ |
| D | nuvoton,npcm750-clk.txt | 1 * Nuvoton NPCM7XX Clock Controller
3 Nuvoton Poleg BMC NPCM7XX contains an integrated clock controller, which
8 There are six fixed clocks that are generated outside the BMC. All clocks are of
9 a known fixed value that cannot be changed. clk_refclk, clk_mcbypck and
10 clk_sysbypck are inputs to the clock controller.
12 network. They are set on the device tree, but not used by the clock module. The
17 dt-bindings/clock/nuvoton,npcm7xx-clock.h
20 Required Properties of clock controller:
22 - compatible: "nuvoton,npcm750-clk" : for clock controller of Nuvoton
25 - reg: physical base address of the clock controller and length of
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| D | fixed-factor-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-factor-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Binding for simple fixed factor rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
16 - allwinner,sun4i-a10-pll3-2x-clk
17 - fixed-factor-clock
19 "#clock-cells":
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| D | cirrus,lochnagar.txt | 5 Logic devices on mini-cards, as well as allowing connection of
11 This binding document describes the binding for the clock portion of
15 [1] Clock : ../clock/clock-bindings.txt
18 [2] include/dt-bindings/clock/lochnagar.h
25 - compatible : One of the following strings:
26 "cirrus,lochnagar1-clk"
27 "cirrus,lochnagar2-clk"
29 - #clock-cells : Must be 1. The first cell indicates the clock
34 - clocks : Must contain an entry for each clock in clock-names.
35 - clock-names : May contain entries for each of the following
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| D | fixed-mmio-clock.txt | 1 Binding for simple memory mapped io fixed-rate clock sources.
2 The driver reads a clock frequency value from a single 32-bit memory mapped
3 I/O register and registers it as a fixed rate clock.
7 This binding uses the common clock binding[1].
9 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
12 - compatible : shall be "fixed-mmio-clock".
13 - #clock-cells : from common clock binding; shall be set to 0.
14 - reg : Address and length of the clock value register set.
17 - clock-output-names : From common clock binding.
21 #clock-cells = <0>;
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| D | fixed-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/clock/fixed-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Binding for simple fixed-rate clock sources
10 - Michael Turquette <mturquette@baylibre.com>
11 - Stephen Boyd <sboyd@kernel.org>
15 const: fixed-clock
17 "#clock-cells":
20 clock-frequency: true
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| D | imx8mn-clock.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/bindings/clock/imx8mn-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX8M Nano Clock Control Module Binding
10 - Anson Huang <Anson.Huang@nxp.com>
13 NXP i.MX8M Nano clock control module is an integrated clock controller, which
18 const: fsl,imx8mn-ccm
25 - description: 32k osc
26 - description: 24m osc
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| D | samsung,s5pv210-clock.txt | 1 * Samsung S5P6442/S5PC110/S5PV210 Clock Controller
3 Samsung S5P6442, S5PC110 and S5PV210 SoCs contain integrated clock
4 controller, which generates and supplies clock to various controllers
9 - compatible: should be one of following:
10 - "samsung,s5pv210-clock" : for clock controller of Samsung
12 - "samsung,s5p6442-clock" : for clock controller of Samsung
15 - reg: physical base address of the controller and length of memory mapped
18 - #clock-cells: should be 1.
21 dt-bindings/clock/s5pv210.h header and can be used in device tree sources.
26 that they are defined using standard clock bindings with following
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| D | lpc1850-cgu.txt | 1 * NXP LPC1850 Clock Generation Unit (CGU)
4 peripheral blocks of the LPC18xx. Each independent clock is called
5 a base clock and itself is one of the inputs to the two Clock
9 The CGU selects the inputs to the clock generators from multiple
10 clock sources, controls the clock generation, and routes the outputs
11 of the clock generators through the clock source bus to the output
12 stages. Each output stage provides an independent clock source and
15 - Above text taken from NXP LPC1850 User Manual.
18 This binding uses the common clock binding:
19 Documentation/devicetree/bindings/clock/clock-bindings.txt
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| D | clk-s5pv210-audss.txt | 1 * Samsung Audio Subsystem Clock Controller
3 The Samsung Audio Subsystem clock controller generates and supplies clocks
8 - compatible: should be "samsung,s5pv210-audss-clock".
9 - reg: physical base address and length of the controller's register set.
11 - #clock-cells: should be 1.
13 - clocks:
14 - hclk: AHB bus clock of the Audio Subsystem.
15 - xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
16 not specified (i.e. xusbxti is used for PLL reference), it is fixed to
17 a clock named "xxti".
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| D | keystone-pll.txt | 1 Status: Unstable - ABI compatibility may be broken in the future
9 This binding uses the common clock binding[1].
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 - #clock-cells : from common clock binding; shall be set to 0.
15 - compatible : shall be "ti,keystone,main-pll-clock" or "ti,keystone,pll-clock"
16 - clocks : parent clock phandle
17 - reg - pll control0 and pll multipler registers
18 - reg-names : control, multiplier and post-divider. The multiplier and
19 post-divider registers are applicable only for main pll clock
20 - fixed-postdiv : fixed post divider value. If absent, use clkod register bits
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| D | lpc1850-creg-clk.txt | 5 32 kHz oscillator driver with power up/down and clock gating. Next
6 is a fixed divider that creates a 1 kHz clock from the 32 kHz osc.
12 This binding uses the common clock binding:
13 Documentation/devicetree/bindings/clock/clock-bindings.txt
16 - compatible:
17 Should be "nxp,lpc1850-creg-clk"
18 - #clock-cells:
20 - clocks:
21 Shall contain a phandle to the fixed 32 kHz crystal.
23 The creg-clk node must be a child of the creg syscon node.
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| D | altr_socfpga.txt | 1 Device Tree Clock bindings for Altera's SoCFPGA platform
3 This binding uses the common clock binding[1].
5 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
8 - compatible : shall be one of the following:
9 "altr,socfpga-pll-clock" - for a PLL clock
10 "altr,socfpga-perip-clock" - The peripheral clock divided from the
11 PLL clock.
12 "altr,socfpga-gate-clk" - Clocks that directly feed peripherals and
15 - reg : shall be the control register offset from CLOCK_MANAGER's base for the clock.
16 - clocks : shall be the input parent clock phandle for the clock. This is
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| D | ingenic,cgu.txt | 3 The CGU in an Ingenic SoC provides all the clocks generated on-chip. It
5 to provide many different clock signals derived from only 2 external source
9 - compatible : Should be one of:
10 * ingenic,jz4740-cgu
11 * ingenic,jz4725b-cgu
12 * ingenic,jz4770-cgu
13 * ingenic,jz4780-cgu
14 - reg : The address & length of the CGU registers.
15 - clocks : List of phandle & clock specifiers for clocks external to the CGU.
16 Two such external clocks should be specified - first the external crystal
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| D | nvidia,tegra20-car.txt | 1 NVIDIA Tegra20 Clock And Reset Controller
3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
10 - compatible : Should be "nvidia,tegra20-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the
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| D | nvidia,tegra30-car.txt | 1 NVIDIA Tegra30 Clock And Reset Controller
3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
10 - compatible : Should be "nvidia,tegra30-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the
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| D | nvidia,tegra114-car.txt | 1 NVIDIA Tegra114 Clock And Reset Controller
3 This binding uses the common clock binding:
4 Documentation/devicetree/bindings/clock/clock-bindings.txt
6 The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
10 - compatible : Should be "nvidia,tegra114-car"
11 - reg : Should contain CAR registers location and length
12 - clocks : Should contain phandle and clock specifiers for two clocks:
13 the 32 KHz "32k_in", and the board-specific oscillator "osc".
14 - #clock-cells : Should be 1.
15 In clock consumers, this cell represents the clock ID exposed by the
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| /Documentation/devicetree/bindings/clock/ti/ |
| D | fixed-factor-clock.txt | 1 Binding for TI fixed factor rate clock sources.
3 Binding status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1], and also uses the autoidle
6 support from TI autoidle clock [2].
8 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
9 [2] Documentation/devicetree/bindings/clock/ti/autoidle.txt
12 - compatible : shall be "ti,fixed-factor-clock".
13 - #clock-cells : from common clock binding; shall be set to 0.
14 - ti,clock-div: fixed divider.
15 - ti,clock-mult: fixed multiplier.
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| D | autoidle.txt | 1 Binding for Texas Instruments autoidle clock.
3 Binding status: Unstable - ABI compatibility may be broken in the future
5 This binding uses the common clock binding[1]. It assumes a register mapped
6 clock which can be put to idle automatically by hardware based on the usage
7 and a configuration bit setting. Autoidle clock is never an individual
8 clock, it is always a derivative of some basic clock like a gate, divider,
9 or fixed-factor.
11 [1] Documentation/devicetree/bindings/clock/clock-bindings.txt
14 - reg : offset for the register controlling the autoidle
15 - ti,autoidle-shift : bit shift of the autoidle enable bit
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| /Documentation/devicetree/bindings/regulator/ |
| D | fixed-regulator.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/regulator/fixed-regulator.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Fixed Voltage regulators
10 - Liam Girdwood <lgirdwood@gmail.com>
11 - Mark Brown <broonie@kernel.org>
15 regulator.yaml, can also be used. However a fixed voltage regulator is
16 expected to have the regulator-min-microvolt and regulator-max-microvolt
20 - $ref: "regulator.yaml#"
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| /Documentation/devicetree/bindings/timer/ |
| D | marvell,armada-370-xp-timer.txt | 2 ---------------------------------------
5 - compatible: Should be one of the following
6 "marvell,armada-370-timer",
7 "marvell,armada-375-timer",
8 "marvell,armada-xp-timer".
9 - interrupts: Should contain the list of Global Timer interrupts and
11 - reg: Should contain location and length for timers register. First
15 Clocks required for compatible = "marvell,armada-370-timer":
16 - clocks : Must contain a single entry describing the clock input
18 Clocks required for compatibles = "marvell,armada-xp-timer",
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| /Documentation/devicetree/bindings/net/ |
| D | qca,ar71xx.txt | 2 - compatible: Should be "qca,<soc>-eth". Currently support compatibles are:
3 qca,ar7100-eth - Atheros AR7100
4 qca,ar7240-eth - Atheros AR7240
5 qca,ar7241-eth - Atheros AR7241
6 qca,ar7242-eth - Atheros AR7242
7 qca,ar9130-eth - Atheros AR9130
8 qca,ar9330-eth - Atheros AR9330
9 qca,ar9340-eth - Atheros AR9340
10 qca,qca9530-eth - Qualcomm Atheros QCA9530
11 qca,qca9550-eth - Qualcomm Atheros QCA9550
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| /Documentation/devicetree/bindings/mmc/ |
| D | marvell,xenon-sdhci.txt | 7 clock and PHY.
11 - compatible: should be one of the following
12 - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13 Must provide a second register area and marvell,pad-type.
14 - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15 - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
17 - clocks:
19 Require at least input clock for Xenon IP core. For Armada AP806 and
20 CP110, the AXI clock is also mandatory.
22 - clock-names:
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| /Documentation/devicetree/bindings/clock/sifive/ |
| D | fu540-prci.txt | 3 On the FU540 family of SoCs, most system-wide clock and reset integration
7 - compatible: Should be "sifive,<chip>-prci". Only one value is
8 supported: "sifive,fu540-c000-prci"
9 - reg: Should describe the PRCI's register target physical address region
10 - clocks: Should point to the hfclk device tree node and the rtcclk
11 device tree node. The RTC clock here is not a time-of-day clock,
12 but is instead a high-stability clock source for system timers
14 - #clock-cells: Should be <1>
16 The clock consumer should specify the desired clock via the clock ID
17 macros defined in include/dt-bindings/clock/sifive-fu540-prci.h.
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| /Documentation/devicetree/bindings/watchdog/ |
| D | marvel.txt | 5 - Compatibility : "marvell,orion-wdt"
6 "marvell,armada-370-wdt"
7 "marvell,armada-xp-wdt"
8 "marvell,armada-375-wdt"
9 "marvell,armada-380-wdt"
11 - reg : Should contain two entries: first one with the
15 For "marvell,armada-375-wdt" and "marvell,armada-380-wdt":
17 - reg : A third entry is mandatory and should contain the
20 Clocks required for compatibles = "marvell,orion-wdt",
21 "marvell,armada-370-wdt":
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| /Documentation/devicetree/bindings/hwmon/ |
| D | g762.txt | 5 - "compatible": must be either "gmt,g762" or "gmt,g763"
6 - "reg": I2C bus address of the device
7 - "clocks": a fixed clock providing input clock frequency
12 - "fan_startv": fan startup voltage. Accepted values are 0, 1, 2 and 3.
15 - "pwm_polarity": pwm polarity. Accepted values are 0 (positive duty)
18 - "fan_gear_mode": fan gear mode. Supported values are 0, 1 and 2.
21 unmodified (e.g. u-boot installed value).
25 at http://natisbad.org/NAS/refs/GMT_EDS-762_763-080710-0.2.pdf.
30 #address-cells = <1>;
31 #size-cells = <0>;
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