Searched full:pipeline (Results 1 – 25 of 48) sorted by relevance
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| /Documentation/gpu/ |
| D | komeda-kms.rst | 15 architecture. A display pipeline is made up of multiple individual and
16 functional pipeline stages called components, and every component has some
17 specific capabilities that can give the flowed pipeline pixel data a
24 Layer is the first pipeline stage, which prepares the pixel data for the next
58 Final stage of display pipeline, Timing controller is not for the pixel
76 Possible D71 Pipeline usage
94 Single pipeline data flow
98 :alt: Single pipeline digraph
99 :caption: Single pipeline data flow
140 Dual pipeline with Slave enabled
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| D | drm-kms.rst | 22 :alt: KMS Display Pipeline
23 :caption: KMS Display Pipeline Overview
86 Internally the output pipeline is a bit more complex and matches today's
90 :alt: KMS Output Pipeline
91 :caption: KMS Output Pipeline
93 digraph "Output Pipeline" {
102 label="Internal Pipeline"
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| /Documentation/devicetree/bindings/display/ |
| D | arm,komeda.txt | 18 Required properties for sub-node: pipeline@nq
19 Each device contains one or two pipeline sub-nodes (at least one), each
20 pipeline node should provide properties:
21 - reg: Zero-indexed identifier for the pipeline
27 - port: each pipeline connect to an encoder input port. The connection is
53 dp0_pipe0: pipeline@0 {
65 dp0_pipe1: pipeline@1 {
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| D | simple-framebuffer.yaml | 95 allwinner,pipeline:
96 description: Pipeline used by the framebuffer on Allwinner SoCs
111 amlogic,pipeline:
112 description: Pipeline used by the framebuffer on Amlogic SoCs
138 - allwinner,pipeline
148 - amlogic,pipeline
165 allwinner,pipeline = "de_be0-lcd0";
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| /Documentation/media/uapi/v4l/ |
| D | dev-subdev.rst | 97 responsible for configuring every block in the video pipeline according
98 to the requested format at the pipeline input and/or output.
101 image sizes at the output of a pipeline can be achieved using different
103 :ref:`pipeline-scaling`, where image scaling can be performed on both
109 .. kernel-figure:: pipeline.dot
110 :alt: pipeline.dot
115 High quality and high speed pipeline configuration
121 Depending on the use case (quality vs. speed), the pipeline must be
123 every point in the pipeline explicitly.
133 whole pipeline and making sure that connected pads have compatible
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| D | pixfmt-meta-intel-ipu3.rst | 66 Pipeline parameters
69 The pipeline parameters are passed to the "ipu3-imgu [01] parameters" metadata
73 Both 3A statistics and pipeline parameters described here are closely tied to
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| D | pixfmt-compressed.rst | 66 stateless video decoders that implement an H264 pipeline
117 MPEG-2 pipeline (using the :ref:`mem2mem` and :ref:`media-request-api`).
160 VP8 pipeline (using the :ref:`mem2mem` and :ref:`media-request-api`).
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| D | vidioc-streamon.rst | 109 pipeline configuration is invalid.
112 The driver implements Media Controller interface and the pipeline
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| /Documentation/devicetree/bindings/media/xilinx/ |
| D | xlnx,video.txt | 1 Xilinx Video IP Pipeline (VIPP)
7 Xilinx video IP pipeline processes video streams through one or more Xilinx
10 node of the VIPP represents as a top level node of the pipeline and defines
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| D | video.txt | 6 creating a video pipeline.
12 The whole pipeline is represented by an AMBA bus child node in the device
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| /Documentation/media/v4l-drivers/ |
| D | qcom_camss.rst | 38 - 1 / 2 VFE (Video Front End) module(s). Contain a pipeline of image processing
40 interface feeds the input data to the image processing pipeline. The image
41 processing pipeline contains also a scale and crop module at the end. Three
43 pipeline. The VFE also contains the AXI bus interface which writes the output
137 The media controller pipeline graph is as follows (with connected two / three
146 Media pipeline graph 8x16
152 Media pipeline graph 8x96
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| D | vimc.rst | 18 :alt: Diagram of the default media pipeline topology
21 Media pipeline graph on vimc
28 configuration on each linked subdevice to stream frames through the pipeline.
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| D | fimc.rst | 31 - dynamic pipeline re-configuration at runtime (re-attachment of any FIMC
109 In order to enable more precise camera pipeline control through the sub-device
113 In typical use case there could be a following capture pipeline configuration:
120 devices belonging to the pipeline is done at the video node driver.
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| D | imx7.rst | 68 inherit controls from the active entities in the current pipeline, so controls
77 CSI-2 receiver. The following example configures a video capture pipeline with
88 # Configure pads for pipeline
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| D | ipu3.rst | 110 Once the media pipeline is configured, desired sensor specific settings
268 RAW Bayer frames go through the following ImgU pipeline HW blocks to have the
287 The following steps prepare the ImgU pipeline for the image processing.
360 Overview of IPU3 pipeline
363 IPU3 pipeline has a number of image processing stages, each of which takes a
367 :alt: IPU3 ImgU Pipeline
368 :caption: IPU3 ImgU Pipeline Diagram
495 A few stages of the pipeline will be executed by firmware running on the ISP
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| D | imx.rst | 341 or mem2mem device node. With this pipeline, the VDIC can also operate
396 ipuX_vdic is included in the pipeline (ipuX_ic_prp is receiving from
433 This pipeline uses the preprocess encode entity to route frames directly
442 This pipeline routes frames from the CSI direct pad to the VDIC entity to
455 in the current pipeline, so controls can be accessed either directly
504 # Configure pads for OV5642 pipeline
508 # Configure pads for OV5640 pipeline
524 The following example configures a pipeline to capture from the ADV7180
546 This example configures a pipeline to capture from the ADV7180
590 The following example configures a direct conversion pipeline to capture
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| /Documentation/devicetree/bindings/media/ |
| D | fsl-pxp.txt | 1 Freescale Pixel Pipeline
4 The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine
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| /Documentation/media/ |
| D | .gitignore | 5 uapi/v4l/pipeline.svg
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| /Documentation/media/kapi/ |
| D | mc-core.rst | 24 in a System-on-Chip image processing pipeline), DMA channels or physical
209 When starting streaming, drivers must notify all entities in the pipeline to
217 the pipe argument will be stored in every entity in the pipeline.
219 in higher-level pipeline structures and can then access the
220 pipeline through the struct :c:type:`media_entity`
224 The pipeline pointer must be identical for all nested calls to the function.
251 for any entity which has sink pads in the pipeline. The
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| /Documentation/devicetree/bindings/arc/ |
| D | archs-pct.txt | 3 The ARC HS can be configured with a pipeline performance monitor for counting
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| D | pct.txt | 3 The ARC700 can be configured with a pipeline performance monitor for counting
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| /Documentation/devicetree/bindings/display/bridge/ |
| D | megachips-stdpxxxx-ge-b850v3-fw.txt | 5 The video processing pipeline on the second output on the GE B850v3:
15 The hardware do not provide control over the video processing pipeline, as the
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| /Documentation/ide/ |
| D | ChangeLog.ide-tape.1995-2002 | 91 * Added pipeline read mode. As a result, restores
163 * Abort read pipeline on EOD.
234 * - Limit size of pipeline
249 * Fixed off-by-one error in testing the pipeline length.
250 * Fixed handling of filemarks in the read pipeline.
255 * Set the minimum /proc/ide/hd?/settings values for "pipeline",
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| /Documentation/devicetree/bindings/display/sunxi/ |
| D | sun4i-drm.txt | 1 Allwinner A10 Display Pipeline
4 The Allwinner A10 Display pipeline is composed of several components
8 pipeline, when there are multiple components of the same type at the
21 For a two pipeline system such as the one depicted above, the lines
39 CEC. It is one end of the pipeline.
135 the pipeline.
212 TCON TOPs main purpose is to configure whole display pipeline. It determines
217 It allows display pipeline to be configured in very different ways:
411 Display Engine Pipeline
414 The display engine pipeline (and its entry point, since it can be
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| /Documentation/ABI/testing/ |
| D | configfs-usb-gadget-mass-storage | 10 num_buffers - Number of pipeline buffers. Valid numbers
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