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/Documentation/devicetree/bindings/arm/
Dpsci.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/arm/psci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Power State Coordination Interface (PSCI)
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
13 Firmware implementing the PSCI functions described in ARM document number
15 processors") can be used by Linux to initiate various CPU-centric power
21 Functions are invoked by trapping to the privilege level of the PSCI
25 r0 => 32-bit Function ID / return value
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Didle-states.txt6 1 - Introduction
10 where cores can be put in different low-power states (ranging from simple
12 the range of dynamic idle states that a processor can enter at run-time, can be
19 - Running
20 - Idle_standby
21 - Idle_retention
22 - Sleep
23 - Off
29 wake-up capabilities, hence it is not considered in this document).
39 2 - idle-states definitions
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Dcpu-capacity.txt6 1 - Introduction
15 2 - CPU capacity definition
19 heterogeneity. Such heterogeneity can come from micro-architectural differences
23 capture a first-order approximation of the relative performance of CPUs.
29 * A "single-threaded" or CPU affine benchmark
43 3 - capacity-dmips-mhz
46 capacity-dmips-mhz is an optional cpu node [1] property: u32 value
51 capacity-dmips-mhz property is all-or-nothing: if it is specified for a cpu
54 available, final capacities are calculated by directly using capacity-dmips-
58 4 - Examples
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Darm-boards2 -----------------------------------------------------------------------------
3 ARM's oldest Linux-supported platform with connectors for different core
7 compatible = "arm,integrator-ap"; /* Application Platform */
8 compatible = "arm,integrator-cp"; /* Compact Platform */
10 FPGA type interrupt controllers, see the versatile-fpga-irq binding doc.
14 - core-module: the root node to the Integrator platforms must have
15 a core-module with regs and the compatible string
16 "arm,core-module-integrator"
17 - external-bus-interface: the root node to the Integrator platforms
19 compatible-string "arm,external-bus-interface"
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Dcpus.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
21 with updates for 32-bit and 64-bit ARM systems provided in this document.
30 - square brackets define bitfields, eg reg[7:0] value of the bitfield in
31 the reg property contained in bits 7 down to 0
49 this property is required and must be set to 0.
52 required and matches the CPUID[11:0] register bits.
54 Bits [11:0] in the reg cell must be set to
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/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-qcom-hw.txt8 - compatible
11 Definition: must be "qcom,cpufreq-hw".
13 - clocks
18 - clock-names
23 - reg
25 Value type: <prop-encoded-array>
28 - reg-names
32 "freq-domain0", "freq-domain1".
34 - #freq-domain-cells:
38 * Property qcom,freq-domain
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Dcpufreq-mediatek.txt5 - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock names.
6 - clock-names: Should contain the following:
7 "cpu" - The multiplexer for clock input of CPU cluster.
8 "intermediate" - A parent of "cpu" clock which is used as "intermediate" clock
11 Please refer to Documentation/devicetree/bindings/clock/clock-bindings.txt for
13 - operating-points-v2: Please refer to Documentation/devicetree/bindings/opp/opp.txt
15 - proc-supply: Regulator for Vproc of CPU cluster.
18 - sram-supply: Regulator for Vsram of CPU cluster. When present, the cpufreq driver
23 - #cooling-cells:
30 compatible = "operating-points-v2";
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/Documentation/devicetree/bindings/
Dnuma.txt6 1 - Introduction
18 2 - numa-node-id
23 a node id is a 32-bit integer.
26 numa-node-id property which contains the node id of the device.
29 /* numa node 0 */
30 numa-node-id = <0>;
33 numa-node-id = <1>;
36 3 - distance-map
39 The optional device tree node distance-map describes the relative
42 - compatible : Should at least contain "numa-distance-map-v1".
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/Documentation/devicetree/bindings/opp/
Dsun50i-nvmem-cpufreq.txt7 speedbin blown in the efuse combination. The sun50i-cpufreq-nvmem driver
12 --------------------
14 - operating-points-v2: Phandle to the operating-points-v2 table to use.
16 In 'operating-points-v2' table:
17 - compatible: Should be
18 - 'allwinner,sun50i-h6-operating-points'.
19 - nvmem-cells: A phandle pointing to a nvmem-cells node representing the
22 pair. Please refer the for nvmem-cells bindings
27 - opp-microvolt-<name>: Voltage in micro Volts.
29 matching opp-microvolt-<name> property.
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Dqcom-nvmem-cpufreq.txt8 defines the voltage and frequency value based on the msm-id in SMEM
10 The qcom-cpufreq-nvmem driver reads the msm-id and efuse value from the SoC
13 operating-points-v2 table when it is parsed by the OPP framework.
16 --------------------
18 - operating-points-v2: Phandle to the operating-points-v2 table to use.
20 In 'operating-points-v2' table:
21 - compatible: Should be
22 - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
25 --------------------
27 - power-domains: A phandle pointing to the PM domain specifier which provides
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/Documentation/translations/zh_CN/arm64/
Dbooting.txt12 ---------------------------------------------------------------------
26 ---------------------------------------------------------------------
36 AArch64 异常模型由多个异常级（EL0 - EL3）组成，对于 EL0 和 EL1 异常级
54 -----------------
65 ---------------
77 -------------
87 -------------
98 u64 res2 = 0; /* 保留 */
99 u64 res3 = 0; /* 保留 */
100 u64 res4 = 0; /* 保留 */
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/Documentation/arm64/
Dbooting.rst13 (EL0 - EL3), with EL0 and EL1 having a secure and a non-secure
14 counterpart. EL2 is the hypervisor level and exists only in non-secure
33 ---------------------------
46 -------------------------
50 The device tree blob (dtb) must be placed on an 8-byte boundary and must
59 ------------------------------
71 ------------------------
75 The decompressed kernel image contains a 64-byte header as follows::
82 u64 res2 = 0; /* reserved */
83 u64 res3 = 0; /* reserved */
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Dacpi_object_usage.rst16 - Required: DSDT, FADT, GTDT, MADT, MCFG, RSDP, SPCR, XSDT
18 - Recommended: BERT, EINJ, ERST, HEST, PCCT, SSDT
20 - Optional: BGRT, CPEP, CSRT, DBG2, DRTM, ECDT, FACS, FPDT, IORT,
24 - Not supported: BOOT, DBGP, DMAR, ETDT, HPET, IBFT, IVRS, LPIT,
47 Optional, not currently supported, with no real use-case for an
55 time as ARM-compatible hardware is available, and the specification
123 UEFI-based; if it is UEFI-based, this table may be supplied. When this
139 the hardware reduced profile, and only 64-bit address fields will
155 If PSCI is used (as is recommended), make sure that ARM_BOOT_ARCH is
156 filled in properly - that the PSCI_COMPLIANT flag is set and that
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/Documentation/virt/kvm/
Dapi.txt1 The Definitive KVM (Kernel-based Virtual Machine) API Documentation
5 ----------------------
10 - System ioctls: These query and set global attributes which affect the
14 - VM ioctls: These query and set attributes that affect an entire virtual
21 - vcpu ioctls: These query and set attributes that control the operation
29 - device ioctls: These query and set attributes that control the operation
36 -------------------
73 -------------
77 facility that allows backward-compatible extensions to the API to be
87 ------------------
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