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Searched refs:SCLK_MUX_SEL_MASK (Results 1 – 17 of 17) sorted by relevance

/drivers/gpu/drm/radeon/
Drv740d.h36 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
Drv730d.h39 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
Drv740_dpm.c151 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in rv740_populate_sclk_value()
370 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in rv740_populate_smc_acpi_state()
Drv730_dpm.c83 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in rv730_populate_sclk_value()
293 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in rv730_populate_smc_acpi_state()
Drv770d.h102 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
Dnid.h549 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
Dsid.h96 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
Dcikd.h259 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
Drv770_dpm.c530 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in rv770_populate_sclk_value()
978 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in rv770_populate_smc_acpi_state()
Drv770.c1146 tmp &= SCLK_MUX_SEL_MASK; in rv770_set_clk_bypass_mode()
Devergreend.h84 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
Dni_dpm.c1902 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in ni_populate_smc_acpi_state()
2033 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in ni_calculate_sclk_params()
Dcypress_dpm.c1431 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in cypress_populate_smc_acpi_state()
Dsi_dpm.c4576 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in si_populate_smc_acpi_state()
4816 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in si_calculate_sclk_params()
Dci_dpm.c3025 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in ci_populate_smc_acpi_level()
/drivers/gpu/drm/amd/amdgpu/
Dsid.h98 #define SCLK_MUX_SEL_MASK (0x1ff << 0) macro
Dsi_dpm.c5039 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in si_populate_smc_acpi_state()
5278 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; in si_calculate_sclk_params()