Searched refs:SD_VPCLK0_CTL (Results 1 – 7 of 7) sorted by relevance
| /drivers/staging/rts5208/ |
| D | rtsx_card.c | 672 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, in switch_ssc_clock()
674 rtsx_add_cmd(chip, WRITE_REG_CMD, SD_VPCLK0_CTL, in switch_ssc_clock()
782 retval = rtsx_write_register(chip, SD_VPCLK0_CTL, in switch_normal_clock()
801 retval = rtsx_write_register(chip, SD_VPCLK0_CTL, in switch_normal_clock()
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| D | rtsx_card.h | 787 #define SD_VPCLK0_CTL 0xFC2A macro
791 #define SD_VPTX_CTL SD_VPCLK0_CTL
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| D | sd.c | 845 retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
849 retval = rtsx_write_register(chip, SD_VPCLK0_CTL,
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| /drivers/misc/cardreader/ |
| D | rtsx_usb.c | 460 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_VPCLK0_CTL, in rtsx_usb_switch_clock()
462 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_VPCLK0_CTL, in rtsx_usb_switch_clock()
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| D | rtsx_pcr.c | 813 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, in rtsx_pci_switch_clock()
815 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_VPCLK0_CTL, in rtsx_pci_switch_clock()
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| /drivers/mmc/host/ |
| D | rtsx_usb_sdmmc.c | 592 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_VPCLK0_CTL, in sd_change_phase()
598 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); in sd_change_phase()
599 rtsx_usb_add_cmd(ucr, WRITE_REG_CMD, SD_VPCLK0_CTL, in sd_change_phase()
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| D | rtsx_pci_sdmmc.c | 620 rtsx_pci_write_register(pcr, SD_VPCLK0_CTL, PHASE_NOT_RESET, 0); in sd_change_phase()
621 rtsx_pci_write_register(pcr, SD_VPCLK0_CTL, PHASE_NOT_RESET, in sd_change_phase()
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