| /drivers/misc/cxl/ |
| D | fault.c | 105 ctx->fault_addr = ctx->dar; in cxl_ack_ae()
131 int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar) in cxl_handle_mm_fault() argument
153 if ((result = copro_handle_mm_fault(mm, dar, dsisr, &flt))) { in cxl_handle_mm_fault()
167 if (!mm && (get_region_id(dar) != USER_REGION_ID)) in cxl_handle_mm_fault()
174 hash_page_mm(mm, dar, access, 0x300, inv_flags); in cxl_handle_mm_fault()
182 u64 dsisr, u64 dar) in cxl_handle_page_fault() argument
184 trace_cxl_pte_miss(ctx, dsisr, dar); in cxl_handle_page_fault()
186 if (cxl_handle_mm_fault(mm, dsisr, dar)) { in cxl_handle_page_fault()
233 u64 dar = ctx->dar; in cxl_handle_fault() local
238 cxl_p2n_read(ctx->afu, CXL_PSL_DAR_An) != dar || in cxl_handle_fault()
[all …]
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| D | irq.c | 25 static irqreturn_t schedule_cxl_fault(struct cxl_context *ctx, u64 dsisr, u64 dar) in schedule_cxl_fault() argument
28 ctx->dar = dar; in schedule_cxl_fault()
35 u64 dsisr, dar; in cxl_irq_psl9() local
38 dar = irq_info->dar; in cxl_irq_psl9()
40 trace_cxl_psl9_irq(ctx, irq, dsisr, dar); in cxl_irq_psl9()
42 pr_devel("CXL interrupt %i for afu pe: %i DSISR: %#llx DAR: %#llx\n", irq, ctx->pe, dsisr, dar); in cxl_irq_psl9()
46 return schedule_cxl_fault(ctx, dsisr, dar); in cxl_irq_psl9()
86 u64 dsisr, dar; in cxl_irq_psl8() local
89 dar = irq_info->dar; in cxl_irq_psl8()
91 trace_cxl_psl_irq(ctx, irq, dsisr, dar); in cxl_irq_psl8()
[all …]
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| D | trace.h | 163 TP_PROTO(struct cxl_context *ctx, int irq, u64 dsisr, u64 dar),
165 TP_ARGS(ctx, irq, dsisr, dar),
173 __field(u64, dar)
182 __entry->dar = dar;
192 __entry->dar
197 TP_PROTO(struct cxl_context *ctx, int irq, u64 dsisr, u64 dar),
199 TP_ARGS(ctx, irq, dsisr, dar),
207 __field(u64, dar)
216 __entry->dar = dar;
225 __entry->dar
[all …]
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| D | cxllib.c | 228 u64 dar, vma_start, vma_end; in cxllib_handle_fault() local
244 for (dar = (addr & ~(page_size - 1)); dar < (addr + size); in cxllib_handle_fault()
245 dar += page_size) { in cxllib_handle_fault()
246 if (dar < vma_start || dar >= vma_end) { in cxllib_handle_fault()
261 rc = get_vma_info(mm, dar, &vma_start, &vma_end, in cxllib_handle_fault()
267 rc = cxl_handle_mm_fault(mm, flags, dar); in cxllib_handle_fault()
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| D | native.c | 134 u64 dsisr, dar; in cxl_psl_purge() local
181 dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); in cxl_psl_purge()
183 dsisr, dar); in cxl_psl_purge()
1093 info->dar = cxl_p2n_read(afu, CXL_PSL_DAR_An); in native_get_irq_info()
1210 irq_info.dar); in native_irq_multiplexed()
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| D | cxl.h | 586 u64 dar; member
970 int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar);
998 u64 dar; member
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| D | hcalls.c | 413 info->dsisr, info->dar, info->dsr, info->reserved, in cxl_h_collect_int_info()
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| /drivers/misc/ocxl/ |
| D | trace.h | 71 TP_PROTO(void *spa, u64 pe, u64 dsisr, u64 dar, u64 tfc),
72 TP_ARGS(spa, pe, dsisr, dar, tfc),
78 __field(u64, dar)
86 __entry->dar = dar;
94 __entry->dar,
100 TP_PROTO(void *spa, u64 pe, u64 dsisr, u64 dar, u64 tfc),
101 TP_ARGS(spa, pe, dsisr, dar, tfc)
105 TP_PROTO(void *spa, u64 pe, u64 dsisr, u64 dar, u64 tfc),
106 TP_ARGS(spa, pe, dsisr, dar, tfc)
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| D | link.c | 66 u64 dar; member
99 static void read_irq(struct spa *spa, u64 *dsisr, u64 *dar, u64 *pe) in read_irq() argument
104 *dar = in_be64(spa->reg_dar); in read_irq()
123 spa->xsl_fault.dsisr, spa->xsl_fault.dar, reg); in ack_irq()
143 rc = copro_handle_mm_fault(fault->pe_data.mm, fault->dar, fault->dsisr, in xsl_fault_handler_bh()
150 fault->dar, fault->dsisr); in xsl_fault_handler_bh()
166 if (get_region_id(fault->dar) != USER_REGION_ID) in xsl_fault_handler_bh()
170 hash_page_mm(fault->pe_data.mm, fault->dar, access, 0x300, in xsl_fault_handler_bh()
184 u64 dsisr, dar, pe_handle; in xsl_fault_handler() local
190 read_irq(spa, &dsisr, &dar, &pe_handle); in xsl_fault_handler()
[all …]
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| /drivers/dma/ |
| D | idma64.c | 234 u64 sar, dar; in idma64_hw_desc_fill() local
241 dar = config->dst_addr; in idma64_hw_desc_fill()
248 dar = hw->phys; in idma64_hw_desc_fill()
252 dst_width = __ffs(dar | hw->len | 4); in idma64_hw_desc_fill()
256 lli->dar = dar; in idma64_hw_desc_fill()
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| D | idma64.h | 98 u64 dar; member
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| D | fsldma.h | 112 u64 dar; /* 0x18 - Destination Address Register */ member
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| /drivers/dma/sh/ |
| D | shdma.h | 46 u32 dar; /* DAR / destination address */ member
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| D | shdmac.c | 218 sh_dmae_writel(sh_chan, hw->dar, DAR); in dmae_set_reg()
291 sh_desc->hw.tcr, sh_desc->hw.sar, sh_desc->hw.dar); in sh_dmae_start_xfer()
388 sh_desc->hw.dar = dst; in sh_dmae_desc_setup()
464 (sh_desc->hw.dar + sh_desc->hw.tcr) == dar_buf) || in sh_dmae_desc_completed()
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| D | rcar-dmac.c | 50 u32 dar; member
735 hwdesc->dar = chunk->dst_addr; in rcar_dmac_fill_hwdesc()
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| /drivers/staging/comedi/drivers/ |
| D | mite.h | 26 u32 dar; member
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| /drivers/dma/dw-edma/ |
| D | dw-edma-core.h | 47 u64 dar; member
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| D | dw-edma-v0-core.c | 219 SET_LL(&lli[i].dar_low, lower_32_bits(child->dar)); in dw_edma_v0_core_write_chunk()
220 SET_LL(&lli[i].dar_high, upper_32_bits(child->dar)); in dw_edma_v0_core_write_chunk()
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| D | dw-edma-core.c | 392 burst->dar = xfer->xfer.cyclic.paddr; in dw_edma_device_transfer()
394 burst->dar = sg_dma_address(sg); in dw_edma_device_transfer()
405 burst->dar = dst_addr; in dw_edma_device_transfer()
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| /drivers/dma/dw/ |
| D | core.c | 169 channel_writel(dwc, DAR, lli_read(desc, dar)); in dwc_do_single_block()
422 lli_read(desc, dar), in dwc_dump_lli()
591 lli_write(desc, dar, dest + offset); in dwc_prep_dma_memcpy()
681 lli_write(desc, dar, reg); in dwc_prep_slave_sg()
729 lli_write(desc, dar, mem); in dwc_prep_slave_sg()
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| D | regs.h | 370 __le32 dar; member
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| /drivers/dma/dw-axi-dmac/ |
| D | dw-axi-dmac.h | 69 __le64 dar; member
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| D | dw-axi-dmac-platform.c | 397 desc->lli.dar = cpu_to_le64(adr); in write_desc_dar()
526 le64_to_cpu(desc->lli.dar), in axi_chan_dump_lli()
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