| /drivers/clk/ |
| D | clk-vt8500.c | 456 int div1, div2; in wm8750_find_pll_bits() local
462 for (div1 = 1; div1 >= 0; div1--) in wm8750_find_pll_bits()
465 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2)); in wm8750_find_pll_bits()
471 *filter = wm8750_get_filter(parent_rate, div1); in wm8750_find_pll_bits()
473 *divisor1 = div1; in wm8750_find_pll_bits()
481 *divisor1 = div1; in wm8750_find_pll_bits()
504 int div1, div2; in wm8850_find_pll_bits() local
510 for (div1 = 1; div1 >= 0; div1--) in wm8850_find_pll_bits()
514 ((div1 + 1) * (1 << div2)); in wm8850_find_pll_bits()
521 *divisor1 = div1; in wm8850_find_pll_bits()
[all …]
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| /drivers/clk/uniphier/ |
| D | clk-uniphier.h | 110 #define UNIPHIER_CLK_DIV2(parent, div0, div1) \ argument
112 UNIPHIER_CLK_DIV(parent, div1)
114 #define UNIPHIER_CLK_DIV3(parent, div0, div1, div2) \ argument
115 UNIPHIER_CLK_DIV2(parent, div0, div1), \
118 #define UNIPHIER_CLK_DIV4(parent, div0, div1, div2, div3) \ argument
119 UNIPHIER_CLK_DIV2(parent, div0, div1), \
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| /drivers/clk/imx/ |
| D | clk-composite-8m.c | 52 int div1, div2; in imx8m_clk_composite_compute_dividers() local
59 for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) { in imx8m_clk_composite_compute_dividers()
61 int new_error = ((parent_rate / div1) / div2) - rate; in imx8m_clk_composite_compute_dividers()
64 *prediv = div1; in imx8m_clk_composite_compute_dividers()
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| /drivers/clk/samsung/ |
| D | clk-cpu.c | 155 unsigned long div0, div1 = 0, mux_reg; in exynos_cpuclk_pre_rate_change() local
174 div1 = cfg_data->div1; in exynos_cpuclk_pre_rate_change()
176 div1 = readl(base + E4210_DIV_CPU1) & in exynos_cpuclk_pre_rate_change()
216 writel(div1, base + E4210_DIV_CPU1); in exynos_cpuclk_pre_rate_change()
283 unsigned long div0, div1 = 0, mux_reg; in exynos5433_cpuclk_pre_rate_change() local
300 div1 = cfg_data->div1; in exynos5433_cpuclk_pre_rate_change()
329 writel(div1, base + E5433_DIV_CPU1); in exynos5433_cpuclk_pre_rate_change()
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| D | clk-cpu.h | 28 unsigned long div1; member
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| /drivers/spi/ |
| D | spi-omap-uwire.c | 317 int div1; in uwire_setup_transfer() local
362 div1 = 2; in uwire_setup_transfer()
365 div1 = 4; in uwire_setup_transfer()
368 div1 = 7; in uwire_setup_transfer()
372 div1 = 10; in uwire_setup_transfer()
375 div2 = (rate / div1 + hz - 1) / hz; in uwire_setup_transfer()
392 rate /= div1; in uwire_setup_transfer()
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| /drivers/media/tuners/ |
| D | mt2131.c | 89 u32 div1, num1, div2, num2; in mt2131_set_params() local
106 div1 = num1 / 8192; in mt2131_set_params()
137 b[3] = div1; in mt2131_set_params()
146 (int)div1, (int)num1, (int)div2, (int)num2); in mt2131_set_params()
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| D | mt2060.c | 196 u32 div1,num1,div2,num2; in mt2060_set_params() local
228 div1 = num1 / 64; in mt2060_set_params()
249 b[2] = div1; in mt2060_set_params()
256 dprintk("PLL div1=%d num1=%d div2=%d num2=%d",(int)div1,(int)num1,(int)div2,(int)num2); in mt2060_set_params()
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| /drivers/gpu/drm/nouveau/nvkm/engine/disp/ |
| D | sorgf119.c | 124 u32 div1 = sor->asy.link == 3; in gf119_sor_clock() local
132 nvkm_mask(device, 0x612300 + soff, 0x00000707, (div2 << 8) | div1); in gf119_sor_clock()
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| /drivers/i2c/busses/ |
| D | i2c-s3c2410.c | 799 unsigned int *div1, unsigned int *divs) in s3c24xx_i2c_calcdivisor() argument
818 *div1 = calc_div1; in s3c24xx_i2c_calcdivisor()
832 unsigned int divs, div1; in s3c24xx_i2c_clockrate() local
846 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs); in s3c24xx_i2c_clockrate()
861 if (div1 == 512) in s3c24xx_i2c_clockrate()
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| D | i2c-sprd.c | 334 u32 div1 = I2C_ADDR_DVD1_CALC(high, low); in sprd_i2c_set_clk() local
337 writel(div1, i2c_dev->base + ADDR_DVD1); in sprd_i2c_set_clk()
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| /drivers/media/dvb-frontends/ |
| D | stb0899_algo.c | 1274 int div1, div2, rem1, rem2; in stb0899_dvbs2_get_srate() local
1276 div1 = config->btr_nco_bits / 2; in stb0899_dvbs2_get_srate()
1277 div2 = config->btr_nco_bits - div1 - 1; in stb0899_dvbs2_get_srate()
1285 intval1 = internal->master_clk / (1 << div1); in stb0899_dvbs2_get_srate()
1288 rem1 = internal->master_clk % (1 << div1); in stb0899_dvbs2_get_srate()
1291 srate = (intval1 * intval2) + ((intval1 * rem2) / (1 << div2)) + ((intval2 * rem1) / (1 << div1)); in stb0899_dvbs2_get_srate()
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| /drivers/staging/comedi/drivers/ |
| D | adl_pci9118.c | 533 unsigned int *div1, unsigned int *div2, in pci9118_calc_divisors() argument
539 *div1 = *tim2 / pacer->osc_base; /* convert timer (burst) */ in pci9118_calc_divisors()
541 *div2 = *div2 / *div1; /* major timer is c1*c2 */ in pci9118_calc_divisors()
545 *tim2 = *div1 * pacer->osc_base; /* real convert timer */ in pci9118_calc_divisors()
553 *tim1 = *div1 * *div2 * pacer->osc_base; in pci9118_calc_divisors()
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| /drivers/gpu/drm/i915/display/ |
| D | intel_ddi.c | 1411 u32 m1, m2_int, m2_frac, div1, div2, ref_clock; in icl_calc_mg_pll_link() local
1425 div1 = 2; in icl_calc_mg_pll_link()
1428 div1 = 3; in icl_calc_mg_pll_link()
1431 div1 = 5; in icl_calc_mg_pll_link()
1434 div1 = 7; in icl_calc_mg_pll_link()
1455 tmp = div_u64(tmp, 5 * div1 * div2); in icl_calc_mg_pll_link()
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| D | intel_dpll_mgr.c | 2636 int div1 = div1_vals[i]; in icl_mg_pll_find_divisors() local
2639 int dco = div1 * div2 * clock_khz * 5; in icl_mg_pll_find_divisors()
2655 switch (div1) { in icl_mg_pll_find_divisors()
2657 MISSING_CASE(div1); in icl_mg_pll_find_divisors()
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