| /drivers/staging/media/omap4iss/ |
| D | iss_csiphy.c | 36 reg |= (phy->lanes.data[i].pol ? in csiphy_lanes_config()
38 reg |= (phy->lanes.data[i].pos << in csiphy_lanes_config()
44 reg |= phy->lanes.clk.pol ? CSI2_COMPLEXIO_CFG_CLOCK_POL : 0; in csiphy_lanes_config()
45 reg |= phy->lanes.clk.pos << CSI2_COMPLEXIO_CFG_CLOCK_POSITION_SHIFT; in csiphy_lanes_config()
123 struct iss_csiphy_lanes_cfg *lanes; in omap4iss_csiphy_config() local
128 lanes = &subdevs->bus.csi2.lanecfg; in omap4iss_csiphy_config()
175 if (lanes->data[i].pos == 0) in omap4iss_csiphy_config()
178 if (lanes->data[i].pol > 1 || in omap4iss_csiphy_config()
179 lanes->data[i].pos > (csi2->phy->max_data_lanes + 1)) in omap4iss_csiphy_config()
182 if (used_lanes & (1 << lanes->data[i].pos)) in omap4iss_csiphy_config()
[all …]
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| /drivers/media/platform/omap3isp/ |
| D | ispcsiphy.c | 166 struct isp_csiphy_lanes_cfg *lanes; in omap3isp_csiphy_config() local
174 lanes = &buscfg->bus.ccp2.lanecfg; in omap3isp_csiphy_config()
177 lanes = &buscfg->bus.csi2.lanecfg; in omap3isp_csiphy_config()
186 if (lanes->data[i].pol > 1 || lanes->data[i].pos > 3) in omap3isp_csiphy_config()
189 if (used_lanes & (1 << lanes->data[i].pos)) in omap3isp_csiphy_config()
192 used_lanes |= 1 << lanes->data[i].pos; in omap3isp_csiphy_config()
195 if (lanes->clk.pol > 1 || lanes->clk.pos > 3) in omap3isp_csiphy_config()
198 if (lanes->clk.pos == 0 || used_lanes & (1 << lanes->clk.pos)) in omap3isp_csiphy_config()
244 reg |= (lanes->data[i].pol << in omap3isp_csiphy_config()
246 reg |= (lanes->data[i].pos << in omap3isp_csiphy_config()
[all …]
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| /drivers/gpu/drm/bridge/adv7511/ |
| D | adv7533.c | 43 clock_div_by_lanes[dsi->lanes - 2] << 3); in adv7511_dsi_config_timing_gen()
74 regmap_write(adv->regmap_cec, 0x1c, dsi->lanes << 4); in adv7533_dsi_power_on()
106 int lanes, ret; in adv7533_mode_set() local
112 lanes = 4; in adv7533_mode_set()
114 lanes = 3; in adv7533_mode_set()
116 if (lanes != dsi->lanes) { in adv7533_mode_set()
118 dsi->lanes = lanes; in adv7533_mode_set()
165 dsi->lanes = adv->num_dsi_lanes; in adv7533_attach_dsi()
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| /drivers/net/ethernet/netronome/nfp/ |
| D | nfp_devlink.c | 40 nfp_devlink_set_lanes(struct nfp_pf *pf, unsigned int idx, unsigned int lanes) in nfp_devlink_set_lanes() argument
49 ret = __nfp_eth_set_split(nsp, lanes); in nfp_devlink_set_lanes()
70 unsigned int lanes; in nfp_devlink_port_split() local
90 lanes = eth_port.port_lanes / count; in nfp_devlink_port_split()
91 if (eth_port.lanes == 10 && count == 2) in nfp_devlink_port_split()
92 lanes = 8 / count; in nfp_devlink_port_split()
94 ret = nfp_devlink_set_lanes(pf, eth_port.index, lanes); in nfp_devlink_port_split()
107 unsigned int lanes; in nfp_devlink_port_unsplit() local
124 lanes = eth_port.port_lanes; in nfp_devlink_port_unsplit()
126 lanes = 10; in nfp_devlink_port_unsplit()
[all …]
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| /drivers/video/fbdev/omap2/omapfb/dss/ |
| D | hdmi_common.c | 20 u32 lanes[8]; in hdmi_parse_lanes_of() local
22 if (len / sizeof(u32) != ARRAY_SIZE(lanes)) { in hdmi_parse_lanes_of()
27 r = of_property_read_u32_array(ep, "lanes", lanes, in hdmi_parse_lanes_of()
28 ARRAY_SIZE(lanes)); in hdmi_parse_lanes_of()
34 r = hdmi_phy_parse_lanes(phy, lanes); in hdmi_parse_lanes_of()
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| D | hdmi_phy.c | 41 int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes) in hdmi_phy_parse_lanes() argument
49 dx = lanes[i]; in hdmi_phy_parse_lanes()
50 dy = lanes[i + 1]; in hdmi_phy_parse_lanes()
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| /drivers/gpu/drm/omapdrm/dss/ |
| D | hdmi_common.c | 20 u32 lanes[8]; in hdmi_parse_lanes_of() local
22 if (len / sizeof(u32) != ARRAY_SIZE(lanes)) { in hdmi_parse_lanes_of()
27 r = of_property_read_u32_array(ep, "lanes", lanes, in hdmi_parse_lanes_of()
28 ARRAY_SIZE(lanes)); in hdmi_parse_lanes_of()
34 r = hdmi_phy_parse_lanes(phy, lanes); in hdmi_parse_lanes_of()
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| D | hdmi_phy.c | 32 int hdmi_phy_parse_lanes(struct hdmi_phy_data *phy, const u32 *lanes) in hdmi_phy_parse_lanes() argument
40 dx = lanes[i]; in hdmi_phy_parse_lanes()
41 dy = lanes[i + 1]; in hdmi_phy_parse_lanes()
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| /drivers/nubus/ |
| D | proc.c | 73 int lanes = board->lanes; in nubus_proc_add_rsrc_dir() local
78 return proc_mkdir_data(name, 0555, procdir, (void *)lanes); in nubus_proc_add_rsrc_dir()
120 int lanes = (int)proc_get_parent_data(inode); in nubus_proc_rsrc_show() local
123 if (!lanes) in nubus_proc_rsrc_show()
126 ent.mask = lanes; in nubus_proc_rsrc_show()
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| /drivers/phy/tegra/ |
| D | xusb.c | 35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
91 struct device_node *np, *lanes; in tegra_xusb_pad_find_phy_node() local
93 lanes = of_get_child_by_name(pad->dev.of_node, "lanes"); in tegra_xusb_pad_find_phy_node()
94 if (!lanes) in tegra_xusb_pad_find_phy_node()
97 np = of_get_child_by_name(lanes, pad->soc->lanes[index].name); in tegra_xusb_pad_find_phy_node()
98 of_node_put(lanes); in tegra_xusb_pad_find_phy_node()
187 pad->lanes = devm_kcalloc(&pad->dev, pad->soc->num_lanes, sizeof(lane), in tegra_xusb_pad_register()
189 if (!pad->lanes) { in tegra_xusb_pad_register()
[all …]
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| /drivers/gpu/drm/rockchip/ |
| D | cdn-dp-core.c | 147 u8 lanes; in cdn_dp_get_port_lanes() local
154 lanes = 2; in cdn_dp_get_port_lanes()
156 lanes = 4; in cdn_dp_get_port_lanes()
158 lanes = 0; in cdn_dp_get_port_lanes()
161 return lanes; in cdn_dp_get_port_lanes()
181 int i, lanes; in cdn_dp_connected_port() local
185 lanes = cdn_dp_get_port_lanes(port); in cdn_dp_connected_port()
186 if (lanes) in cdn_dp_connected_port()
283 u8 lanes, bpc; in cdn_dp_connector_mode_valid() local
303 source_max = dp->lanes; in cdn_dp_connector_mode_valid()
[all …]
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| D | cdn-dp-core.h | 59 u8 lanes; member
98 u8 lanes; member
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| /drivers/gpu/drm/hisilicon/kirin/kirin/ |
| D | dw_drm_dsi.c | 245 u32 lanes) in dsi_set_phy_timer() argument
252 val = (lanes - 1) | (PHY_STOP_WAIT_TIME << 8); in dsi_set_phy_timer()
278 u32 lanes) in dsi_set_mipi_phy() argument
285 dsi_set_phy_timer(base, phy, lanes); in dsi_set_mipi_phy()
309 for (i = 0; i < lanes; i++) { in dsi_set_mipi_phy()
462 dphy_req_kHz = mode->clock * bpp / dsi->lanes; in dsi_mipi_init()
469 dsi_set_mipi_phy(base, phy, dsi->lanes); in dsi_mipi_init()
481 dsi->lanes, mode->clock, phy->lane_byte_clk_kHz); in dsi_mipi_init()
513 req_kHz = mode->clock * bpp / dsi->lanes; in dsi_encoder_phy_mode_valid()
525 if (mode->clock/dsi->lanes == lane_byte_clk_kHz/3) { in dsi_encoder_phy_mode_valid()
[all …]
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| /drivers/gpu/drm/vc4/ |
| D | vc4_dsi.c | 514 u32 lanes; member
680 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) | in vc4_dsi_ulps()
681 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) | in vc4_dsi_ulps()
682 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0)); in vc4_dsi_ulps()
685 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) | in vc4_dsi_ulps()
686 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) | in vc4_dsi_ulps()
687 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0)); in vc4_dsi_ulps()
690 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) | in vc4_dsi_ulps()
691 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) | in vc4_dsi_ulps()
692 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0)); in vc4_dsi_ulps()
[all …]
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| /drivers/phy/ |
| D | phy-core-mipi-dphy.c | 24 unsigned int lanes, in phy_mipi_dphy_get_default_config() argument
34 do_div(hs_clk_rate, lanes); in phy_mipi_dphy_get_default_config()
76 cfg->lanes = lanes; in phy_mipi_dphy_get_default_config()
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| /drivers/gpu/drm/bridge/synopsys/ |
| D | dw-mipi-dsi.c | 235 u32 lanes; member
302 if (device->lanes > dsi->plat_data->max_data_lanes) { in dw_mipi_dsi_host_attach()
304 device->lanes); in dw_mipi_dsi_host_attach()
308 dsi->lanes = device->lanes; in dw_mipi_dsi_host_attach()
754 N_LANES(dsi->lanes)); in dw_mipi_dsi_dphy_interface_config()
834 return dsi->master->lanes + dsi->lanes; in dw_mipi_dsi_get_lanes()
838 return dsi->lanes + dsi->slave->lanes; in dw_mipi_dsi_get_lanes()
841 return dsi->lanes; in dw_mipi_dsi_get_lanes()
850 u32 lanes = dw_mipi_dsi_get_lanes(dsi); in dw_mipi_dsi_mode_set() local
855 lanes, dsi->format, &dsi->lane_mbps); in dw_mipi_dsi_mode_set()
[all …]
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| /drivers/pci/controller/ |
| D | pcie-rockchip.c | 58 rockchip->lanes = 1; in rockchip_pcie_parse_dt()
59 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes); in rockchip_pcie_parse_dt()
60 if (!err && (rockchip->lanes == 0 || in rockchip_pcie_parse_dt()
61 rockchip->lanes == 3 || in rockchip_pcie_parse_dt()
62 rockchip->lanes > 4)) { in rockchip_pcie_parse_dt()
64 rockchip->lanes = 1; in rockchip_pcie_parse_dt()
241 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes); in rockchip_pcie_init_port()
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| /drivers/gpu/drm/tegra/ |
| D | dsi.c | 39 unsigned int lanes; member
70 unsigned int lanes; member
478 return dsi->master->lanes + dsi->lanes; in tegra_dsi_get_lanes()
481 return dsi->lanes + dsi->slave->lanes; in tegra_dsi_get_lanes()
483 return dsi->lanes; in tegra_dsi_get_lanes()
516 DSI_CONTROL_LANES(dsi->lanes - 1) | in tegra_dsi_configure()
600 unsigned int lanes = state->lanes; in tegra_dsi_configure() local
604 delay = DIV_ROUND_UP(delay * mul, div * lanes); in tegra_dsi_configure()
608 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); in tegra_dsi_configure()
609 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes); in tegra_dsi_configure()
[all …]
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| /drivers/gpu/drm/hisilicon/kirin/kirin960/ |
| D | dw_drm_dsi.c | 205 dsi->client[id].lanes = 4; in get_dsi_phy_ctrl()
207 dsi->client[id].lanes = 3; in get_dsi_phy_ctrl()
211 dphy_req_kHz = mode->clock * bpp / dsi->client[id].lanes; in get_dsi_phy_ctrl()
541 u32 lanes; in dsi_mipi_init() local
561 lanes = dsi->client[id].lanes - 1; in dsi_mipi_init()
564 set_reg(mipi_dsi_base + MIPIDSI_PHY_IF_CFG_OFFSET, lanes, 2, 0); in dsi_mipi_init()
620 for (i = 0; i <= lanes; i++) { in dsi_mipi_init()
670 if (lanes >= DSI_4_LANES) in dsi_mipi_init()
672 else if (lanes >= DSI_3_LANES) in dsi_mipi_init()
674 else if (lanes >= DSI_2_LANES) in dsi_mipi_init()
[all …]
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| /drivers/media/platform/rcar-vin/ |
| D | rcar-csi2.c | 372 unsigned short lanes; member
417 const u32 lane_mask = (1 << priv->lanes) - 1; in rcsi2_wait_phy_start()
474 do_div(mbps, priv->lanes * 1000000); in rcsi2_calc_mbps()
525 phycnt |= (1 << priv->lanes) - 1; in rcsi2_start_receiver()
790 priv->lanes = vep->bus.mipi_csi2.num_data_lanes; in rcsi2_parse_v4l2()
791 if (priv->lanes != 1 && priv->lanes != 2 && priv->lanes != 4) { in rcsi2_parse_v4l2()
793 priv->lanes); in rcsi2_parse_v4l2()
798 priv->lane_swap[i] = i < priv->lanes ? in rcsi2_parse_v4l2()
1192 dev_info(priv->dev, "%d lanes found\n", priv->lanes); in rcsi2_probe()
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| /drivers/gpu/drm/panel/ |
| D | panel-innolux-p079zca.c | 43 unsigned int lanes; member
251 .lanes = 4,
400 .lanes = 4,
517 dsi->lanes = desc->lanes; in innolux_panel_probe()
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| D | panel-sitronix-st7701.c | 93 unsigned int lanes; member
325 .lanes = 2,
346 dsi->lanes = desc->lanes; in st7701_dsi_probe()
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| /drivers/media/platform/cadence/ |
| D | cdns-csi2rx.c | 73 u8 lanes[CSI2RX_LANES_MAX]; member
120 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, csi2rx->lanes[i]); in csi2rx_start()
121 set_bit(csi2rx->lanes[i], &lanes_used); in csi2rx_start()
388 memcpy(csi2rx->lanes, v4l2_ep.bus.mipi_csi2.data_lanes, in csi2rx_parse_dt()
389 sizeof(csi2rx->lanes)); in csi2rx_parse_dt()
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| /drivers/net/ethernet/netronome/nfp/nfpcore/ |
| D | nfp_nsp_eth.c | 139 dst->lanes = FIELD_GET(NSP_ETH_PORT_LANES, port); in nfp_eth_port_translate()
146 dst->speed = dst->lanes * rate; in nfp_eth_port_translate()
187 table->ports[i].port_lanes += table->ports[j].lanes; in nfp_eth_calc_port_geometry()
605 int __nfp_eth_set_split(struct nfp_nsp *nsp, unsigned int lanes) in __nfp_eth_set_split() argument
608 lanes, NSP_ETH_CTRL_SET_LANES); in __nfp_eth_set_split()
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| /drivers/gpu/drm/gma500/ |
| D | intel_bios.c | 89 switch (edp_link_params->lanes) { in parse_edp()
91 dev_priv->edp.lanes = 1; in parse_edp()
94 dev_priv->edp.lanes = 2; in parse_edp()
98 dev_priv->edp.lanes = 4; in parse_edp()
102 dev_priv->edp.lanes, dev_priv->edp.rate, dev_priv->edp.bpp); in parse_edp()
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