| /drivers/video/fbdev/via/ |
| D | via_clock.h | 47 static inline u32 get_pll_internal_frequency(u32 ref_freq, in get_pll_internal_frequency() argument
50 return ref_freq / pll.divisor * pll.multiplier; in get_pll_internal_frequency()
53 static inline u32 get_pll_output_frequency(u32 ref_freq, in get_pll_output_frequency() argument
56 return get_pll_internal_frequency(ref_freq, pll) >> pll.rshift; in get_pll_output_frequency()
|
| /drivers/net/wireless/ti/wl1251/ |
| D | boot.c | 60 u32 scr_pad6, init_data, tmp, elp_cmd, ref_freq; in wl1251_boot_init_seq() local
88 ref_freq = scr_pad6 & 0x000000FF; in wl1251_boot_init_seq()
89 wl1251_debug(DEBUG_BOOT, "ref_freq 0x%x", ref_freq); in wl1251_boot_init_seq()
143 tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000; in wl1251_boot_init_seq()
149 tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER]; in wl1251_boot_init_seq()
160 tmp = (LUT[ref_freq][LUT_PARAM_ATTN_BB] << 16) | in wl1251_boot_init_seq()
161 (LUT[ref_freq][LUT_PARAM_ALPHA_BB] << 12) | 0x1; in wl1251_boot_init_seq()
168 tmp = LUT[ref_freq][LUT_PARAM_STOP_TIME_BB] | 0x000A0000; in wl1251_boot_init_seq()
176 tmp = LUT[ref_freq][LUT_PARAM_BB_PLL_LOOP_FILTER] | 0x00000030; in wl1251_boot_init_seq()
|
| /drivers/clk/ |
| D | clk-highbank.c | 110 static void clk_pll_calc(unsigned long rate, unsigned long ref_freq, in clk_pll_calc() argument
127 divf = (vco_freq + (ref_freq / 2)) / ref_freq; in clk_pll_calc()
138 unsigned long ref_freq = *parent_rate; in clk_pll_round_rate() local
140 clk_pll_calc(rate, ref_freq, &divq, &divf); in clk_pll_round_rate()
142 return (ref_freq * (divf + 1)) / (1 << divq); in clk_pll_round_rate()
|
| /drivers/video/fbdev/matrox/ |
| D | matroxfb_misc.c | 133 unsigned int fxtal = pll->ref_freq; in matroxfb_PLL_calcclock()
143 printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq); in matroxfb_PLL_calcclock()
547 minfo->features.pll.ref_freq = 14318; in parse_pins1()
557 minfo->features.pll.ref_freq = 14318; in default_pins1()
571 minfo->features.pll.ref_freq = 14318; in parse_pins2()
582 minfo->features.pll.ref_freq = 14318; in default_pins2()
599 minfo->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000; in parse_pins3()
612 minfo->features.pll.ref_freq = 27000; in default_pins3()
630 minfo->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000; in parse_pins4()
644 minfo->features.pll.ref_freq = 27000; in default_pins4()
[all …]
|
| D | g450_pll.c | 35 return (minfo->features.pll.ref_freq * n + (m >> 1)) / m; in g450_mnp2vco()
99 n = ((tvco * (m+1) + minfo->features.pll.ref_freq) / (minfo->features.pll.ref_freq * 2)) - 2; in g450_nextpll()
|
| D | matroxfb_maven.c | 200 unsigned int ref_freq; member
215 .ref_freq = 540000,
220 .ref_freq = 450450, /* 27027000/60 == 27000000/59.94005994 */
230 unsigned int fxtal = ctl->ref_freq; in matroxfb_PLL_mavenclock()
|
| D | matroxfb_DAC1064.c | 181 } else if (minfo->crtc2.pixclock == minfo->features.pll.ref_freq) { in g450_set_plls()
590 minfo->features.pll.ref_freq = 14318; in MGA1064_ramdac_init()
858 if (!minfo->features.pll.ref_freq) { in MGAG100_preinit()
859 minfo->features.pll.ref_freq = 27000; in MGAG100_preinit()
|
| D | matroxfb_base.h | 222 unsigned int ref_freq; member
|
| D | matroxfb_Ti3026.c | 547 minfo->features.pll.ref_freq = 114545; in ti3026_ramdac_init()
|
| /drivers/media/dvb-frontends/ |
| D | stv6111.c | 35 u32 ref_freq; member
393 state->ref_freq = 16000; in init_state()
469 div = fvco / state->ref_freq; in set_lof()
470 frac = fvco % state->ref_freq; in set_lof()
471 frac = muldiv32(frac, 0x40000, state->ref_freq); in set_lof()
|
| /drivers/clk/bcm/ |
| D | clk-iproc-pll.c | 142 static int get_kp(unsigned long ref_freq, enum kp_band kp_index) in get_kp() argument
146 if (ref_freq < ref_freq_table[0][0]) in get_kp()
150 if (ref_freq >= ref_freq_table[i][0] && in get_kp()
151 ref_freq < ref_freq_table[i][1]) in get_kp()
324 unsigned long ref_freq; in pll_set_rate() local
332 ref_freq = parent_rate * 2; in pll_set_rate()
334 ref_freq = parent_rate / vco->pdiv; in pll_set_rate()
352 kp = get_kp(ref_freq, kp_index); in pll_set_rate()
|
| /drivers/video/fbdev/ |
| D | smscufx.c | 505 static u32 ufx_calc_range(u32 ref_freq) in ufx_calc_range() argument
507 if (ref_freq >= 88000000) in ufx_calc_range()
510 if (ref_freq >= 54000000) in ufx_calc_range()
513 if (ref_freq >= 34000000) in ufx_calc_range()
516 if (ref_freq >= 21000000) in ufx_calc_range()
519 if (ref_freq >= 13000000) in ufx_calc_range()
522 if (ref_freq >= 8000000) in ufx_calc_range()
|
| /drivers/gpu/drm/msm/dsi/pll/ |
| D | dsi_pll_10nm.c | 62 u32 ref_freq; member
136 config->ref_freq = pll->vco_ref_clk_rate; in dsi_pll_setup_config()
214 ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) / 2 - 1; in dsi_pll_calc_ssc()
|
| /drivers/video/fbdev/aty/ |
| D | atyfb.h | 61 u16 ref_freq; member
|
| D | atyfb_base.c | 3366 pll_block.ref_freq, pll_block.ref_divider); in init_from_bios()
3373 par->pll_limits.ref_clk = pll_block.ref_freq/100; in init_from_bios()
|
| /drivers/gpu/drm/radeon/ |
| D | radeon_uvd.c | 969 unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq; in radeon_uvd_calc_upll_dividers() local
981 do_div(fb_div, ref_freq); in radeon_uvd_calc_upll_dividers()
|
| D | radeon_legacy_crtc.c | 266 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, in radeon_compute_pll_gain() argument
274 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; in radeon_compute_pll_gain()
|
| D | rv6xx_dpm.c | 533 static inline u32 rv6xx_calculate_spread_spectrum_clk_v(u32 vco_freq, u32 ref_freq, in rv6xx_calculate_spread_spectrum_clk_v() argument
537 u32 fb_divider = vco_freq / ref_freq; in rv6xx_calculate_spread_spectrum_clk_v()
543 static inline u32 rv6xx_calculate_spread_spectrum_clk_s(u32 ss_rate, u32 ref_freq) in rv6xx_calculate_spread_spectrum_clk_s() argument
545 return (((ref_freq * 10) / (ss_rate * 2)) - 1) / 4; in rv6xx_calculate_spread_spectrum_clk_s()
|
| /drivers/gpu/drm/i915/display/ |
| D | intel_display.h | 431 const char *name, u32 reg, int ref_freq);
|
| D | intel_dpll_mgr.c | 2210 u32 dco_freq, u32 ref_freq, in cnl_wrpll_params_populate() argument
2251 dco = div_u64((u64)dco_freq << 15, ref_freq); in cnl_wrpll_params_populate()
|
| D | intel_display.c | 173 const char *name, u32 reg, int ref_freq) in vlv_get_cck_clock() argument
185 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); in vlv_get_cck_clock()
|