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Searched refs:src_offset (Results 1 – 25 of 52) sorted by relevance

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/drivers/misc/mic/scif/
Dscif_dma.c56 s64 src_offset; member
888 offset = work->src_offset; in scif_rma_list_dma_copy_unaligned()
1099 s64 src_offset = work->src_offset, dst_offset = work->dst_offset; in _scif_rma_list_dma_copy_aligned() local
1114 if (src_offset == end_src_offset) { in _scif_rma_list_dma_copy_aligned()
1128 src_dma_addr = scif_off_to_dma_addr(src_window, src_offset, in _scif_rma_list_dma_copy_aligned()
1156 src_offset += (loop_len - 1); in _scif_rma_list_dma_copy_aligned()
1189 src_offset += loop_len; in _scif_rma_list_dma_copy_aligned()
1219 s64 src_offset = work->src_offset, dst_offset = work->dst_offset; in scif_rma_list_dma_copy_aligned() local
1229 src_cache_off = src_offset & (L1_CACHE_BYTES - 1); in scif_rma_list_dma_copy_aligned()
1234 src_dma_addr = __scif_off_to_dma_addr(src_window, src_offset); in scif_rma_list_dma_copy_aligned()
[all …]
Dscif_rma.h397 static inline bool scif_unaligned(off_t src_offset, off_t dst_offset) in scif_unaligned() argument
399 src_offset = src_offset & (L1_CACHE_BYTES - 1); in scif_unaligned()
401 return !(src_offset == dst_offset); in scif_unaligned()
/drivers/gpu/drm/radeon/
Drv770_dma.c43 uint64_t src_offset, uint64_t dst_offset, in rv770_copy_dma() argument
76 radeon_ring_write(ring, src_offset & 0xfffffffc); in rv770_copy_dma()
78 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in rv770_copy_dma()
79 src_offset += cur_size_in_dw * 4; in rv770_copy_dma()
Devergreen_dma.c108 uint64_t src_offset, in evergreen_copy_dma() argument
142 radeon_ring_write(ring, src_offset & 0xfffffffc); in evergreen_copy_dma()
144 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in evergreen_copy_dma()
145 src_offset += cur_size_in_dw * 4; in evergreen_copy_dma()
Devergreen_cs.c2804 u64 src_offset, dst_offset, dst2_offset; in evergreen_dma_cs_parse() local
2869 src_offset = radeon_get_ib_value(p, idx+2); in evergreen_dma_cs_parse()
2870 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in evergreen_dma_cs_parse()
2873 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
2875 src_offset + (count * 4), radeon_bo_size(src_reloc->robj)); in evergreen_dma_cs_parse()
2894 src_offset = radeon_get_ib_value(p, idx+1); in evergreen_dma_cs_parse()
2895 src_offset <<= 8; in evergreen_dma_cs_parse()
2904 src_offset = radeon_get_ib_value(p, idx+7); in evergreen_dma_cs_parse()
2905 src_offset |= ((u64)(radeon_get_ib_value(p, idx+8) & 0xff)) << 32; in evergreen_dma_cs_parse()
2913 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in evergreen_dma_cs_parse()
[all …]
Dsi_dma.c232 uint64_t src_offset, uint64_t dst_offset, in si_copy_dma() argument
265 radeon_ring_write(ring, lower_32_bits(src_offset)); in si_copy_dma()
267 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in si_copy_dma()
268 src_offset += cur_size_in_bytes; in si_copy_dma()
Dr600_dma.c445 uint64_t src_offset, uint64_t dst_offset, in r600_copy_dma() argument
478 radeon_ring_write(ring, src_offset & 0xfffffffc); in r600_copy_dma()
480 (upper_32_bits(src_offset) & 0xff))); in r600_copy_dma()
481 src_offset += cur_size_in_dw * 4; in r600_copy_dma()
Dradeon_asic.h86 uint64_t src_offset,
157 uint64_t src_offset,
348 uint64_t src_offset, uint64_t dst_offset,
352 uint64_t src_offset, uint64_t dst_offset,
474 uint64_t src_offset, uint64_t dst_offset,
548 uint64_t src_offset, uint64_t dst_offset,
726 uint64_t src_offset, uint64_t dst_offset,
797 uint64_t src_offset, uint64_t dst_offset,
801 uint64_t src_offset, uint64_t dst_offset,
Dr200.c84 uint64_t src_offset, in r200_copy_dma() argument
114 radeon_ring_write(ring, src_offset); in r200_copy_dma()
117 src_offset += cur_size; in r200_copy_dma()
Dcik_sdma.c580 uint64_t src_offset, uint64_t dst_offset, in cik_copy_dma() argument
614 radeon_ring_write(ring, lower_32_bits(src_offset)); in cik_copy_dma()
615 radeon_ring_write(ring, upper_32_bits(src_offset)); in cik_copy_dma()
618 src_offset += cur_size_in_bytes; in cik_copy_dma()
Dr600_cs.c2385 u64 src_offset, dst_offset; in r600_dma_cs_parse() local
2443 src_offset = radeon_get_ib_value(p, idx+1); in r600_dma_cs_parse()
2444 src_offset <<= 8; in r600_dma_cs_parse()
2453 src_offset = radeon_get_ib_value(p, idx+5); in r600_dma_cs_parse()
2454 src_offset |= ((u64)(radeon_get_ib_value(p, idx+6) & 0xff)) << 32; in r600_dma_cs_parse()
2465 src_offset = radeon_get_ib_value(p, idx+2); in r600_dma_cs_parse()
2466 src_offset |= ((u64)(radeon_get_ib_value(p, idx+4) & 0xff)) << 32; in r600_dma_cs_parse()
2476 src_offset = radeon_get_ib_value(p, idx+2); in r600_dma_cs_parse()
2477 src_offset |= ((u64)(radeon_get_ib_value(p, idx+3) & 0xff)) << 32; in r600_dma_cs_parse()
2488 if ((src_offset + (count * 4)) > radeon_bo_size(src_reloc->robj)) { in r600_dma_cs_parse()
[all …]
/drivers/gpu/drm/vc4/
Dvc4_validate.c487 uint32_t src_offset = 0; in vc4_validate_bin_cl() local
489 while (src_offset < len) { in vc4_validate_bin_cl()
491 void *src_pkt = unvalidated + src_offset; in vc4_validate_bin_cl()
497 src_offset, cmd); in vc4_validate_bin_cl()
504 src_offset, cmd); in vc4_validate_bin_cl()
508 if (src_offset + info->len > len) { in vc4_validate_bin_cl()
511 src_offset, cmd, info->name, info->len, in vc4_validate_bin_cl()
512 src_offset + len); in vc4_validate_bin_cl()
523 src_offset, cmd, info->name); in vc4_validate_bin_cl()
527 src_offset += info->len; in vc4_validate_bin_cl()
[all …]
/drivers/gpu/drm/i915/gem/
Di915_gem_object_blt.c206 u64 src_offset, dst_offset; in intel_emit_vma_copy_blt() local
232 src_offset = src->node.start; in intel_emit_vma_copy_blt()
248 *cmd++ = lower_32_bits(src_offset); in intel_emit_vma_copy_blt()
249 *cmd++ = upper_32_bits(src_offset); in intel_emit_vma_copy_blt()
259 *cmd++ = lower_32_bits(src_offset); in intel_emit_vma_copy_blt()
260 *cmd++ = upper_32_bits(src_offset); in intel_emit_vma_copy_blt()
267 *cmd++ = src_offset; in intel_emit_vma_copy_blt()
273 src_offset += size; in intel_emit_vma_copy_blt()
/drivers/gpu/drm/vmwgfx/
Dvmwgfx_blit.c358 u32 src_offset, in vmw_bo_cpu_blit_line() argument
366 u32 src_page = src_offset >> PAGE_SHIFT; in vmw_bo_cpu_blit_line()
368 u32 src_page_offset = src_offset & ~PAGE_MASK; in vmw_bo_cpu_blit_line()
416 src_offset += copy_size; in vmw_bo_cpu_blit_line()
448 u32 src_offset, u32 src_stride, in vmw_bo_cpu_blit() argument
493 ret = vmw_bo_cpu_blit_line(&d, dst_offset, src_offset, w); in vmw_bo_cpu_blit()
498 src_offset += src_stride; in vmw_bo_cpu_blit()
/drivers/gpu/drm/vkms/
Dvkms_composer.c23 int i, j, src_offset; in compute_crc() local
32 src_offset = composer->offset in compute_crc()
36 memset(vaddr_out + src_offset + 24, 0, 8); in compute_crc()
37 crc = crc32_le(crc, vaddr_out + src_offset, in compute_crc()
/drivers/gpu/drm/nouveau/
Dnouveau_bo.c787 u64 src_offset = mem->vma[0].addr; in nvc0_bo_move_copy() local
801 OUT_RING (chan, upper_32_bits(src_offset)); in nvc0_bo_move_copy()
802 OUT_RING (chan, lower_32_bits(src_offset)); in nvc0_bo_move_copy()
813 src_offset += (PAGE_SIZE * line_count); in nvc0_bo_move_copy()
825 u64 src_offset = mem->vma[0].addr; in nvc0_bo_move_m2mf() local
842 OUT_RING (chan, upper_32_bits(src_offset)); in nvc0_bo_move_m2mf()
843 OUT_RING (chan, lower_32_bits(src_offset)); in nvc0_bo_move_m2mf()
852 src_offset += (PAGE_SIZE * line_count); in nvc0_bo_move_m2mf()
864 u64 src_offset = mem->vma[0].addr; in nva3_bo_move_copy() local
878 OUT_RING (chan, upper_32_bits(src_offset)); in nva3_bo_move_copy()
[all …]
/drivers/gpu/drm/qxl/
Dqxl_ioctl.c79 int src_offset; member
95 info->src_offset); in apply_reloc()
245 reloc_info[i].src_offset = reloc.src_offset; in qxl_process_single_command()
248 reloc_info[i].src_offset = 0; in qxl_process_single_command()
/drivers/clk/sirf/
Dclk-atlas7.c222 u16 src_offset; /* dto src offset */ member
491 reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; in dto_clk_is_enabled()
501 reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; in dto_clk_enable()
513 reg = clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_ENA - SIRFSOC_CLKC_AUDIO_DTO_SRC; in dto_clk_disable()
525 …u32 droff = clkc_readl(clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC… in dto_clk_recalc_rate()
556 clkc_writel(0, clk->src_offset + SIRFSOC_CLKC_AUDIO_DTO_DROFF - SIRFSOC_CLKC_AUDIO_DTO_SRC); in dto_clk_set_rate()
566 return clkc_readl(clk->src_offset); in dto_clk_get_parent()
576 clkc_writel(index, clk->src_offset); in dto_clk_set_parent()
607 .src_offset = SIRFSOC_CLKC_AUDIO_DTO_SRC,
628 .src_offset = SIRFSOC_CLKC_DISP0_DTO_SRC,
[all …]
/drivers/net/wireless/broadcom/brcm80211/brcmfmac/
Dbcmsdh.c383 unsigned int max_req_sz, src_offset, dst_offset; in brcmf_sdiod_sglist_rw() local
483 src_offset = 0; in brcmf_sdiod_sglist_rw()
492 if (req_sz > src->len - src_offset) in brcmf_sdiod_sglist_rw()
493 req_sz = src->len - src_offset; in brcmf_sdiod_sglist_rw()
495 orig_data = src->data + src_offset; in brcmf_sdiod_sglist_rw()
499 src_offset += req_sz; in brcmf_sdiod_sglist_rw()
500 if (src_offset == src->len) { in brcmf_sdiod_sglist_rw()
501 src_offset = 0; in brcmf_sdiod_sglist_rw()
/drivers/crypto/ccp/
Dccp-dmaengine.c367 unsigned int src_offset, src_len; in ccp_create_desc() local
386 src_offset = 0; in ccp_create_desc()
402 src_offset = 0; in ccp_create_desc()
434 ccp_pt->src_dma = sg_dma_address(src_sg) + src_offset; in ccp_create_desc()
451 src_offset += len; in ccp_create_desc()
/drivers/net/ethernet/mellanox/mlxsw/
Dspectrum_acl_ctcam.c29 u16 src_offset, u16 dst_offset, u16 size) in mlxsw_sp_acl_ctcam_region_move() argument
34 region->tcam_region_info, src_offset, in mlxsw_sp_acl_ctcam_region_move()
/drivers/video/fbdev/
Dfb-puv3.c137 int src_offset = src_y0 * src_pitch + src_x0 * (m_iBpp / 8); in unifb_prim_fillrect() local
164 writel(src_offset, UGE_SRCSTART); in unifb_prim_fillrect()
227 int src_offset = src_y0 * src_pitch + src_x0 * (m_iBpp / 8); in unifb_prim_copyarea() local
247 src_offset = (src_y0 + aheight) * src_pitch + in unifb_prim_copyarea()
269 writel(src_offset, UGE_SRCSTART); in unifb_prim_copyarea()
/drivers/net/ethernet/intel/i40e/
Di40e_ethtool.c3587 rule->flex_offset == entry->src_offset) { in i40e_prune_flex_pit_list()
3613 rule->flex_offset == entry->src_offset) { in i40e_prune_flex_pit_list()
3701 u16 src_offset) in i40e_find_flex_offset() argument
3711 if (entry->src_offset == src_offset) in i40e_find_flex_offset()
3740 u16 src_offset, in i40e_add_flex_offset() argument
3749 new_pit->src_offset = src_offset; in i40e_add_flex_offset()
3756 if (new_pit->src_offset < entry->src_offset) { in i40e_add_flex_offset()
3765 if (new_pit->src_offset == entry->src_offset) { in i40e_add_flex_offset()
3834 u16 offset = entry->src_offset + j; in __i40e_reprogram_flex_pit()
3853 entry->src_offset)); in __i40e_reprogram_flex_pit()
[all …]
/drivers/gpu/drm/gma500/
Daccel_2d.c160 uint32_t src_offset, uint32_t src_stride, in psb_accel_2d_copy() argument
203 *buf++ = src_offset; in psb_accel_2d_copy()
/drivers/gpu/drm/amd/amdgpu/
Damdgpu_sdma.h78 uint64_t src_offset,

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