Lines Matching refs:operations

865 	  The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
876 	  erratum. For very specific sequences of memory operations, it is
904 	  between two write operations may not ensure the correct visibility
933 	  corrects this value, ensuring cache maintenance operations which use
937 	bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
942 	  broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1035 	  On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1159 	bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1163 	  operations that do not specify an address execute, relative to
1355 	  management operations described in ARM document number ARM DEN
1646 	  such copy operations with large buffers.
2018 	  Note that gcc does not generate 80-bit operations by default,