Lines Matching refs:r6
272 ldr r6, =(_end) @ Cover whole kernel
273 sub r6, r6, r5 @ Minimum size of region to map
274 clz r6, r6 @ Region size must be 2^N...
275 rsb r6, r6, #31 @ ...so round up region size
276 lsl r6, r6, #PMSAv7_RSR_SZ @ Put size in right field
277 orr r6, r6, #(1 << PMSAv7_RSR_EN) @ Set region enabled bit
294 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ PHYS_OFFSET, shared, enabled
296 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ PHYS_OFFSET, shared, enabled
305 mov r6, #PMSAv7_RSR_ALL_MEM @ 4GB region, enabled
307 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ 0x0, BG region, enabled
309 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE r12 @ 0x0, BG region, enabled
319 ldr r6, =(_exiprom) @ ROM end
320 sub r6, r6, r0 @ Minimum size of region to map
321 clz r6, r6 @ Region size must be 2^N...
322 rsb r6, r6, #31 @ ...so round up region size
323 lsl r6, r6, #PMSAv7_RSR_SZ @ Put size in right field
324 orr r6, r6, #(1 << PMSAv7_RSR_EN) @ Set region enabled bit
326 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled
328 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled
342 ldr r6, =(_exiprom) @ ROM end
343 sub r6, r6, #1
344 bic r6, r6, #(PMSAv8_MINALIGN - 1)
347 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN)
350 AR_CLASS(mcr p15, 0, r6, c6, c8, 1) @ PRLAR0
352 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(0)])
356 ldr r6, =KERNEL_END
357 sub r6, r6, #1
358 bic r6, r6, #(PMSAv8_MINALIGN - 1)
361 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN)
364 AR_CLASS(mcr p15, 0, r6, c6, c8, 5) @ PRLAR1
366 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(1)])
370 ldr r6, =KERNEL_START
372 cmp r6, r5
373 movcs r6, r5
375 ldr r6, =KERNEL_START
377 cmp r6, #0
381 sub r6, r6, #1
382 bic r6, r6, #(PMSAv8_MINALIGN - 1)
385 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN)
388 AR_CLASS(mcr p15, 0, r6, c6, c9, 1) @ PRLAR2
390 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(2)])
396 ldr r6, =(_exiprom)
397 cmp r5, r6
398 movcc r5, r6
402 mov r6, #0xffffffff
403 bic r6, r6, #(PMSAv8_MINALIGN - 1)
406 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN)
409 AR_CLASS(mcr p15, 0, r6, c6, c9, 5) @ PRLAR3
411 M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(3)])
416 ldr r6, =KERNEL_END
417 cmp r5, r6
418 movcs r5, r6
420 ldr r6, =KERNEL_START
422 cmp r6, r0
423 movcc r6, r0
425 sub r6, r6, #1
426 bic r6, r6, #(PMSAv8_MINALIGN - 1)
429 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN)
438 str r6, [r12, #PMSAv8_RLAR_A(0)]
441 mcr p15, 0, r6, c6, c10, 1 @ PRLAR4
455 ldr r6, [r7] @ get secondary_data.mpu_rgn_info
477 ldr r4, [r6, #MPU_RNG_INFO_USED]
479 add r3, r6, #MPU_RNG_INFO_RNGS
491 ldr r6, [r3, #MPU_RGN_DRSR]
494 setup_region r0, r5, r6, PMSAv7_DATA_SIDE
496 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE
507 ldr r4, [r6, #MPU_RNG_INFO_USED]
512 add r3, r6, #MPU_RNG_INFO_RNGS
523 ldr r6, [r3, #MPU_RGN_PRLAR]
526 mcr p15, 0, r6, c6, c3, 1 @ PRLAR