Lines Matching refs:sp
72 W(add) sp, sp, #1 /* Reset 7 */
73 W(add) sp, sp, #1 /* Undef 6 */
74 W(add) sp, sp, #1 /* Syscall 5 */
75 W(add) sp, sp, #1 /* Prefetch abort 4 */
76 W(add) sp, sp, #1 /* Data abort 3 */
77 W(add) sp, sp, #1 /* HVC 2 */
78 W(add) sp, sp, #1 /* IRQ 1 */
94 W(add) sp, sp, #1 /* Reset 7 */
95 W(add) sp, sp, #1 /* Undef 6 */
96 W(add) sp, sp, #1 /* Syscall 5 */
97 W(add) sp, sp, #1 /* Prefetch abort 4 */
98 W(add) sp, sp, #1 /* Data abort 3 */
99 W(add) sp, sp, #1 /* HVC 2 */
100 W(add) sp, sp, #1 /* IRQ 1 */
116 mov r0, sp
118 sub sp, sp, r0
127 ARM( eor sp, sp, #\val )
128 ARM( tst sp, #7 )
129 ARM( eorne sp, sp, #\val )
248 ldr r0, [sp] @ Guest's r0