41 	writel(1 << ((d->irq - ar7_irq_base) % 32),  in ar7_unmask_irq()
47 	writel(1 << ((d->irq - ar7_irq_base) % 32),  in ar7_mask_irq()
53 	writel(1 << ((d->irq - ar7_irq_base) % 32),  in ar7_ack_irq()
59 	writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET));  in ar7_unmask_sec_irq()
64 	writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET));  in ar7_mask_sec_irq()
69 	writel(1 << (d->irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET));  in ar7_ack_sec_irq()
98 	writel(0xffffffff, REG(ECR_OFFSET(0)));  in ar7_irq_init()
99 	writel(0xff, REG(ECR_OFFSET(32)));  in ar7_irq_init()
100 	writel(0xffffffff, REG(SEC_ECR_OFFSET));  in ar7_irq_init()
101 	writel(0xffffffff, REG(CR_OFFSET(0)));  in ar7_irq_init()
102 	writel(0xff, REG(CR_OFFSET(32)));  in ar7_irq_init()
103 	writel(0xffffffff, REG(SEC_CR_OFFSET));  in ar7_irq_init()
108 		writel(i, REG(CHNL_OFFSET(i)));  in ar7_irq_init()
143 	writel(1, REG(CR_OFFSET(irq)));  in ar7_cascade()