Lines Matching refs:wp
109 u32 wp[2]; member
200 vc.wp[0] = current->thread.evr[fc]; in do_spe_mathemu()
201 vc.wp[1] = regs->gpr[fc]; in do_spe_mathemu()
202 va.wp[0] = current->thread.evr[fa]; in do_spe_mathemu()
203 va.wp[1] = regs->gpr[fa]; in do_spe_mathemu()
204 vb.wp[0] = current->thread.evr[fb]; in do_spe_mathemu()
205 vb.wp[1] = regs->gpr[fb]; in do_spe_mathemu()
210 pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]); in do_spe_mathemu()
211 pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]); in do_spe_mathemu()
212 pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]); in do_spe_mathemu()
221 FP_UNPACK_SP(SA, va.wp + 1); in do_spe_mathemu()
223 FP_UNPACK_SP(SB, vb.wp + 1); in do_spe_mathemu()
226 FP_UNPACK_SP(SA, va.wp + 1); in do_spe_mathemu()
235 vc.wp[1] = va.wp[1] & ~SIGN_BIT_S; in do_spe_mathemu()
239 vc.wp[1] = va.wp[1] | SIGN_BIT_S; in do_spe_mathemu()
243 vc.wp[1] = va.wp[1] ^ SIGN_BIT_S; in do_spe_mathemu()
277 vc.wp[1] = 0; in do_spe_mathemu()
281 FP_TO_INT_ROUND_S(vc.wp[1], SB, 32, in do_spe_mathemu()
301 vc.wp[1] = 0; in do_spe_mathemu()
304 FP_TO_INT_ROUND_S(vc.wp[1], SB, 32, in do_spe_mathemu()
312 vc.wp[1] = 0; in do_spe_mathemu()
315 FP_TO_INT_S(vc.wp[1], SB, 32, in do_spe_mathemu()
328 FP_PACK_SP(vc.wp + 1, SR); in do_spe_mathemu()
407 vc.wp[1] = 0; in do_spe_mathemu()
411 FP_TO_INT_ROUND_D(vc.wp[1], DB, 32, in do_spe_mathemu()
419 FP_UNPACK_SP(SB, vb.wp + 1); in do_spe_mathemu()
442 vc.wp[1] = 0; in do_spe_mathemu()
445 FP_TO_INT_ROUND_D(vc.wp[1], DB, 32, in do_spe_mathemu()
453 vc.wp[1] = 0; in do_spe_mathemu()
456 FP_TO_INT_D(vc.wp[1], DB, 32, in do_spe_mathemu()
494 FP_UNPACK_SP(SA0, va.wp); in do_spe_mathemu()
495 FP_UNPACK_SP(SA1, va.wp + 1); in do_spe_mathemu()
497 FP_UNPACK_SP(SB0, vb.wp); in do_spe_mathemu()
498 FP_UNPACK_SP(SB1, vb.wp + 1); in do_spe_mathemu()
501 FP_UNPACK_SP(SA0, va.wp); in do_spe_mathemu()
502 FP_UNPACK_SP(SA1, va.wp + 1); in do_spe_mathemu()
517 vc.wp[0] = va.wp[0] & ~SIGN_BIT_S; in do_spe_mathemu()
518 vc.wp[1] = va.wp[1] & ~SIGN_BIT_S; in do_spe_mathemu()
522 vc.wp[0] = va.wp[0] | SIGN_BIT_S; in do_spe_mathemu()
523 vc.wp[1] = va.wp[1] | SIGN_BIT_S; in do_spe_mathemu()
527 vc.wp[0] = va.wp[0] ^ SIGN_BIT_S; in do_spe_mathemu()
528 vc.wp[1] = va.wp[1] ^ SIGN_BIT_S; in do_spe_mathemu()
566 vc.wp[0] = 0; in do_spe_mathemu()
570 FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32, in do_spe_mathemu()
574 vc.wp[1] = 0; in do_spe_mathemu()
578 FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32, in do_spe_mathemu()
586 vc.wp[0] = 0; in do_spe_mathemu()
589 FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32, in do_spe_mathemu()
593 vc.wp[1] = 0; in do_spe_mathemu()
596 FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32, in do_spe_mathemu()
604 vc.wp[0] = 0; in do_spe_mathemu()
607 FP_TO_INT_S(vc.wp[0], SB0, 32, in do_spe_mathemu()
611 vc.wp[1] = 0; in do_spe_mathemu()
614 FP_TO_INT_S(vc.wp[1], SB1, 32, in do_spe_mathemu()
630 FP_PACK_SP(vc.wp, SR0); in do_spe_mathemu()
631 FP_PACK_SP(vc.wp + 1, SR1); in do_spe_mathemu()
682 current->thread.evr[fc] = vc.wp[0]; in do_spe_mathemu()
683 regs->gpr[fc] = vc.wp[1]; in do_spe_mathemu()
688 pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]); in do_spe_mathemu()
689 pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]); in do_spe_mathemu()
690 pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]); in do_spe_mathemu()
754 fgpr.wp[0] = current->thread.evr[fc]; in speround_handler()
755 fgpr.wp[1] = regs->gpr[fc]; in speround_handler()
788 if (fgpr.wp[1] == 0) in speround_handler()
796 if (fgpr.wp[1] == 0) in speround_handler()
798 if (fgpr.wp[0] == 0) in speround_handler()
807 if (fgpr.wp[1] == 0) in speround_handler()
816 pr_debug("round fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]); in speround_handler()
825 if (!s_lo) fgpr.wp[1]++; /* Z > 0, choose Z1 */ in speround_handler()
829 fgpr.wp[1]++; /* Z < 0, choose Z2 */ in speround_handler()
831 fgpr.wp[1]--; /* Z < 0, choose Z2 */ in speround_handler()
842 fgpr.wp[1]++; /* Z > 0, choose Z1 */ in speround_handler()
849 fgpr.wp[1]--; /* Z < 0, choose Z2 */ in speround_handler()
857 fgpr.wp[1]++; /* Z_low > 0, choose Z1 */ in speround_handler()
859 fgpr.wp[0]++; /* Z_high word > 0, choose Z1 */ in speround_handler()
863 fgpr.wp[1]++; /* Z_low < 0, choose Z2 */ in speround_handler()
865 fgpr.wp[1]--; /* Z_low < 0, choose Z2 */ in speround_handler()
869 fgpr.wp[0]++; /* Z_high < 0, choose Z2 */ in speround_handler()
871 fgpr.wp[0]--; /* Z_high < 0, choose Z2 */ in speround_handler()
880 current->thread.evr[fc] = fgpr.wp[0]; in speround_handler()
881 regs->gpr[fc] = fgpr.wp[1]; in speround_handler()
883 pr_debug(" to fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]); in speround_handler()