100 	addr = __raw_readl(hose->reg_base + SH4_PCIALR);  in sh7780_pci_err_irq()
105 	status = __raw_readw(hose->reg_base + PCI_STATUS);  in sh7780_pci_err_irq()
113 			__raw_writew(cmd, hose->reg_base + PCI_STATUS);  in sh7780_pci_err_irq()
119 	status = __raw_readl(hose->reg_base + SH4_PCIAINT);  in sh7780_pci_err_irq()
127 	__raw_writel(cmd, hose->reg_base + SH4_PCIAINT);  in sh7780_pci_err_irq()
132 	status = __raw_readl(hose->reg_base + SH4_PCIINT);  in sh7780_pci_err_irq()
140 	__raw_writel(cmd, hose->reg_base + SH4_PCIINT);  in sh7780_pci_err_irq()
154 	__raw_writel(SH4_PCIINTM_SDIM, hose->reg_base + SH4_PCIINTM);  in sh7780_pci_serr_irq()
169 	__raw_writel(0, hose->reg_base + SH4_PCIAINT);  in sh7780_pci_setup_irqs()
177 		     PCI_STATUS_PARITY, hose->reg_base + PCI_STATUS);  in sh7780_pci_setup_irqs()
202 		     SH4_PCIAINT_WDPE, hose->reg_base + SH4_PCIAINTM);  in sh7780_pci_setup_irqs()
210 		     SH4_PCIINTM_MRDPEIM, hose->reg_base + SH4_PCIINTM);  in sh7780_pci_setup_irqs()
229 	tmp = __raw_readl(hose->reg_base + SH4_PCICR);  in sh7780_pci66_init()
231 	__raw_writel(tmp, hose->reg_base + SH4_PCICR);  in sh7780_pci66_init()
234 	tmp = __raw_readw(hose->reg_base + PCI_STATUS);  in sh7780_pci66_init()
236 	__raw_writew(tmp, hose->reg_base + PCI_STATUS);  in sh7780_pci66_init()
239 	tmp = __raw_readl(hose->reg_base + SH4_PCICR);  in sh7780_pci66_init()
241 	__raw_writel(tmp, hose->reg_base + SH4_PCICR);  in sh7780_pci66_init()
255 	chan->reg_base = 0xfe040000;  in sh7780_pci_init()
262 		     chan->reg_base + SH4_PCICR);  in sh7780_pci_init()
271 	id = __raw_readw(chan->reg_base + PCI_VENDOR_ID);  in sh7780_pci_init()
277 	id = __raw_readw(chan->reg_base + PCI_DEVICE_ID);  in sh7780_pci_init()
291 	       __raw_readb(chan->reg_base + PCI_REVISION_ID));  in sh7780_pci_init()
298 		     chan->reg_base + SH4_PCICR);  in sh7780_pci_init()
308 		__raw_writel(memphys + SZ_512M, chan->reg_base + SH4_PCILAR1);  in sh7780_pci_init()
310 			     chan->reg_base + SH4_PCILSR1);  in sh7780_pci_init()
316 		__raw_writel(0, chan->reg_base + SH4_PCILAR1);  in sh7780_pci_init()
317 		__raw_writel(0, chan->reg_base + SH4_PCILSR1);  in sh7780_pci_init()
324 	__raw_writel(memphys, chan->reg_base + SH4_PCILAR0);  in sh7780_pci_init()
326 		     chan->reg_base + SH4_PCILSR0);  in sh7780_pci_init()
338 	__raw_writel(0, chan->reg_base + SH7780_PCICSCR0);  in sh7780_pci_init()
339 	__raw_writel(0, chan->reg_base + SH7780_PCICSAR0);  in sh7780_pci_init()
340 	__raw_writel(0, chan->reg_base + SH7780_PCICSCR1);  in sh7780_pci_init()
341 	__raw_writel(0, chan->reg_base + SH7780_PCICSAR1);  in sh7780_pci_init()
369 			     chan->reg_base + SH7780_PCIMBMR(i - 1));  in sh7780_pci_init()
370 		__raw_writel(res->start, chan->reg_base + SH7780_PCIMBR(i - 1));  in sh7780_pci_init()
376 	__raw_writel(0, chan->reg_base + PCI_BASE_ADDRESS_0);  in sh7780_pci_init()
377 	__raw_writel(0, chan->reg_base + SH7780_PCIIOBR);  in sh7780_pci_init()
378 	__raw_writel(0, chan->reg_base + SH7780_PCIIOBMR);  in sh7780_pci_init()
382 		     PCI_COMMAND_MEMORY, chan->reg_base + PCI_COMMAND);  in sh7780_pci_init()
390 		     chan->reg_base + SH4_PCICR);  in sh7780_pci_init()
399 	       (__raw_readw(chan->reg_base + PCI_STATUS) & PCI_STATUS_66MHZ) ?  in sh7780_pci_init()