Lines Matching refs:r21
178 movi MMUIR_FIRST, r21
181 putcfg r21, 0, ZERO /* Clear MMUIR[n].PTEH.V */
182 addi r21, MMUIR_STEP, r21
183 bne r21, r22, tr1
187 movi MMUDR_FIRST, r21
190 putcfg r21, 0, ZERO /* Clear MMUDR[n].PTEH.V */
191 addi r21, MMUDR_STEP, r21
192 bne r21, r22, tr1
195 movi MMUIR_FIRST, r21
198 putcfg r21, 1, r22 /* Set MMUIR[0].PTEL */
201 putcfg r21, 0, r22 /* Set MMUIR[0].PTEH */
204 movi MMUDR_FIRST, r21
207 putcfg r21, 1, r22 /* Set MMUDR[0].PTEL */
210 putcfg r21, 0, r22 /* Set MMUDR[0].PTEH */
215 addi r21, MMUDR_STEP, r21
218 putcfg r21, 1, r22 /* PTEL first */
221 putcfg r21, 0, r22 /* PTEH last */
227 movi ICCR_BASE, r21
230 putcfg r21, ICCR_REG0, r22
231 putcfg r21, ICCR_REG1, r23
234 movi OCCR_BASE, r21
237 putcfg r21, OCCR_REG0, r22
238 putcfg r21, OCCR_REG1, r23
246 getcon SR, r21
248 or r21, r22, r21
249 putcon r21, SSR
289 getcon SR, r21
291 and r21, r22, r22
294 xor r21, r22, r21
295 shlri r21, 15, r21 /* Supposedly 0/1 */
296 st.q r31, 0 , r21 /* Set fpu_in_use */
298 movi 0, r21
299 st.q r31, 0 , r21 /* Set fpu_in_use */
301 or r21, ZERO, r31 /* Set FPU flag at last */