Lines Matching refs:config
213 u64 config; in nhmex_uncore_msr_disable_box() local
216 rdmsrl(msr, config); in nhmex_uncore_msr_disable_box()
217 config &= ~((1ULL << uncore_num_counters(box)) - 1); in nhmex_uncore_msr_disable_box()
220 config &= ~NHMEX_W_PMON_GLOBAL_FIXED_EN; in nhmex_uncore_msr_disable_box()
221 wrmsrl(msr, config); in nhmex_uncore_msr_disable_box()
228 u64 config; in nhmex_uncore_msr_enable_box() local
231 rdmsrl(msr, config); in nhmex_uncore_msr_enable_box()
232 config |= (1ULL << uncore_num_counters(box)) - 1; in nhmex_uncore_msr_enable_box()
235 config |= NHMEX_W_PMON_GLOBAL_FIXED_EN; in nhmex_uncore_msr_enable_box()
236 wrmsrl(msr, config); in nhmex_uncore_msr_enable_box()
252 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_uncore_msr_enable_event()
254 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_uncore_msr_enable_event()
357 ctr = (hwc->config & NHMEX_B_PMON_CTR_MASK) >> in nhmex_bbox_hw_config()
359 ev_sel = (hwc->config & NHMEX_B_PMON_CTL_EV_SEL_MASK) >> in nhmex_bbox_hw_config()
372 reg1->config = event->attr.config1; in nhmex_bbox_hw_config()
373 reg2->config = event->attr.config2; in nhmex_bbox_hw_config()
384 wrmsrl(reg1->reg, reg1->config); in nhmex_bbox_msr_enable_event()
385 wrmsrl(reg1->reg + 1, reg2->config); in nhmex_bbox_msr_enable_event()
388 (hwc->config & NHMEX_B_PMON_CTL_EV_SEL_MASK)); in nhmex_bbox_msr_enable_event()
448 if ((hwc->config & NHMEX_PMON_CTL_EV_SEL_MASK) != in nhmex_sbox_hw_config()
457 reg1->config = event->attr.config1; in nhmex_sbox_hw_config()
458 reg2->config = event->attr.config2; in nhmex_sbox_hw_config()
470 wrmsrl(reg1->reg + 1, reg1->config); in nhmex_sbox_msr_enable_event()
471 wrmsrl(reg1->reg + 2, reg2->config); in nhmex_sbox_msr_enable_event()
474 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT22); in nhmex_sbox_msr_enable_event()
553 static bool nhmex_mbox_get_shared_reg(struct intel_uncore_box *box, int idx, u64 config) in nhmex_mbox_get_shared_reg() argument
563 if (!atomic_read(&er->ref) || er->config == config) { in nhmex_mbox_get_shared_reg()
565 er->config = config; in nhmex_mbox_get_shared_reg()
597 if (!atomic_read(&er->ref) || !((er->config ^ config) & mask)) { in nhmex_mbox_get_shared_reg()
605 er->config &= ~mask; in nhmex_mbox_get_shared_reg()
606 er->config |= (config & mask); in nhmex_mbox_get_shared_reg()
634 u64 config = reg1->config; in nhmex_mbox_alter_er() local
639 config &= NHMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx); in nhmex_mbox_alter_er()
641 config &= WSMEX_M_PMON_ZDP_CTL_FVC_EVENT_MASK(idx); in nhmex_mbox_alter_er()
644 config <<= 3 * idx; in nhmex_mbox_alter_er()
647 config >>= 3 * idx; in nhmex_mbox_alter_er()
652 config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config; in nhmex_mbox_alter_er()
654 config |= WSMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config; in nhmex_mbox_alter_er()
655 config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config; in nhmex_mbox_alter_er()
659 hwc->config += idx << NHMEX_M_PMON_CTL_INC_SEL_SHIFT; in nhmex_mbox_alter_er()
661 hwc->config -= idx << NHMEX_M_PMON_CTL_INC_SEL_SHIFT; in nhmex_mbox_alter_er()
662 reg1->config = config; in nhmex_mbox_alter_er()
665 return config; in nhmex_mbox_alter_er()
674 u64 config1 = reg1->config; in nhmex_mbox_get_constraint()
695 !nhmex_mbox_get_shared_reg(box, reg2->idx, reg2->config)) in nhmex_mbox_get_constraint()
779 if (er->event != (event->hw.config & er->config_mask)) in nhmex_mbox_hw_config()
798 reg1->config = event->attr.config1; in nhmex_mbox_hw_config()
808 reg2->config = event->attr.config2; in nhmex_mbox_hw_config()
810 reg2->config = ~0ULL; in nhmex_mbox_hw_config()
823 u64 config; in nhmex_mbox_shared_reg_config() local
826 return box->shared_regs[idx].config; in nhmex_mbox_shared_reg_config()
830 config = er->config; in nhmex_mbox_shared_reg_config()
832 return config; in nhmex_mbox_shared_reg_config()
853 if (reg2->config != ~0ULL) { in nhmex_mbox_msr_enable_event()
855 reg2->config & NHMEX_M_PMON_ADDR_MATCH_MASK); in nhmex_mbox_msr_enable_event()
857 (reg2->config >> NHMEX_M_PMON_ADDR_MASK_SHIFT)); in nhmex_mbox_msr_enable_event()
862 wrmsrl(hwc->config_base, hwc->config | NHMEX_PMON_CTL_EN_BIT0); in nhmex_mbox_msr_enable_event()
952 hwc->config -= 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT; in nhmex_rbox_alter_er()
955 hwc->config += 1 << NHMEX_R_PMON_CTL_EV_SEL_SHIFT; in nhmex_rbox_alter_er()
962 reg1->config >>= 8; in nhmex_rbox_alter_er()
966 reg1->config <<= 8; in nhmex_rbox_alter_er()
993 config1 = reg1->config; in nhmex_rbox_get_constraint()
1004 if (!atomic_read(&er->ref) || er->config == reg1->config) { in nhmex_rbox_get_constraint()
1006 er->config = reg1->config; in nhmex_rbox_get_constraint()
1016 !((er->config ^ config1) & mask)) { in nhmex_rbox_get_constraint()
1018 er->config &= ~mask; in nhmex_rbox_get_constraint()
1019 er->config |= config1 & mask; in nhmex_rbox_get_constraint()
1024 (er->config == (hwc->config >> 32) && in nhmex_rbox_get_constraint()
1025 er->config1 == reg1->config && in nhmex_rbox_get_constraint()
1026 er->config2 == reg2->config)) { in nhmex_rbox_get_constraint()
1028 er->config = (hwc->config >> 32); in nhmex_rbox_get_constraint()
1029 er->config1 = reg1->config; in nhmex_rbox_get_constraint()
1030 er->config2 = reg2->config; in nhmex_rbox_get_constraint()
1093 idx = (event->hw.config & NHMEX_R_PMON_CTL_EV_SEL_MASK) >> in nhmex_rbox_hw_config()
1099 reg1->config = event->attr.config1; in nhmex_rbox_hw_config()
1104 hwc->config |= event->attr.config & (~0ULL << 32); in nhmex_rbox_hw_config()
1105 reg2->config = event->attr.config2; in nhmex_rbox_hw_config()
1123 wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG0(port), reg1->config); in nhmex_rbox_msr_enable_event()
1126 wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG1(port), reg1->config); in nhmex_rbox_msr_enable_event()
1135 hwc->config >> 32); in nhmex_rbox_msr_enable_event()
1136 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(port), reg1->config); in nhmex_rbox_msr_enable_event()
1137 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MASK(port), reg2->config); in nhmex_rbox_msr_enable_event()
1141 hwc->config >> 32); in nhmex_rbox_msr_enable_event()
1142 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config); in nhmex_rbox_msr_enable_event()
1143 wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MASK(port), reg2->config); in nhmex_rbox_msr_enable_event()
1148 (hwc->config & NHMEX_R_PMON_CTL_EV_SEL_MASK)); in nhmex_rbox_msr_enable_event()