130 static u32 __init find_cap(int bus, int slot, int func, int cap)  in find_cap()  argument
135 	if (!(read_pci_config_16(bus, slot, func, PCI_STATUS) &  in find_cap()
139 	pos = read_pci_config_byte(bus, slot, func, PCI_CAPABILITY_LIST);  in find_cap()
144 		id = read_pci_config_byte(bus, slot, func, pos+PCI_CAP_LIST_ID);  in find_cap()
149 		pos = read_pci_config_byte(bus, slot, func,  in find_cap()
156 static u32 __init read_agp(int bus, int slot, int func, int cap, u32 *order)  in read_agp()  argument
165 	pr_info("pci 0000:%02x:%02x:%02x: AGP bridge\n", bus, slot, func);  in read_agp()
166 	apsizereg = read_pci_config_16(bus, slot, func, cap + 0x14);  in read_agp()
169 		       bus, slot, func);  in read_agp()
185 	aper_low = read_pci_config(bus, slot, func, 0x10);  in read_agp()
186 	aper_hi = read_pci_config(bus, slot, func, 0x14);  in read_agp()
194 		bus, slot, func, aper, aper + (32ULL << (old_order + 20)) - 1,  in read_agp()
198 			bus, slot, func, 32 << *order, apsizereg);  in read_agp()
203 		bus, slot, func, aper, aper + (32ULL << (*order + 20)) - 1,  in read_agp()
226 	int bus, slot, func;  in search_agp_bridge()  local
229 	for (bus = 0; bus < 256; bus++) {  in search_agp_bridge()
234 				class = read_pci_config(bus, slot, func,  in search_agp_bridge()
243 					cap = find_cap(bus, slot, func,  in search_agp_bridge()
248 					return read_agp(bus, slot, func, cap,  in search_agp_bridge()
253 				type = read_pci_config_byte(bus, slot, func,  in search_agp_bridge()
308 		int bus;  in early_gart_iommu_check()  local
311 		bus = amd_nb_bus_dev_ranges[i].bus;  in early_gart_iommu_check()
316 			if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))  in early_gart_iommu_check()
319 			ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);  in early_gart_iommu_check()
323 			aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;  in early_gart_iommu_check()
364 		int bus;  in early_gart_iommu_check()  local
367 		bus = amd_nb_bus_dev_ranges[i].bus;  in early_gart_iommu_check()
372 			if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))  in early_gart_iommu_check()
375 			ctl = read_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL);  in early_gart_iommu_check()
377 			write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);  in early_gart_iommu_check()
408 		int bus;  in gart_iommu_hole_init()  local
412 		bus = amd_nb_bus_dev_ranges[i].bus;  in gart_iommu_hole_init()
417 			if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))  in gart_iommu_hole_init()
424 			ctl = read_pci_config(bus, slot, 3,  in gart_iommu_hole_init()
434 			write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);  in gart_iommu_hole_init()
438 			aper_base = read_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE) & 0x7fff;  in gart_iommu_hole_init()
533 		int bus, dev_base, dev_limit;  in gart_iommu_hole_init()  local
541 		bus = amd_nb_bus_dev_ranges[i].bus;  in gart_iommu_hole_init()
545 			if (!early_is_amd_nb(read_pci_config(bus, slot, 3, 0x00)))  in gart_iommu_hole_init()
548 			write_pci_config(bus, slot, 3, AMD64_GARTAPERTURECTL, ctl);  in gart_iommu_hole_init()
549 			write_pci_config(bus, slot, 3, AMD64_GARTAPERTUREBASE, aper_alloc >> 25);  in gart_iommu_hole_init()