Lines Matching refs:u32
29 u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
30 u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
31 u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and
34 u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
35 u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
36 u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
38 u32 porcir; /* 0x.0020 - POR Configuration Information
42 u32 gpiocr; /* 0x.0030 - GPIO Control Register */
44 u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data
48 u32 gpindr; /* 0x.0050 - General-Purpose Input Data
52 u32 pmuxcr; /* 0x.0060 - Alternate Function Signal
55 u32 pmuxcr2; /* 0x.0064 - Alternate function signal
58 u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
60 u32 devdisr; /* 0x.0070 - Device Disable Control */
63 u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
65 u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control
68 u32 powmgtcsr; /* 0x.0080 - Power Management Status and
71 u32 pmrccr; /* 0x.0084 - Power Management Reset Counter
74 u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter
77 u32 pmcdr; /* 0x.008c - 4Power management clock disable
80 u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
81 u32 rstrscr; /* 0x.0094 - Reset Request Status and
84 u32 ectrstcr; /* 0x.0098 - Exception reset control register */
85 u32 autorstsr; /* 0x.009c - Automatic reset status register */
86 u32 pvr; /* 0x.00a0 - Processor Version Register */
87 u32 svr; /* 0x.00a4 - System Version Register */
89 u32 rstcr; /* 0x.00b0 - Reset Control Register */
91 u32 iovselsr; /* 0x.00c0 - I/O voltage select status register
94 u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
97 u32 iodelay1; /* 0x.0224 - IO delay control register 1 */
98 u32 iodelay2; /* 0x.0228 - IO delay control register 2 */
100 u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
102 u32 clkdvdr; /* 0x.0800 - Clock Divide Register */
104 u32 ircr; /* 0x.0900 - Infrared Control Register */
106 u32 dmacr; /* 0x.0908 - DMA Control Register */
108 u32 elbccr; /* 0x.0914 - eLBC Control Register */
110 u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
111 u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
112 u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
114 u32 clkocr; /* 0x.0e00 - Clock Out Select Register */
116 u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
118 u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
119 u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override
123 u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
124 u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
126 u32 itcr; /* 0x.0f2c - Internal transaction control
130 u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
131 u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */