Lines Matching refs:fourcc_mod_code

317 #define fourcc_mod_code(vendor, val) \  macro
335 #define DRM_FORMAT_MOD_INVALID	fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
345 #define DRM_FORMAT_MOD_LINEAR	fourcc_mod_code(NONE, 0)
361 #define I915_FORMAT_MOD_X_TILED	fourcc_mod_code(INTEL, 1)
376 #define I915_FORMAT_MOD_Y_TILED	fourcc_mod_code(INTEL, 2)
391 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
410 #define I915_FORMAT_MOD_Y_TILED_CCS	fourcc_mod_code(INTEL, 4)
411 #define I915_FORMAT_MOD_Yf_TILED_CCS	fourcc_mod_code(INTEL, 5)
426 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE	fourcc_mod_code(SAMSUNG, 1)
435 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE	fourcc_mod_code(SAMSUNG, 2)
448 #define DRM_FORMAT_MOD_QCOM_COMPRESSED	fourcc_mod_code(QCOM, 1)
456 #define DRM_FORMAT_MOD_QCOM_DX	fourcc_mod_code(QCOM, 0x2)
464 #define DRM_FORMAT_MOD_QCOM_TIGHT	fourcc_mod_code(QCOM, 0x4)
472 #define DRM_FORMAT_MOD_QCOM_TILE	fourcc_mod_code(QCOM, 0x8)
482 #define DRM_FORMAT_MOD_VIVANTE_TILED		fourcc_mod_code(VIVANTE, 1)
494 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED	fourcc_mod_code(VIVANTE, 2)
503 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED	fourcc_mod_code(VIVANTE, 3)
512 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
521 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
545 	fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
548 	fourcc_mod_code(NVIDIA, 0x10)
550 	fourcc_mod_code(NVIDIA, 0x11)
552 	fourcc_mod_code(NVIDIA, 0x12)
554 	fourcc_mod_code(NVIDIA, 0x13)
556 	fourcc_mod_code(NVIDIA, 0x14)
558 	fourcc_mod_code(NVIDIA, 0x15)
569 	fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
596 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
659 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
675 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode)	fourcc_mod_code(ARM, __afbc_mode)
781 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)