Lines Matching refs:val
59 static void __hyp_text __gic_v3_set_lr(u64 val, int lr) in __gic_v3_set_lr() argument
63 write_gicreg(val, ICH_LR0_EL2); in __gic_v3_set_lr()
66 write_gicreg(val, ICH_LR1_EL2); in __gic_v3_set_lr()
69 write_gicreg(val, ICH_LR2_EL2); in __gic_v3_set_lr()
72 write_gicreg(val, ICH_LR3_EL2); in __gic_v3_set_lr()
75 write_gicreg(val, ICH_LR4_EL2); in __gic_v3_set_lr()
78 write_gicreg(val, ICH_LR5_EL2); in __gic_v3_set_lr()
81 write_gicreg(val, ICH_LR6_EL2); in __gic_v3_set_lr()
84 write_gicreg(val, ICH_LR7_EL2); in __gic_v3_set_lr()
87 write_gicreg(val, ICH_LR8_EL2); in __gic_v3_set_lr()
90 write_gicreg(val, ICH_LR9_EL2); in __gic_v3_set_lr()
93 write_gicreg(val, ICH_LR10_EL2); in __gic_v3_set_lr()
96 write_gicreg(val, ICH_LR11_EL2); in __gic_v3_set_lr()
99 write_gicreg(val, ICH_LR12_EL2); in __gic_v3_set_lr()
102 write_gicreg(val, ICH_LR13_EL2); in __gic_v3_set_lr()
105 write_gicreg(val, ICH_LR14_EL2); in __gic_v3_set_lr()
108 write_gicreg(val, ICH_LR15_EL2); in __gic_v3_set_lr()
113 static void __hyp_text __vgic_v3_write_ap0rn(u32 val, int n) in __vgic_v3_write_ap0rn() argument
117 write_gicreg(val, ICH_AP0R0_EL2); in __vgic_v3_write_ap0rn()
120 write_gicreg(val, ICH_AP0R1_EL2); in __vgic_v3_write_ap0rn()
123 write_gicreg(val, ICH_AP0R2_EL2); in __vgic_v3_write_ap0rn()
126 write_gicreg(val, ICH_AP0R3_EL2); in __vgic_v3_write_ap0rn()
131 static void __hyp_text __vgic_v3_write_ap1rn(u32 val, int n) in __vgic_v3_write_ap1rn() argument
135 write_gicreg(val, ICH_AP1R0_EL2); in __vgic_v3_write_ap1rn()
138 write_gicreg(val, ICH_AP1R1_EL2); in __vgic_v3_write_ap1rn()
141 write_gicreg(val, ICH_AP1R2_EL2); in __vgic_v3_write_ap1rn()
144 write_gicreg(val, ICH_AP1R3_EL2); in __vgic_v3_write_ap1rn()
151 u32 val; in __vgic_v3_read_ap0rn() local
155 val = read_gicreg(ICH_AP0R0_EL2); in __vgic_v3_read_ap0rn()
158 val = read_gicreg(ICH_AP0R1_EL2); in __vgic_v3_read_ap0rn()
161 val = read_gicreg(ICH_AP0R2_EL2); in __vgic_v3_read_ap0rn()
164 val = read_gicreg(ICH_AP0R3_EL2); in __vgic_v3_read_ap0rn()
170 return val; in __vgic_v3_read_ap0rn()
175 u32 val; in __vgic_v3_read_ap1rn() local
179 val = read_gicreg(ICH_AP1R0_EL2); in __vgic_v3_read_ap1rn()
182 val = read_gicreg(ICH_AP1R1_EL2); in __vgic_v3_read_ap1rn()
185 val = read_gicreg(ICH_AP1R2_EL2); in __vgic_v3_read_ap1rn()
188 val = read_gicreg(ICH_AP1R3_EL2); in __vgic_v3_read_ap1rn()
194 return val; in __vgic_v3_read_ap1rn()
312 u64 val; in __vgic_v3_deactivate_traps() local
318 val = read_gicreg(ICC_SRE_EL2); in __vgic_v3_deactivate_traps()
319 write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2); in __vgic_v3_deactivate_traps()
339 u64 val; in __vgic_v3_save_aprs() local
345 val = read_gicreg(ICH_VTR_EL2); in __vgic_v3_save_aprs()
346 nr_pre_bits = vtr_to_nr_pre_bits(val); in __vgic_v3_save_aprs()
376 u64 val; in __vgic_v3_restore_aprs() local
382 val = read_gicreg(ICH_VTR_EL2); in __vgic_v3_restore_aprs()
383 nr_pre_bits = vtr_to_nr_pre_bits(val); in __vgic_v3_restore_aprs()
461 u64 val = __gic_v3_get_lr(i); in __vgic_v3_highest_priority_lr() local
462 u8 lr_prio = (val & ICH_LR_PRIORITY_MASK) >> ICH_LR_PRIORITY_SHIFT; in __vgic_v3_highest_priority_lr()
465 if ((val & ICH_LR_STATE) != ICH_LR_PENDING_BIT) in __vgic_v3_highest_priority_lr()
469 if (!(val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG0_MASK)) in __vgic_v3_highest_priority_lr()
473 if ((val & ICH_LR_GROUP) && !(vmcr & ICH_VMCR_ENG1_MASK)) in __vgic_v3_highest_priority_lr()
482 *lr_val = val; in __vgic_v3_highest_priority_lr()
499 u64 val = __gic_v3_get_lr(i); in __vgic_v3_find_active_lr() local
501 if ((val & ICH_LR_VIRTUAL_ID_MASK) == intid && in __vgic_v3_find_active_lr()
502 (val & ICH_LR_ACTIVE_BIT)) { in __vgic_v3_find_active_lr()
503 *lr_val = val; in __vgic_v3_find_active_lr()
519 u32 val; in __vgic_v3_get_highest_active_priority() local
531 val = __vgic_v3_read_ap0rn(i); in __vgic_v3_get_highest_active_priority()
532 val |= __vgic_v3_read_ap1rn(i); in __vgic_v3_get_highest_active_priority()
533 if (!val) { in __vgic_v3_get_highest_active_priority()
538 return (hap + __ffs(val)) << __vgic_v3_bpr_min(); in __vgic_v3_get_highest_active_priority()
589 u32 val; in __vgic_v3_set_active_priority() local
597 val = __vgic_v3_read_ap0rn(apr); in __vgic_v3_set_active_priority()
598 __vgic_v3_write_ap0rn(val | BIT(ap % 32), apr); in __vgic_v3_set_active_priority()
600 val = __vgic_v3_read_ap1rn(apr); in __vgic_v3_set_active_priority()
601 __vgic_v3_write_ap1rn(val | BIT(ap % 32), apr); in __vgic_v3_set_active_priority()
774 u64 val = vcpu_get_reg(vcpu, rt); in __vgic_v3_write_igrpen0() local
776 if (val & 1) in __vgic_v3_write_igrpen0()
786 u64 val = vcpu_get_reg(vcpu, rt); in __vgic_v3_write_igrpen1() local
788 if (val & 1) in __vgic_v3_write_igrpen1()
808 u64 val = vcpu_get_reg(vcpu, rt); in __vgic_v3_write_bpr0() local
812 if (val < bpr_min) in __vgic_v3_write_bpr0()
813 val = bpr_min; in __vgic_v3_write_bpr0()
815 val <<= ICH_VMCR_BPR0_SHIFT; in __vgic_v3_write_bpr0()
816 val &= ICH_VMCR_BPR0_MASK; in __vgic_v3_write_bpr0()
818 vmcr |= val; in __vgic_v3_write_bpr0()
825 u64 val = vcpu_get_reg(vcpu, rt); in __vgic_v3_write_bpr1() local
832 if (val < bpr_min) in __vgic_v3_write_bpr1()
833 val = bpr_min; in __vgic_v3_write_bpr1()
835 val <<= ICH_VMCR_BPR1_SHIFT; in __vgic_v3_write_bpr1()
836 val &= ICH_VMCR_BPR1_MASK; in __vgic_v3_write_bpr1()
838 vmcr |= val; in __vgic_v3_write_bpr1()
845 u32 val; in __vgic_v3_read_apxrn() local
848 val = __vgic_v3_read_ap0rn(n); in __vgic_v3_read_apxrn()
850 val = __vgic_v3_read_ap1rn(n); in __vgic_v3_read_apxrn()
852 vcpu_set_reg(vcpu, rt, val); in __vgic_v3_read_apxrn()
857 u32 val = vcpu_get_reg(vcpu, rt); in __vgic_v3_write_apxrn() local
860 __vgic_v3_write_ap0rn(val, n); in __vgic_v3_write_apxrn()
862 __vgic_v3_write_ap1rn(val, n); in __vgic_v3_write_apxrn()
944 u32 val = vcpu_get_reg(vcpu, rt); in __vgic_v3_write_pmr() local
946 val <<= ICH_VMCR_PMR_SHIFT; in __vgic_v3_write_pmr()
947 val &= ICH_VMCR_PMR_MASK; in __vgic_v3_write_pmr()
949 vmcr |= val; in __vgic_v3_write_pmr()
957 u32 val = __vgic_v3_get_highest_active_priority(); in __vgic_v3_read_rpr() local
958 vcpu_set_reg(vcpu, rt, val); in __vgic_v3_read_rpr()
964 u32 vtr, val; in __vgic_v3_read_ctlr() local
968 val = ((vtr >> 29) & 7) << ICC_CTLR_EL1_PRI_BITS_SHIFT; in __vgic_v3_read_ctlr()
970 val |= ((vtr >> 23) & 7) << ICC_CTLR_EL1_ID_BITS_SHIFT; in __vgic_v3_read_ctlr()
972 val |= ((vtr >> 22) & 1) << ICC_CTLR_EL1_SEIS_SHIFT; in __vgic_v3_read_ctlr()
974 val |= ((vtr >> 21) & 1) << ICC_CTLR_EL1_A3V_SHIFT; in __vgic_v3_read_ctlr()
976 val |= ((vmcr & ICH_VMCR_EOIM_MASK) >> ICH_VMCR_EOIM_SHIFT) << ICC_CTLR_EL1_EOImode_SHIFT; in __vgic_v3_read_ctlr()
978 val |= (vmcr & ICH_VMCR_CBPR_MASK) >> ICH_VMCR_CBPR_SHIFT; in __vgic_v3_read_ctlr()
980 vcpu_set_reg(vcpu, rt, val); in __vgic_v3_read_ctlr()
986 u32 val = vcpu_get_reg(vcpu, rt); in __vgic_v3_write_ctlr() local
988 if (val & ICC_CTLR_EL1_CBPR_MASK) in __vgic_v3_write_ctlr()
993 if (val & ICC_CTLR_EL1_EOImode_MASK) in __vgic_v3_write_ctlr()