54 				    unsigned long val)  in vgic_mmio_write_v2_misc()  argument
61 		dist->enabled = val & GICD_ENABLE;  in vgic_mmio_write_v2_misc()
74 					   unsigned long val)  in vgic_mmio_uaccess_write_v2_misc()  argument
78 		if (val != vgic_mmio_read_v2_misc(vcpu, addr, len))  in vgic_mmio_uaccess_write_v2_misc()
94 	vgic_mmio_write_v2_misc(vcpu, addr, len, val);  in vgic_mmio_uaccess_write_v2_misc()
100 					    unsigned long val)  in vgic_mmio_uaccess_write_v2_group()  argument
103 		vgic_mmio_write_group(vcpu, addr, len, val);  in vgic_mmio_uaccess_write_v2_group()
110 				 unsigned long val)  in vgic_mmio_write_sgir()  argument
113 	int intid = val & 0xf;  in vgic_mmio_write_sgir()
114 	int targets = (val >> 16) & 0xff;  in vgic_mmio_write_sgir()
115 	int mode = (val >> 24) & 0x03;  in vgic_mmio_write_sgir()
156 	u64 val = 0;  in vgic_mmio_read_target()  local
161 		val |= (u64)irq->targets << (i * 8);  in vgic_mmio_read_target()
166 	return val;  in vgic_mmio_read_target()
171 				   unsigned long val)  in vgic_mmio_write_target()  argument
188 		irq->targets = (val >> (i * 8)) & cpu_mask;  in vgic_mmio_write_target()
202 	u64 val = 0;  in vgic_mmio_read_sgipend()  local
207 		val |= (u64)irq->source << (i * 8);  in vgic_mmio_read_sgipend()
211 	return val;  in vgic_mmio_read_sgipend()
216 				     unsigned long val)  in vgic_mmio_write_sgipendc()  argument
227 		irq->source &= ~((val >> (i * 8)) & 0xff);  in vgic_mmio_write_sgipendc()
238 				     unsigned long val)  in vgic_mmio_write_sgipends()  argument
249 		irq->source |= (val >> (i * 8)) & 0xff;  in vgic_mmio_write_sgipends()
268 	u32 val;  in vgic_mmio_read_vcpuif()  local
274 		val = vmcr.grpen0 << GIC_CPU_CTRL_EnableGrp0_SHIFT;  in vgic_mmio_read_vcpuif()
275 		val |= vmcr.grpen1 << GIC_CPU_CTRL_EnableGrp1_SHIFT;  in vgic_mmio_read_vcpuif()
276 		val |= vmcr.ackctl << GIC_CPU_CTRL_AckCtl_SHIFT;  in vgic_mmio_read_vcpuif()
277 		val |= vmcr.fiqen << GIC_CPU_CTRL_FIQEn_SHIFT;  in vgic_mmio_read_vcpuif()
278 		val |= vmcr.cbpr << GIC_CPU_CTRL_CBPR_SHIFT;  in vgic_mmio_read_vcpuif()
279 		val |= vmcr.eoim << GIC_CPU_CTRL_EOImodeNS_SHIFT;  in vgic_mmio_read_vcpuif()
290 		val = (vmcr.pmr & GICV_PMR_PRIORITY_MASK) >>  in vgic_mmio_read_vcpuif()
294 		val = vmcr.bpr;  in vgic_mmio_read_vcpuif()
297 		val = vmcr.abpr;  in vgic_mmio_read_vcpuif()
300 		val = ((PRODUCT_ID_KVM << 20) |  in vgic_mmio_read_vcpuif()
308 	return val;  in vgic_mmio_read_vcpuif()
313 				   unsigned long val)  in vgic_mmio_write_vcpuif()  argument
321 		vmcr.grpen0 = !!(val & GIC_CPU_CTRL_EnableGrp0);  in vgic_mmio_write_vcpuif()
322 		vmcr.grpen1 = !!(val & GIC_CPU_CTRL_EnableGrp1);  in vgic_mmio_write_vcpuif()
323 		vmcr.ackctl = !!(val & GIC_CPU_CTRL_AckCtl);  in vgic_mmio_write_vcpuif()
324 		vmcr.fiqen = !!(val & GIC_CPU_CTRL_FIQEn);  in vgic_mmio_write_vcpuif()
325 		vmcr.cbpr = !!(val & GIC_CPU_CTRL_CBPR);  in vgic_mmio_write_vcpuif()
326 		vmcr.eoim = !!(val & GIC_CPU_CTRL_EOImodeNS);  in vgic_mmio_write_vcpuif()
337 		vmcr.pmr = (val << GICV_PMR_PRIORITY_SHIFT) &  in vgic_mmio_write_vcpuif()
341 		vmcr.bpr = val;  in vgic_mmio_write_vcpuif()
344 		vmcr.abpr = val;  in vgic_mmio_write_vcpuif()
378 				unsigned long val)  in vgic_mmio_write_apr()  argument
388 		vcpu->arch.vgic_cpu.vgic_v2.vgic_apr = val;  in vgic_mmio_write_apr()
398 		vgicv3->vgic_ap1r[n] = val;  in vgic_mmio_write_apr()
525 			  int offset, u32 *val)  in vgic_v2_cpuif_uaccess()  argument
533 	return vgic_uaccess(vcpu, &dev, is_write, offset, val);  in vgic_v2_cpuif_uaccess()
537 			 int offset, u32 *val)  in vgic_v2_dist_uaccess()  argument
545 	return vgic_uaccess(vcpu, &dev, is_write, offset, val);  in vgic_v2_dist_uaccess()