28 		     unsigned long val)  in update_64bit_reg()  argument
34 	val &= GENMASK_ULL(len * 8 - 1, 0);  in update_64bit_reg()
36 	return reg | ((u64)val << lower);  in update_64bit_reg()
97 				    unsigned long val)  in vgic_mmio_write_v3_misc()  argument
104 		dist->enabled = val & GICD_CTLR_ENABLE_SS_G1;  in vgic_mmio_write_v3_misc()
117 					   unsigned long val)  in vgic_mmio_uaccess_write_v3_misc()  argument
121 		if (val != vgic_mmio_read_v3_misc(vcpu, addr, len))  in vgic_mmio_uaccess_write_v3_misc()
125 	vgic_mmio_write_v3_misc(vcpu, addr, len, val);  in vgic_mmio_uaccess_write_v3_misc()
149 				    unsigned long val)  in vgic_mmio_write_irouter()  argument
167 	irq->mpidr = val & GENMASK(23, 0);  in vgic_mmio_write_irouter()
185 				     unsigned long val)  in vgic_mmio_write_v3r_ctlr()  argument
193 	vgic_cpu->lpis_enabled = val & GICR_CTLR_ENABLE_LPIS;  in vgic_mmio_write_v3r_ctlr()
289 					 unsigned long val)  in vgic_v3_uaccess_write_pending()  argument
299 		if (test_bit(i, &val)) {  in vgic_v3_uaccess_write_pending()
411 				     unsigned long val)  in vgic_mmio_write_propbase()  argument
424 		propbaser = update_64bit_reg(propbaser, addr & 4, len, val);  in vgic_mmio_write_propbase()
440 				     unsigned long val)  in vgic_mmio_write_pendbase()  argument
452 		pendbaser = update_64bit_reg(pendbaser, addr & 4, len, val);  in vgic_mmio_write_pendbase()
971 			 int offset, u32 *val)  in vgic_v3_dist_uaccess()  argument
978 	return vgic_uaccess(vcpu, &dev, is_write, offset, val);  in vgic_v3_dist_uaccess()
982 			   int offset, u32 *val)  in vgic_v3_redist_uaccess()  argument
989 	return vgic_uaccess(vcpu, &rd_dev, is_write, offset, val);  in vgic_v3_redist_uaccess()
993 				    u32 intid, u64 *val)  in vgic_v3_line_level_info_uaccess()  argument
999 		vgic_write_irq_line_level_info(vcpu, intid, *val);  in vgic_v3_line_level_info_uaccess()
1001 		*val = vgic_read_irq_line_level_info(vcpu, intid);  in vgic_v3_line_level_info_uaccess()