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1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2014 Linaro Ltd. <ard.biesheuvel@linaro.org>
4  */
5 
6 #ifndef __ASM_CPUFEATURE_H
7 #define __ASM_CPUFEATURE_H
8 
9 #include <asm/cpucaps.h>
10 #include <asm/cputype.h>
11 #include <asm/hwcap.h>
12 #include <asm/sysreg.h>
13 
14 #define MAX_CPU_FEATURES	64
15 #define cpu_feature(x)		KERNEL_HWCAP_ ## x
16 
17 #ifndef __ASSEMBLY__
18 
19 #include <linux/bug.h>
20 #include <linux/jump_label.h>
21 #include <linux/kernel.h>
22 
23 /*
24  * CPU feature register tracking
25  *
26  * The safe value of a CPUID feature field is dependent on the implications
27  * of the values assigned to it by the architecture. Based on the relationship
28  * between the values, the features are classified into 3 types - LOWER_SAFE,
29  * HIGHER_SAFE and EXACT.
30  *
31  * The lowest value of all the CPUs is chosen for LOWER_SAFE and highest
32  * for HIGHER_SAFE. It is expected that all CPUs have the same value for
33  * a field when EXACT is specified, failing which, the safe value specified
34  * in the table is chosen.
35  */
36 
37 enum ftr_type {
38 	FTR_EXACT,			/* Use a predefined safe value */
39 	FTR_LOWER_SAFE,			/* Smaller value is safe */
40 	FTR_HIGHER_SAFE,		/* Bigger value is safe */
41 	FTR_HIGHER_OR_ZERO_SAFE,	/* Bigger value is safe, but 0 is biggest */
42 };
43 
44 #define FTR_STRICT	true	/* SANITY check strict matching required */
45 #define FTR_NONSTRICT	false	/* SANITY check ignored */
46 
47 #define FTR_SIGNED	true	/* Value should be treated as signed */
48 #define FTR_UNSIGNED	false	/* Value should be treated as unsigned */
49 
50 #define FTR_VISIBLE	true	/* Feature visible to the user space */
51 #define FTR_HIDDEN	false	/* Feature is hidden from the user */
52 
53 #define FTR_VISIBLE_IF_IS_ENABLED(config)		\
54 	(IS_ENABLED(config) ? FTR_VISIBLE : FTR_HIDDEN)
55 
56 struct arm64_ftr_bits {
57 	bool		sign;	/* Value is signed ? */
58 	bool		visible;
59 	bool		strict;	/* CPU Sanity check: strict matching required ? */
60 	enum ftr_type	type;
61 	u8		shift;
62 	u8		width;
63 	s64		safe_val; /* safe value for FTR_EXACT features */
64 };
65 
66 /*
67  * @arm64_ftr_reg - Feature register
68  * @strict_mask		Bits which should match across all CPUs for sanity.
69  * @sys_val		Safe value across the CPUs (system view)
70  */
71 struct arm64_ftr_reg {
72 	const char			*name;
73 	u64				strict_mask;
74 	u64				user_mask;
75 	u64				sys_val;
76 	u64				user_val;
77 	const struct arm64_ftr_bits	*ftr_bits;
78 };
79 
80 extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0;
81 
82 /*
83  * CPU capabilities:
84  *
85  * We use arm64_cpu_capabilities to represent system features, errata work
86  * arounds (both used internally by kernel and tracked in cpu_hwcaps) and
87  * ELF HWCAPs (which are exposed to user).
88  *
89  * To support systems with heterogeneous CPUs, we need to make sure that we
90  * detect the capabilities correctly on the system and take appropriate
91  * measures to ensure there are no incompatibilities.
92  *
93  * This comment tries to explain how we treat the capabilities.
94  * Each capability has the following list of attributes :
95  *
96  * 1) Scope of Detection : The system detects a given capability by
97  *    performing some checks at runtime. This could be, e.g, checking the
98  *    value of a field in CPU ID feature register or checking the cpu
99  *    model. The capability provides a call back ( @matches() ) to
100  *    perform the check. Scope defines how the checks should be performed.
101  *    There are three cases:
102  *
103  *     a) SCOPE_LOCAL_CPU: check all the CPUs and "detect" if at least one
104  *        matches. This implies, we have to run the check on all the
105  *        booting CPUs, until the system decides that state of the
106  *        capability is finalised. (See section 2 below)
107  *		Or
108  *     b) SCOPE_SYSTEM: check all the CPUs and "detect" if all the CPUs
109  *        matches. This implies, we run the check only once, when the
110  *        system decides to finalise the state of the capability. If the
111  *        capability relies on a field in one of the CPU ID feature
112  *        registers, we use the sanitised value of the register from the
113  *        CPU feature infrastructure to make the decision.
114  *		Or
115  *     c) SCOPE_BOOT_CPU: Check only on the primary boot CPU to detect the
116  *        feature. This category is for features that are "finalised"
117  *        (or used) by the kernel very early even before the SMP cpus
118  *        are brought up.
119  *
120  *    The process of detection is usually denoted by "update" capability
121  *    state in the code.
122  *
123  * 2) Finalise the state : The kernel should finalise the state of a
124  *    capability at some point during its execution and take necessary
125  *    actions if any. Usually, this is done, after all the boot-time
126  *    enabled CPUs are brought up by the kernel, so that it can make
127  *    better decision based on the available set of CPUs. However, there
128  *    are some special cases, where the action is taken during the early
129  *    boot by the primary boot CPU. (e.g, running the kernel at EL2 with
130  *    Virtualisation Host Extensions). The kernel usually disallows any
131  *    changes to the state of a capability once it finalises the capability
132  *    and takes any action, as it may be impossible to execute the actions
133  *    safely. A CPU brought up after a capability is "finalised" is
134  *    referred to as "Late CPU" w.r.t the capability. e.g, all secondary
135  *    CPUs are treated "late CPUs" for capabilities determined by the boot
136  *    CPU.
137  *
138  *    At the moment there are two passes of finalising the capabilities.
139  *      a) Boot CPU scope capabilities - Finalised by primary boot CPU via
140  *         setup_boot_cpu_capabilities().
141  *      b) Everything except (a) - Run via setup_system_capabilities().
142  *
143  * 3) Verification: When a CPU is brought online (e.g, by user or by the
144  *    kernel), the kernel should make sure that it is safe to use the CPU,
145  *    by verifying that the CPU is compliant with the state of the
146  *    capabilities finalised already. This happens via :
147  *
148  *	secondary_start_kernel()-> check_local_cpu_capabilities()
149  *
150  *    As explained in (2) above, capabilities could be finalised at
151  *    different points in the execution. Each newly booted CPU is verified
152  *    against the capabilities that have been finalised by the time it
153  *    boots.
154  *
155  *	a) SCOPE_BOOT_CPU : All CPUs are verified against the capability
156  *	except for the primary boot CPU.
157  *
158  *	b) SCOPE_LOCAL_CPU, SCOPE_SYSTEM: All CPUs hotplugged on by the
159  *	user after the kernel boot are verified against the capability.
160  *
161  *    If there is a conflict, the kernel takes an action, based on the
162  *    severity (e.g, a CPU could be prevented from booting or cause a
163  *    kernel panic). The CPU is allowed to "affect" the state of the
164  *    capability, if it has not been finalised already. See section 5
165  *    for more details on conflicts.
166  *
167  * 4) Action: As mentioned in (2), the kernel can take an action for each
168  *    detected capability, on all CPUs on the system. Appropriate actions
169  *    include, turning on an architectural feature, modifying the control
170  *    registers (e.g, SCTLR, TCR etc.) or patching the kernel via
171  *    alternatives. The kernel patching is batched and performed at later
172  *    point. The actions are always initiated only after the capability
173  *    is finalised. This is usally denoted by "enabling" the capability.
174  *    The actions are initiated as follows :
175  *	a) Action is triggered on all online CPUs, after the capability is
176  *	finalised, invoked within the stop_machine() context from
177  *	enable_cpu_capabilitie().
178  *
179  *	b) Any late CPU, brought up after (1), the action is triggered via:
180  *
181  *	  check_local_cpu_capabilities() -> verify_local_cpu_capabilities()
182  *
183  * 5) Conflicts: Based on the state of the capability on a late CPU vs.
184  *    the system state, we could have the following combinations :
185  *
186  *		x-----------------------------x
187  *		| Type  | System   | Late CPU |
188  *		|-----------------------------|
189  *		|  a    |   y      |    n     |
190  *		|-----------------------------|
191  *		|  b    |   n      |    y     |
192  *		x-----------------------------x
193  *
194  *     Two separate flag bits are defined to indicate whether each kind of
195  *     conflict can be allowed:
196  *		ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU - Case(a) is allowed
197  *		ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU - Case(b) is allowed
198  *
199  *     Case (a) is not permitted for a capability that the system requires
200  *     all CPUs to have in order for the capability to be enabled. This is
201  *     typical for capabilities that represent enhanced functionality.
202  *
203  *     Case (b) is not permitted for a capability that must be enabled
204  *     during boot if any CPU in the system requires it in order to run
205  *     safely. This is typical for erratum work arounds that cannot be
206  *     enabled after the corresponding capability is finalised.
207  *
208  *     In some non-typical cases either both (a) and (b), or neither,
209  *     should be permitted. This can be described by including neither
210  *     or both flags in the capability's type field.
211  */
212 
213 
214 /*
215  * Decide how the capability is detected.
216  * On any local CPU vs System wide vs the primary boot CPU
217  */
218 #define ARM64_CPUCAP_SCOPE_LOCAL_CPU		((u16)BIT(0))
219 #define ARM64_CPUCAP_SCOPE_SYSTEM		((u16)BIT(1))
220 /*
221  * The capabilitiy is detected on the Boot CPU and is used by kernel
222  * during early boot. i.e, the capability should be "detected" and
223  * "enabled" as early as possibly on all booting CPUs.
224  */
225 #define ARM64_CPUCAP_SCOPE_BOOT_CPU		((u16)BIT(2))
226 #define ARM64_CPUCAP_SCOPE_MASK			\
227 	(ARM64_CPUCAP_SCOPE_SYSTEM	|	\
228 	 ARM64_CPUCAP_SCOPE_LOCAL_CPU	|	\
229 	 ARM64_CPUCAP_SCOPE_BOOT_CPU)
230 
231 #define SCOPE_SYSTEM				ARM64_CPUCAP_SCOPE_SYSTEM
232 #define SCOPE_LOCAL_CPU				ARM64_CPUCAP_SCOPE_LOCAL_CPU
233 #define SCOPE_BOOT_CPU				ARM64_CPUCAP_SCOPE_BOOT_CPU
234 #define SCOPE_ALL				ARM64_CPUCAP_SCOPE_MASK
235 
236 /*
237  * Is it permitted for a late CPU to have this capability when system
238  * hasn't already enabled it ?
239  */
240 #define ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU	((u16)BIT(4))
241 /* Is it safe for a late CPU to miss this capability when system has it */
242 #define ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU	((u16)BIT(5))
243 
244 /*
245  * CPU errata workarounds that need to be enabled at boot time if one or
246  * more CPUs in the system requires it. When one of these capabilities
247  * has been enabled, it is safe to allow any CPU to boot that doesn't
248  * require the workaround. However, it is not safe if a "late" CPU
249  * requires a workaround and the system hasn't enabled it already.
250  */
251 #define ARM64_CPUCAP_LOCAL_CPU_ERRATUM		\
252 	(ARM64_CPUCAP_SCOPE_LOCAL_CPU | ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
253 /*
254  * CPU feature detected at boot time based on system-wide value of a
255  * feature. It is safe for a late CPU to have this feature even though
256  * the system hasn't enabled it, although the feature will not be used
257  * by Linux in this case. If the system has enabled this feature already,
258  * then every late CPU must have it.
259  */
260 #define ARM64_CPUCAP_SYSTEM_FEATURE	\
261 	(ARM64_CPUCAP_SCOPE_SYSTEM | ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
262 /*
263  * CPU feature detected at boot time based on feature of one or more CPUs.
264  * All possible conflicts for a late CPU are ignored.
265  * NOTE: this means that a late CPU with the feature will *not* cause the
266  * capability to be advertised by cpus_have_*cap()!
267  */
268 #define ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE		\
269 	(ARM64_CPUCAP_SCOPE_LOCAL_CPU		|	\
270 	 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU	|	\
271 	 ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU)
272 
273 /*
274  * CPU feature detected at boot time, on one or more CPUs. A late CPU
275  * is not allowed to have the capability when the system doesn't have it.
276  * It is Ok for a late CPU to miss the feature.
277  */
278 #define ARM64_CPUCAP_BOOT_RESTRICTED_CPU_LOCAL_FEATURE	\
279 	(ARM64_CPUCAP_SCOPE_LOCAL_CPU		|	\
280 	 ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU)
281 
282 /*
283  * CPU feature used early in the boot based on the boot CPU. All secondary
284  * CPUs must match the state of the capability as detected by the boot CPU.
285  */
286 #define ARM64_CPUCAP_STRICT_BOOT_CPU_FEATURE ARM64_CPUCAP_SCOPE_BOOT_CPU
287 
288 struct arm64_cpu_capabilities {
289 	const char *desc;
290 	u16 capability;
291 	u16 type;
292 	bool (*matches)(const struct arm64_cpu_capabilities *caps, int scope);
293 	/*
294 	 * Take the appropriate actions to configure this capability
295 	 * for this CPU. If the capability is detected by the kernel
296 	 * this will be called on all the CPUs in the system,
297 	 * including the hotplugged CPUs, regardless of whether the
298 	 * capability is available on that specific CPU. This is
299 	 * useful for some capabilities (e.g, working around CPU
300 	 * errata), where all the CPUs must take some action (e.g,
301 	 * changing system control/configuration). Thus, if an action
302 	 * is required only if the CPU has the capability, then the
303 	 * routine must check it before taking any action.
304 	 */
305 	void (*cpu_enable)(const struct arm64_cpu_capabilities *cap);
306 	union {
307 		struct {	/* To be used for erratum handling only */
308 			struct midr_range midr_range;
309 			const struct arm64_midr_revidr {
310 				u32 midr_rv;		/* revision/variant */
311 				u32 revidr_mask;
312 			} * const fixed_revs;
313 		};
314 
315 		const struct midr_range *midr_range_list;
316 		struct {	/* Feature register checking */
317 			u32 sys_reg;
318 			u8 field_pos;
319 			u8 min_field_value;
320 			u8 hwcap_type;
321 			bool sign;
322 			unsigned long hwcap;
323 		};
324 	};
325 
326 	/*
327 	 * An optional list of "matches/cpu_enable" pair for the same
328 	 * "capability" of the same "type" as described by the parent.
329 	 * Only matches(), cpu_enable() and fields relevant to these
330 	 * methods are significant in the list. The cpu_enable is
331 	 * invoked only if the corresponding entry "matches()".
332 	 * However, if a cpu_enable() method is associated
333 	 * with multiple matches(), care should be taken that either
334 	 * the match criteria are mutually exclusive, or that the
335 	 * method is robust against being called multiple times.
336 	 */
337 	const struct arm64_cpu_capabilities *match_list;
338 };
339 
cpucap_default_scope(const struct arm64_cpu_capabilities * cap)340 static inline int cpucap_default_scope(const struct arm64_cpu_capabilities *cap)
341 {
342 	return cap->type & ARM64_CPUCAP_SCOPE_MASK;
343 }
344 
345 static inline bool
cpucap_late_cpu_optional(const struct arm64_cpu_capabilities * cap)346 cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap)
347 {
348 	return !!(cap->type & ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU);
349 }
350 
351 static inline bool
cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities * cap)352 cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap)
353 {
354 	return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU);
355 }
356 
357 /*
358  * Generic helper for handling capabilties with multiple (match,enable) pairs
359  * of call backs, sharing the same capability bit.
360  * Iterate over each entry to see if at least one matches.
361  */
362 static inline bool
cpucap_multi_entry_cap_matches(const struct arm64_cpu_capabilities * entry,int scope)363 cpucap_multi_entry_cap_matches(const struct arm64_cpu_capabilities *entry,
364 			       int scope)
365 {
366 	const struct arm64_cpu_capabilities *caps;
367 
368 	for (caps = entry->match_list; caps->matches; caps++)
369 		if (caps->matches(caps, scope))
370 			return true;
371 
372 	return false;
373 }
374 
375 extern DECLARE_BITMAP(cpu_hwcaps, ARM64_NCAPS);
376 extern struct static_key_false cpu_hwcap_keys[ARM64_NCAPS];
377 extern struct static_key_false arm64_const_caps_ready;
378 
379 /* ARM64 CAPS + alternative_cb */
380 #define ARM64_NPATCHABLE (ARM64_NCAPS + 1)
381 extern DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE);
382 
383 #define for_each_available_cap(cap)		\
384 	for_each_set_bit(cap, cpu_hwcaps, ARM64_NCAPS)
385 
386 bool this_cpu_has_cap(unsigned int cap);
387 void cpu_set_feature(unsigned int num);
388 bool cpu_have_feature(unsigned int num);
389 unsigned long cpu_get_elf_hwcap(void);
390 unsigned long cpu_get_elf_hwcap2(void);
391 
392 #define cpu_set_named_feature(name) cpu_set_feature(cpu_feature(name))
393 #define cpu_have_named_feature(name) cpu_have_feature(cpu_feature(name))
394 
395 /* System capability check for constant caps */
__cpus_have_const_cap(int num)396 static __always_inline bool __cpus_have_const_cap(int num)
397 {
398 	if (num >= ARM64_NCAPS)
399 		return false;
400 	return static_branch_unlikely(&cpu_hwcap_keys[num]);
401 }
402 
cpus_have_cap(unsigned int num)403 static inline bool cpus_have_cap(unsigned int num)
404 {
405 	if (num >= ARM64_NCAPS)
406 		return false;
407 	return test_bit(num, cpu_hwcaps);
408 }
409 
cpus_have_const_cap(int num)410 static __always_inline bool cpus_have_const_cap(int num)
411 {
412 	if (static_branch_likely(&arm64_const_caps_ready))
413 		return __cpus_have_const_cap(num);
414 	else
415 		return cpus_have_cap(num);
416 }
417 
cpus_set_cap(unsigned int num)418 static inline void cpus_set_cap(unsigned int num)
419 {
420 	if (num >= ARM64_NCAPS) {
421 		pr_warn("Attempt to set an illegal CPU capability (%d >= %d)\n",
422 			num, ARM64_NCAPS);
423 	} else {
424 		__set_bit(num, cpu_hwcaps);
425 	}
426 }
427 
428 static inline int __attribute_const__
cpuid_feature_extract_signed_field_width(u64 features,int field,int width)429 cpuid_feature_extract_signed_field_width(u64 features, int field, int width)
430 {
431 	return (s64)(features << (64 - width - field)) >> (64 - width);
432 }
433 
434 static inline int __attribute_const__
cpuid_feature_extract_signed_field(u64 features,int field)435 cpuid_feature_extract_signed_field(u64 features, int field)
436 {
437 	return cpuid_feature_extract_signed_field_width(features, field, 4);
438 }
439 
440 static inline unsigned int __attribute_const__
cpuid_feature_extract_unsigned_field_width(u64 features,int field,int width)441 cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)
442 {
443 	return (u64)(features << (64 - width - field)) >> (64 - width);
444 }
445 
446 static inline unsigned int __attribute_const__
cpuid_feature_extract_unsigned_field(u64 features,int field)447 cpuid_feature_extract_unsigned_field(u64 features, int field)
448 {
449 	return cpuid_feature_extract_unsigned_field_width(features, field, 4);
450 }
451 
452 /*
453  * Fields that identify the version of the Performance Monitors Extension do
454  * not follow the standard ID scheme. See ARM DDI 0487E.a page D13-2825,
455  * "Alternative ID scheme used for the Performance Monitors Extension version".
456  */
457 static inline u64 __attribute_const__
cpuid_feature_cap_perfmon_field(u64 features,int field,u64 cap)458 cpuid_feature_cap_perfmon_field(u64 features, int field, u64 cap)
459 {
460 	u64 val = cpuid_feature_extract_unsigned_field(features, field);
461 	u64 mask = GENMASK_ULL(field + 3, field);
462 
463 	/* Treat IMPLEMENTATION DEFINED functionality as unimplemented */
464 	if (val == 0xf)
465 		val = 0;
466 
467 	if (val > cap) {
468 		features &= ~mask;
469 		features |= (cap << field) & mask;
470 	}
471 
472 	return features;
473 }
474 
arm64_ftr_mask(const struct arm64_ftr_bits * ftrp)475 static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp)
476 {
477 	return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
478 }
479 
arm64_ftr_reg_user_value(const struct arm64_ftr_reg * reg)480 static inline u64 arm64_ftr_reg_user_value(const struct arm64_ftr_reg *reg)
481 {
482 	return (reg->user_val | (reg->sys_val & reg->user_mask));
483 }
484 
485 static inline int __attribute_const__
cpuid_feature_extract_field_width(u64 features,int field,int width,bool sign)486 cpuid_feature_extract_field_width(u64 features, int field, int width, bool sign)
487 {
488 	return (sign) ?
489 		cpuid_feature_extract_signed_field_width(features, field, width) :
490 		cpuid_feature_extract_unsigned_field_width(features, field, width);
491 }
492 
493 static inline int __attribute_const__
cpuid_feature_extract_field(u64 features,int field,bool sign)494 cpuid_feature_extract_field(u64 features, int field, bool sign)
495 {
496 	return cpuid_feature_extract_field_width(features, field, 4, sign);
497 }
498 
arm64_ftr_value(const struct arm64_ftr_bits * ftrp,u64 val)499 static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val)
500 {
501 	return (s64)cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width, ftrp->sign);
502 }
503 
id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)504 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
505 {
506 	return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||
507 		cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;
508 }
509 
id_aa64pfr0_32bit_el0(u64 pfr0)510 static inline bool id_aa64pfr0_32bit_el0(u64 pfr0)
511 {
512 	u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_EL0_SHIFT);
513 
514 	return val == ID_AA64PFR0_EL0_32BIT_64BIT;
515 }
516 
id_aa64pfr0_sve(u64 pfr0)517 static inline bool id_aa64pfr0_sve(u64 pfr0)
518 {
519 	u32 val = cpuid_feature_extract_unsigned_field(pfr0, ID_AA64PFR0_SVE_SHIFT);
520 
521 	return val > 0;
522 }
523 
524 void __init setup_cpu_features(void);
525 void check_local_cpu_capabilities(void);
526 
527 u64 read_sanitised_ftr_reg(u32 id);
528 
cpu_supports_mixed_endian_el0(void)529 static inline bool cpu_supports_mixed_endian_el0(void)
530 {
531 	return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1));
532 }
533 
supports_csv2p3(int scope)534 static inline bool supports_csv2p3(int scope)
535 {
536 	u64 pfr0;
537 	u8 csv2_val;
538 
539 	if (scope == SCOPE_LOCAL_CPU)
540 		pfr0 = read_sysreg_s(SYS_ID_AA64PFR0_EL1);
541 	else
542 		pfr0 = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
543 
544 	csv2_val = cpuid_feature_extract_unsigned_field(pfr0,
545 							ID_AA64PFR0_CSV2_SHIFT);
546 	return csv2_val == 3;
547 }
548 
supports_clearbhb(int scope)549 static inline bool supports_clearbhb(int scope)
550 {
551 	u64 isar2;
552 
553 	if (scope == SCOPE_LOCAL_CPU)
554 		isar2 = read_sysreg_s(SYS_ID_AA64ISAR2_EL1);
555 	else
556 		isar2 = read_sanitised_ftr_reg(SYS_ID_AA64ISAR2_EL1);
557 
558 	return cpuid_feature_extract_unsigned_field(isar2,
559 						    ID_AA64ISAR2_CLEARBHB_SHIFT);
560 }
561 
system_supports_32bit_el0(void)562 static inline bool system_supports_32bit_el0(void)
563 {
564 	return cpus_have_const_cap(ARM64_HAS_32BIT_EL0);
565 }
566 
system_supports_4kb_granule(void)567 static inline bool system_supports_4kb_granule(void)
568 {
569 	u64 mmfr0;
570 	u32 val;
571 
572 	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
573 	val = cpuid_feature_extract_unsigned_field(mmfr0,
574 						ID_AA64MMFR0_TGRAN4_SHIFT);
575 
576 	return val == ID_AA64MMFR0_TGRAN4_SUPPORTED;
577 }
578 
system_supports_64kb_granule(void)579 static inline bool system_supports_64kb_granule(void)
580 {
581 	u64 mmfr0;
582 	u32 val;
583 
584 	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
585 	val = cpuid_feature_extract_unsigned_field(mmfr0,
586 						ID_AA64MMFR0_TGRAN64_SHIFT);
587 
588 	return val == ID_AA64MMFR0_TGRAN64_SUPPORTED;
589 }
590 
system_supports_16kb_granule(void)591 static inline bool system_supports_16kb_granule(void)
592 {
593 	u64 mmfr0;
594 	u32 val;
595 
596 	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
597 	val = cpuid_feature_extract_unsigned_field(mmfr0,
598 						ID_AA64MMFR0_TGRAN16_SHIFT);
599 
600 	return val == ID_AA64MMFR0_TGRAN16_SUPPORTED;
601 }
602 
system_supports_mixed_endian_el0(void)603 static inline bool system_supports_mixed_endian_el0(void)
604 {
605 	return id_aa64mmfr0_mixed_endian_el0(read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1));
606 }
607 
system_supports_mixed_endian(void)608 static inline bool system_supports_mixed_endian(void)
609 {
610 	u64 mmfr0;
611 	u32 val;
612 
613 	mmfr0 =	read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
614 	val = cpuid_feature_extract_unsigned_field(mmfr0,
615 						ID_AA64MMFR0_BIGENDEL_SHIFT);
616 
617 	return val == 0x1;
618 }
619 
system_supports_fpsimd(void)620 static inline bool system_supports_fpsimd(void)
621 {
622 	return !cpus_have_const_cap(ARM64_HAS_NO_FPSIMD);
623 }
624 
system_uses_ttbr0_pan(void)625 static inline bool system_uses_ttbr0_pan(void)
626 {
627 	return IS_ENABLED(CONFIG_ARM64_SW_TTBR0_PAN) &&
628 		!cpus_have_const_cap(ARM64_HAS_PAN);
629 }
630 
system_supports_sve(void)631 static inline bool system_supports_sve(void)
632 {
633 	return IS_ENABLED(CONFIG_ARM64_SVE) &&
634 		cpus_have_const_cap(ARM64_SVE);
635 }
636 
system_supports_cnp(void)637 static inline bool system_supports_cnp(void)
638 {
639 	return IS_ENABLED(CONFIG_ARM64_CNP) &&
640 		cpus_have_const_cap(ARM64_HAS_CNP);
641 }
642 
system_supports_address_auth(void)643 static inline bool system_supports_address_auth(void)
644 {
645 	return IS_ENABLED(CONFIG_ARM64_PTR_AUTH) &&
646 		(cpus_have_const_cap(ARM64_HAS_ADDRESS_AUTH_ARCH) ||
647 		 cpus_have_const_cap(ARM64_HAS_ADDRESS_AUTH_IMP_DEF));
648 }
649 
system_supports_generic_auth(void)650 static inline bool system_supports_generic_auth(void)
651 {
652 	return IS_ENABLED(CONFIG_ARM64_PTR_AUTH) &&
653 		(cpus_have_const_cap(ARM64_HAS_GENERIC_AUTH_ARCH) ||
654 		 cpus_have_const_cap(ARM64_HAS_GENERIC_AUTH_IMP_DEF));
655 }
656 
system_uses_irq_prio_masking(void)657 static __always_inline bool system_uses_irq_prio_masking(void)
658 {
659 	return IS_ENABLED(CONFIG_ARM64_PSEUDO_NMI) &&
660 	       cpus_have_const_cap(ARM64_HAS_IRQ_PRIO_MASKING);
661 }
662 
system_has_prio_mask_debugging(void)663 static inline bool system_has_prio_mask_debugging(void)
664 {
665 	return IS_ENABLED(CONFIG_ARM64_DEBUG_PRIORITY_MASKING) &&
666 	       system_uses_irq_prio_masking();
667 }
668 
669 #define ARM64_BP_HARDEN_UNKNOWN		-1
670 #define ARM64_BP_HARDEN_WA_NEEDED	0
671 #define ARM64_BP_HARDEN_NOT_REQUIRED	1
672 
673 int get_spectre_v2_workaround_state(void);
674 
675 #define ARM64_SSBD_UNKNOWN		-1
676 #define ARM64_SSBD_FORCE_DISABLE	0
677 #define ARM64_SSBD_KERNEL		1
678 #define ARM64_SSBD_FORCE_ENABLE		2
679 #define ARM64_SSBD_MITIGATED		3
680 
arm64_get_ssbd_state(void)681 static inline int arm64_get_ssbd_state(void)
682 {
683 #ifdef CONFIG_ARM64_SSBD
684 	extern int ssbd_state;
685 	return ssbd_state;
686 #else
687 	return ARM64_SSBD_UNKNOWN;
688 #endif
689 }
690 
691 void arm64_set_ssbd_mitigation(bool state);
692 
693 /* Watch out, ordering is important here. */
694 enum mitigation_state {
695 	SPECTRE_UNAFFECTED,
696 	SPECTRE_MITIGATED,
697 	SPECTRE_VULNERABLE,
698 };
699 
700 enum mitigation_state arm64_get_spectre_bhb_state(void);
701 bool is_spectre_bhb_affected(const struct arm64_cpu_capabilities *entry, int scope);
702 u8 spectre_bhb_loop_affected(int scope);
703 void spectre_bhb_enable_mitigation(const struct arm64_cpu_capabilities *__unused);
704 
705 extern int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);
706 
id_aa64mmfr0_parange_to_phys_shift(int parange)707 static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange)
708 {
709 	switch (parange) {
710 	case 0: return 32;
711 	case 1: return 36;
712 	case 2: return 40;
713 	case 3: return 42;
714 	case 4: return 44;
715 	case 5: return 48;
716 	case 6: return 52;
717 	/*
718 	 * A future PE could use a value unknown to the kernel.
719 	 * However, by the "D10.1.4 Principles of the ID scheme
720 	 * for fields in ID registers", ARM DDI 0487C.a, any new
721 	 * value is guaranteed to be higher than what we know already.
722 	 * As a safe limit, we return the limit supported by the kernel.
723 	 */
724 	default: return CONFIG_ARM64_PA_BITS;
725 	}
726 }
727 
728 #ifdef CONFIG_ARM64_AMU_EXTN
729 /* Check whether the cpu supports the Activity Monitors Unit (AMU) */
730 extern bool cpu_has_amu_feat(int cpu);
731 #endif
732 
733 #endif /* __ASSEMBLY__ */
734 
735 #endif
736