1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2015 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #ifndef __ARM_KVM_HYP_H__
8 #define __ARM_KVM_HYP_H__
9
10 #include <linux/compiler.h>
11 #include <linux/kvm_host.h>
12 #include <asm/cp15.h>
13 #include <asm/vfp.h>
14
15 #define __hyp_text __section(.hyp.text) notrace
16
17 #define __ACCESS_VFP(CRn) \
18 "mrc", "mcr", __stringify(p10, 7, %0, CRn, cr0, 0), u32
19
20 #define write_special(v, r) \
21 asm volatile("msr " __stringify(r) ", %0" : : "r" (v))
22 #define read_special(r) ({ \
23 u32 __val; \
24 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
25 __val; \
26 })
27
28 #define TTBR0 __ACCESS_CP15_64(0, c2)
29 #define TTBR1 __ACCESS_CP15_64(1, c2)
30 #define VTTBR __ACCESS_CP15_64(6, c2)
31 #define PAR __ACCESS_CP15_64(0, c7)
32 #define CNTP_CVAL __ACCESS_CP15_64(2, c14)
33 #define CNTV_CVAL __ACCESS_CP15_64(3, c14)
34 #define CNTVOFF __ACCESS_CP15_64(4, c14)
35
36 #define MIDR __ACCESS_CP15(c0, 0, c0, 0)
37 #define CSSELR __ACCESS_CP15(c0, 2, c0, 0)
38 #define VPIDR __ACCESS_CP15(c0, 4, c0, 0)
39 #define VMPIDR __ACCESS_CP15(c0, 4, c0, 5)
40 #define SCTLR __ACCESS_CP15(c1, 0, c0, 0)
41 #define CPACR __ACCESS_CP15(c1, 0, c0, 2)
42 #define HCR __ACCESS_CP15(c1, 4, c1, 0)
43 #define HDCR __ACCESS_CP15(c1, 4, c1, 1)
44 #define HCPTR __ACCESS_CP15(c1, 4, c1, 2)
45 #define HSTR __ACCESS_CP15(c1, 4, c1, 3)
46 #define TTBCR __ACCESS_CP15(c2, 0, c0, 2)
47 #define HTCR __ACCESS_CP15(c2, 4, c0, 2)
48 #define VTCR __ACCESS_CP15(c2, 4, c1, 2)
49 #define DACR __ACCESS_CP15(c3, 0, c0, 0)
50 #define DFSR __ACCESS_CP15(c5, 0, c0, 0)
51 #define IFSR __ACCESS_CP15(c5, 0, c0, 1)
52 #define ADFSR __ACCESS_CP15(c5, 0, c1, 0)
53 #define AIFSR __ACCESS_CP15(c5, 0, c1, 1)
54 #define HSR __ACCESS_CP15(c5, 4, c2, 0)
55 #define DFAR __ACCESS_CP15(c6, 0, c0, 0)
56 #define IFAR __ACCESS_CP15(c6, 0, c0, 2)
57 #define HDFAR __ACCESS_CP15(c6, 4, c0, 0)
58 #define HIFAR __ACCESS_CP15(c6, 4, c0, 2)
59 #define HPFAR __ACCESS_CP15(c6, 4, c0, 4)
60 #define ICIALLUIS __ACCESS_CP15(c7, 0, c1, 0)
61 #define BPIALLIS __ACCESS_CP15(c7, 0, c1, 6)
62 #define ICIMVAU __ACCESS_CP15(c7, 0, c5, 1)
63 #define ATS1CPR __ACCESS_CP15(c7, 0, c8, 0)
64 #define TLBIALLIS __ACCESS_CP15(c8, 0, c3, 0)
65 #define TLBIALL __ACCESS_CP15(c8, 0, c7, 0)
66 #define TLBIALLNSNHIS __ACCESS_CP15(c8, 4, c3, 4)
67 #define PRRR __ACCESS_CP15(c10, 0, c2, 0)
68 #define NMRR __ACCESS_CP15(c10, 0, c2, 1)
69 #define AMAIR0 __ACCESS_CP15(c10, 0, c3, 0)
70 #define AMAIR1 __ACCESS_CP15(c10, 0, c3, 1)
71 #define VBAR __ACCESS_CP15(c12, 0, c0, 0)
72 #define CID __ACCESS_CP15(c13, 0, c0, 1)
73 #define TID_URW __ACCESS_CP15(c13, 0, c0, 2)
74 #define TID_URO __ACCESS_CP15(c13, 0, c0, 3)
75 #define TID_PRIV __ACCESS_CP15(c13, 0, c0, 4)
76 #define HTPIDR __ACCESS_CP15(c13, 4, c0, 2)
77 #define CNTKCTL __ACCESS_CP15(c14, 0, c1, 0)
78 #define CNTP_CTL __ACCESS_CP15(c14, 0, c2, 1)
79 #define CNTV_CTL __ACCESS_CP15(c14, 0, c3, 1)
80 #define CNTHCTL __ACCESS_CP15(c14, 4, c1, 0)
81
82 #define VFP_FPEXC __ACCESS_VFP(FPEXC)
83
84 /* AArch64 compatibility macros, only for the timer so far */
85 #define read_sysreg_el0(r) read_sysreg(r##_EL0)
86 #define write_sysreg_el0(v, r) write_sysreg(v, r##_EL0)
87
88 #define SYS_CNTP_CTL_EL0 CNTP_CTL
89 #define SYS_CNTP_CVAL_EL0 CNTP_CVAL
90 #define SYS_CNTV_CTL_EL0 CNTV_CTL
91 #define SYS_CNTV_CVAL_EL0 CNTV_CVAL
92
93 #define cntvoff_el2 CNTVOFF
94 #define cnthctl_el2 CNTHCTL
95
96 void __timer_enable_traps(struct kvm_vcpu *vcpu);
97 void __timer_disable_traps(struct kvm_vcpu *vcpu);
98
99 void __vgic_v2_save_state(struct kvm_vcpu *vcpu);
100 void __vgic_v2_restore_state(struct kvm_vcpu *vcpu);
101
102 void __sysreg_save_state(struct kvm_cpu_context *ctxt);
103 void __sysreg_restore_state(struct kvm_cpu_context *ctxt);
104
105 void __vgic_v3_save_state(struct kvm_vcpu *vcpu);
106 void __vgic_v3_restore_state(struct kvm_vcpu *vcpu);
107 void __vgic_v3_activate_traps(struct kvm_vcpu *vcpu);
108 void __vgic_v3_deactivate_traps(struct kvm_vcpu *vcpu);
109 void __vgic_v3_save_aprs(struct kvm_vcpu *vcpu);
110 void __vgic_v3_restore_aprs(struct kvm_vcpu *vcpu);
111
112 asmlinkage void __vfp_save_state(struct vfp_hard_struct *vfp);
113 asmlinkage void __vfp_restore_state(struct vfp_hard_struct *vfp);
__vfp_enabled(void)114 static inline bool __vfp_enabled(void)
115 {
116 return !(read_sysreg(HCPTR) & (HCPTR_TCP(11) | HCPTR_TCP(10)));
117 }
118
119 void __hyp_text __banked_save_state(struct kvm_cpu_context *ctxt);
120 void __hyp_text __banked_restore_state(struct kvm_cpu_context *ctxt);
121
122 asmlinkage int __guest_enter(struct kvm_vcpu *vcpu,
123 struct kvm_cpu_context *host);
124 asmlinkage int __hyp_do_panic(const char *, int, u32);
125
126 #endif /* __ARM_KVM_HYP_H__ */
127