1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_CLOCKSOURCE_DATA 7 select ARCH_HAS_BINFMT_FLAT 8 select ARCH_HAS_CPU_FINALIZE_INIT if MMU 9 select ARCH_HAS_DEBUG_VIRTUAL if MMU 10 select ARCH_HAS_DEVMEM_IS_ALLOWED 11 select ARCH_HAS_DMA_COHERENT_TO_PFN if SWIOTLB 12 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 13 select ARCH_HAS_ELF_RANDOMIZE 14 select ARCH_HAS_FORTIFY_SOURCE 15 select ARCH_HAS_KEEPINITRD 16 select ARCH_HAS_KCOV 17 select ARCH_HAS_MEMBARRIER_SYNC_CORE 18 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 19 select ARCH_HAS_PHYS_TO_DMA 20 select ARCH_HAS_SETUP_DMA_OPS 21 select ARCH_HAS_SET_MEMORY 22 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 23 select ARCH_HAS_STRICT_MODULE_RWX if MMU 24 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 25 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 26 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 27 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 28 select ARCH_HAVE_CUSTOM_GPIO_H 29 select ARCH_HAS_GCOV_PROFILE_ALL 30 select ARCH_KEEP_MEMBLOCK 31 select ARCH_MIGHT_HAVE_PC_PARPORT 32 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 35 select ARCH_SUPPORTS_ATOMIC_RMW 36 select ARCH_USE_BUILTIN_BSWAP 37 select ARCH_USE_CMPXCHG_LOCKREF 38 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 39 select ARCH_WANT_IPC_PARSE_VERSION 40 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 41 select BUILDTIME_EXTABLE_SORT if MMU 42 select CLONE_BACKWARDS 43 select CPU_PM if SUSPEND || CPU_IDLE 44 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 45 select DMA_DECLARE_COHERENT 46 select DMA_REMAP if MMU 47 select EDAC_SUPPORT 48 select EDAC_ATOMIC_SCRUB 49 select GENERIC_ALLOCATOR 50 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 51 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 52 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 53 select GENERIC_CPU_AUTOPROBE 54 select GENERIC_EARLY_IOREMAP 55 select GENERIC_IDLE_POLL_SETUP 56 select GENERIC_IRQ_PROBE 57 select GENERIC_IRQ_SHOW 58 select GENERIC_IRQ_SHOW_LEVEL 59 select GENERIC_PCI_IOMAP 60 select GENERIC_SCHED_CLOCK 61 select GENERIC_SMP_IDLE_THREAD 62 select GENERIC_STRNCPY_FROM_USER 63 select GENERIC_STRNLEN_USER 64 select HANDLE_DOMAIN_IRQ 65 select HARDIRQS_SW_RESEND 66 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 67 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 68 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 69 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 70 select HAVE_ARCH_MMAP_RND_BITS if MMU 71 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 72 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 73 select HAVE_ARCH_TRACEHOOK 74 select HAVE_ARM_SMCCC if CPU_V7 75 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 76 select HAVE_CONTEXT_TRACKING 77 select HAVE_COPY_THREAD_TLS 78 select HAVE_C_RECORDMCOUNT 79 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 80 select HAVE_DMA_CONTIGUOUS if MMU 81 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 82 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 83 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 84 select HAVE_EXIT_THREAD 85 select HAVE_FAST_GUP if ARM_LPAE 86 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 87 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 88 select HAVE_FUNCTION_TRACER if !XIP_KERNEL && (CC_IS_GCC || CLANG_VERSION >= 100000) 89 select HAVE_FUTEX_CMPXCHG if FUTEX 90 select HAVE_GCC_PLUGINS 91 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 92 select HAVE_IDE if PCI || ISA || PCMCIA 93 select HAVE_IRQ_TIME_ACCOUNTING 94 select HAVE_KERNEL_GZIP 95 select HAVE_KERNEL_LZ4 96 select HAVE_KERNEL_LZMA 97 select HAVE_KERNEL_LZO 98 select HAVE_KERNEL_XZ 99 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 100 select HAVE_KRETPROBES if HAVE_KPROBES 101 select HAVE_MOD_ARCH_SPECIFIC 102 select HAVE_NMI 103 select HAVE_OPROFILE if HAVE_PERF_EVENTS 104 select HAVE_OPTPROBES if !THUMB2_KERNEL 105 select HAVE_PERF_EVENTS 106 select HAVE_PERF_REGS 107 select HAVE_PERF_USER_STACK_DUMP 108 select HAVE_RCU_TABLE_FREE if SMP && ARM_LPAE 109 select HAVE_REGS_AND_STACK_ACCESS_API 110 select HAVE_RSEQ 111 select HAVE_STACKPROTECTOR 112 select HAVE_SYSCALL_TRACEPOINTS 113 select HAVE_UID16 114 select HAVE_VIRT_CPU_ACCOUNTING_GEN 115 select IRQ_FORCED_THREADING 116 select MODULES_USE_ELF_REL 117 select NEED_DMA_MAP_STATE 118 select OF_EARLY_FLATTREE if OF 119 select OLD_SIGACTION 120 select OLD_SIGSUSPEND3 121 select PCI_SYSCALL if PCI 122 select PERF_USE_VMALLOC 123 select RTC_LIB 124 select SYS_SUPPORTS_APM_EMULATION 125 # Above selects are sorted alphabetically; please add new ones 126 # according to that. Thanks. 127 help 128 The ARM series is a line of low-power-consumption RISC chip designs 129 licensed by ARM Ltd and targeted at embedded applications and 130 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 131 manufactured, but legacy ARM-based PC hardware remains popular in 132 Europe. There is an ARM Linux project with a web page at 133 <http://www.arm.linux.org.uk/>. 134 135config ARM_HAS_SG_CHAIN 136 bool 137 138config ARM_DMA_USE_IOMMU 139 bool 140 select ARM_HAS_SG_CHAIN 141 select NEED_SG_DMA_LENGTH 142 143if ARM_DMA_USE_IOMMU 144 145config ARM_DMA_IOMMU_ALIGNMENT 146 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 147 range 4 9 148 default 8 149 help 150 DMA mapping framework by default aligns all buffers to the smallest 151 PAGE_SIZE order which is greater than or equal to the requested buffer 152 size. This works well for buffers up to a few hundreds kilobytes, but 153 for larger buffers it just a waste of address space. Drivers which has 154 relatively small addressing window (like 64Mib) might run out of 155 virtual space with just a few allocations. 156 157 With this parameter you can specify the maximum PAGE_SIZE order for 158 DMA IOMMU buffers. Larger buffers will be aligned only to this 159 specified order. The order is expressed as a power of two multiplied 160 by the PAGE_SIZE. 161 162endif 163 164config SYS_SUPPORTS_APM_EMULATION 165 bool 166 167config HAVE_TCM 168 bool 169 select GENERIC_ALLOCATOR 170 171config HAVE_PROC_CPU 172 bool 173 174config NO_IOPORT_MAP 175 bool 176 177config SBUS 178 bool 179 180config STACKTRACE_SUPPORT 181 bool 182 default y 183 184config LOCKDEP_SUPPORT 185 bool 186 default y 187 188config TRACE_IRQFLAGS_SUPPORT 189 bool 190 default !CPU_V7M 191 192config ARCH_HAS_ILOG2_U32 193 bool 194 195config ARCH_HAS_ILOG2_U64 196 bool 197 198config ARCH_HAS_BANDGAP 199 bool 200 201config FIX_EARLYCON_MEM 202 def_bool y if MMU 203 204config GENERIC_HWEIGHT 205 bool 206 default y 207 208config GENERIC_CALIBRATE_DELAY 209 bool 210 default y 211 212config ARCH_MAY_HAVE_PC_FDC 213 bool 214 215config ZONE_DMA 216 bool 217 218config ARCH_SUPPORTS_UPROBES 219 def_bool y 220 221config ARCH_HAS_DMA_SET_COHERENT_MASK 222 bool 223 224config GENERIC_ISA_DMA 225 bool 226 227config FIQ 228 bool 229 230config NEED_RET_TO_USER 231 bool 232 233config ARCH_MTD_XIP 234 bool 235 236config ARM_PATCH_PHYS_VIRT 237 bool "Patch physical to virtual translations at runtime" if EMBEDDED 238 default y 239 depends on !XIP_KERNEL && MMU 240 help 241 Patch phys-to-virt and virt-to-phys translation functions at 242 boot and module load time according to the position of the 243 kernel in system memory. 244 245 This can only be used with non-XIP MMU kernels where the base 246 of physical memory is at a 16MB boundary. 247 248 Only disable this option if you know that you do not require 249 this feature (eg, building a kernel for a single machine) and 250 you need to shrink the kernel to the minimal size. 251 252config NEED_MACH_IO_H 253 bool 254 help 255 Select this when mach/io.h is required to provide special 256 definitions for this platform. The need for mach/io.h should 257 be avoided when possible. 258 259config NEED_MACH_MEMORY_H 260 bool 261 help 262 Select this when mach/memory.h is required to provide special 263 definitions for this platform. The need for mach/memory.h should 264 be avoided when possible. 265 266config PHYS_OFFSET 267 hex "Physical address of main memory" if MMU 268 depends on !ARM_PATCH_PHYS_VIRT 269 default DRAM_BASE if !MMU 270 default 0x00000000 if ARCH_EBSA110 || \ 271 ARCH_FOOTBRIDGE || \ 272 ARCH_INTEGRATOR || \ 273 ARCH_REALVIEW 274 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 275 default 0x20000000 if ARCH_S5PV210 276 default 0xc0000000 if ARCH_SA1100 277 help 278 Please provide the physical address corresponding to the 279 location of main memory in your system. 280 281config GENERIC_BUG 282 def_bool y 283 depends on BUG 284 285config PGTABLE_LEVELS 286 int 287 default 3 if ARM_LPAE 288 default 2 289 290menu "System Type" 291 292config MMU 293 bool "MMU-based Paged Memory Management Support" 294 default y 295 help 296 Select if you want MMU-based virtualised addressing space 297 support by paged memory management. If unsure, say 'Y'. 298 299config ARCH_MMAP_RND_BITS_MIN 300 default 8 301 302config ARCH_MMAP_RND_BITS_MAX 303 default 14 if PAGE_OFFSET=0x40000000 304 default 15 if PAGE_OFFSET=0x80000000 305 default 16 306 307# 308# The "ARM system type" choice list is ordered alphabetically by option 309# text. Please add new entries in the option alphabetic order. 310# 311choice 312 prompt "ARM system type" 313 default ARM_SINGLE_ARMV7M if !MMU 314 default ARCH_MULTIPLATFORM if MMU 315 316config ARCH_MULTIPLATFORM 317 bool "Allow multiple platforms to be selected" 318 depends on MMU 319 select ARM_HAS_SG_CHAIN 320 select ARM_PATCH_PHYS_VIRT 321 select AUTO_ZRELADDR 322 select TIMER_OF 323 select COMMON_CLK 324 select GENERIC_CLOCKEVENTS 325 select GENERIC_IRQ_MULTI_HANDLER 326 select HAVE_PCI 327 select PCI_DOMAINS_GENERIC if PCI 328 select SPARSE_IRQ 329 select USE_OF 330 331config ARM_SINGLE_ARMV7M 332 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 333 depends on !MMU 334 select ARM_NVIC 335 select AUTO_ZRELADDR 336 select TIMER_OF 337 select COMMON_CLK 338 select CPU_V7M 339 select GENERIC_CLOCKEVENTS 340 select NO_IOPORT_MAP 341 select SPARSE_IRQ 342 select USE_OF 343 344config ARCH_EBSA110 345 bool "EBSA-110" 346 select ARCH_USES_GETTIMEOFFSET 347 select CPU_SA110 348 select ISA 349 select NEED_MACH_IO_H 350 select NEED_MACH_MEMORY_H 351 select NO_IOPORT_MAP 352 help 353 This is an evaluation board for the StrongARM processor available 354 from Digital. It has limited hardware on-board, including an 355 Ethernet interface, two PCMCIA sockets, two serial ports and a 356 parallel port. 357 358config ARCH_EP93XX 359 bool "EP93xx-based" 360 select ARCH_SPARSEMEM_ENABLE 361 select ARM_AMBA 362 imply ARM_PATCH_PHYS_VIRT 363 select ARM_VIC 364 select AUTO_ZRELADDR 365 select CLKDEV_LOOKUP 366 select CLKSRC_MMIO 367 select CPU_ARM920T 368 select GENERIC_CLOCKEVENTS 369 select GPIOLIB 370 help 371 This enables support for the Cirrus EP93xx series of CPUs. 372 373config ARCH_FOOTBRIDGE 374 bool "FootBridge" 375 select CPU_SA110 376 select FOOTBRIDGE 377 select GENERIC_CLOCKEVENTS 378 select HAVE_IDE 379 select NEED_MACH_IO_H if !MMU 380 select NEED_MACH_MEMORY_H 381 help 382 Support for systems based on the DC21285 companion chip 383 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 384 385config ARCH_IOP32X 386 bool "IOP32x-based" 387 depends on MMU 388 select CPU_XSCALE 389 select GPIO_IOP 390 select GPIOLIB 391 select NEED_RET_TO_USER 392 select FORCE_PCI 393 select PLAT_IOP 394 help 395 Support for Intel's 80219 and IOP32X (XScale) family of 396 processors. 397 398config ARCH_IXP4XX 399 bool "IXP4xx-based" 400 depends on MMU 401 select ARCH_HAS_DMA_SET_COHERENT_MASK 402 select ARCH_SUPPORTS_BIG_ENDIAN 403 select CPU_XSCALE 404 select DMABOUNCE if PCI 405 select GENERIC_CLOCKEVENTS 406 select GENERIC_IRQ_MULTI_HANDLER 407 select GPIO_IXP4XX 408 select GPIOLIB 409 select HAVE_PCI 410 select IXP4XX_IRQ 411 select IXP4XX_TIMER 412 select NEED_MACH_IO_H 413 select USB_EHCI_BIG_ENDIAN_DESC 414 select USB_EHCI_BIG_ENDIAN_MMIO 415 help 416 Support for Intel's IXP4XX (XScale) family of processors. 417 418config ARCH_DOVE 419 bool "Marvell Dove" 420 select CPU_PJ4 421 select GENERIC_CLOCKEVENTS 422 select GENERIC_IRQ_MULTI_HANDLER 423 select GPIOLIB 424 select HAVE_PCI 425 select MVEBU_MBUS 426 select PINCTRL 427 select PINCTRL_DOVE 428 select PLAT_ORION_LEGACY 429 select SPARSE_IRQ 430 select PM_GENERIC_DOMAINS if PM 431 help 432 Support for the Marvell Dove SoC 88AP510 433 434config ARCH_PXA 435 bool "PXA2xx/PXA3xx-based" 436 depends on MMU 437 select ARCH_MTD_XIP 438 select ARM_CPU_SUSPEND if PM 439 select AUTO_ZRELADDR 440 select COMMON_CLK 441 select CLKDEV_LOOKUP 442 select CLKSRC_PXA 443 select CLKSRC_MMIO 444 select TIMER_OF 445 select CPU_XSCALE if !CPU_XSC3 446 select GENERIC_CLOCKEVENTS 447 select GENERIC_IRQ_MULTI_HANDLER 448 select GPIO_PXA 449 select GPIOLIB 450 select HAVE_IDE 451 select IRQ_DOMAIN 452 select PLAT_PXA 453 select SPARSE_IRQ 454 help 455 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 456 457config ARCH_RPC 458 bool "RiscPC" 459 depends on MMU 460 select ARCH_ACORN 461 select ARCH_MAY_HAVE_PC_FDC 462 select ARCH_SPARSEMEM_ENABLE 463 select ARM_HAS_SG_CHAIN 464 select CPU_SA110 465 select FIQ 466 select HAVE_IDE 467 select HAVE_PATA_PLATFORM 468 select ISA_DMA_API 469 select NEED_MACH_IO_H 470 select NEED_MACH_MEMORY_H 471 select NO_IOPORT_MAP 472 help 473 On the Acorn Risc-PC, Linux can support the internal IDE disk and 474 CD-ROM interface, serial and parallel port, and the floppy drive. 475 476config ARCH_SA1100 477 bool "SA1100-based" 478 select ARCH_MTD_XIP 479 select ARCH_SPARSEMEM_ENABLE 480 select CLKDEV_LOOKUP 481 select CLKSRC_MMIO 482 select CLKSRC_PXA 483 select TIMER_OF if OF 484 select COMMON_CLK 485 select CPU_FREQ 486 select CPU_SA1100 487 select GENERIC_CLOCKEVENTS 488 select GENERIC_IRQ_MULTI_HANDLER 489 select GPIOLIB 490 select HAVE_IDE 491 select IRQ_DOMAIN 492 select ISA 493 select NEED_MACH_MEMORY_H 494 select SPARSE_IRQ 495 help 496 Support for StrongARM 11x0 based boards. 497 498config ARCH_S3C24XX 499 bool "Samsung S3C24XX SoCs" 500 select ATAGS 501 select CLKDEV_LOOKUP 502 select CLKSRC_SAMSUNG_PWM 503 select GENERIC_CLOCKEVENTS 504 select GPIO_SAMSUNG 505 select GPIOLIB 506 select GENERIC_IRQ_MULTI_HANDLER 507 select HAVE_S3C2410_I2C if I2C 508 select HAVE_S3C2410_WATCHDOG if WATCHDOG 509 select HAVE_S3C_RTC if RTC_CLASS 510 select NEED_MACH_IO_H 511 select S3C2410_WATCHDOG 512 select SAMSUNG_ATAGS 513 select USE_OF 514 select WATCHDOG 515 help 516 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 517 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 518 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 519 Samsung SMDK2410 development board (and derivatives). 520 521config ARCH_OMAP1 522 bool "TI OMAP1" 523 depends on MMU 524 select ARCH_OMAP 525 select CLKDEV_LOOKUP 526 select CLKSRC_MMIO 527 select GENERIC_CLOCKEVENTS 528 select GENERIC_IRQ_CHIP 529 select GENERIC_IRQ_MULTI_HANDLER 530 select GPIOLIB 531 select HAVE_IDE 532 select IRQ_DOMAIN 533 select NEED_MACH_IO_H if PCCARD 534 select NEED_MACH_MEMORY_H 535 select SPARSE_IRQ 536 help 537 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 538 539endchoice 540 541menu "Multiple platform selection" 542 depends on ARCH_MULTIPLATFORM 543 544comment "CPU Core family selection" 545 546config ARCH_MULTI_V4 547 bool "ARMv4 based platforms (FA526)" 548 depends on !ARCH_MULTI_V6_V7 549 select ARCH_MULTI_V4_V5 550 select CPU_FA526 551 552config ARCH_MULTI_V4T 553 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 554 depends on !ARCH_MULTI_V6_V7 555 select ARCH_MULTI_V4_V5 556 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 557 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 558 CPU_ARM925T || CPU_ARM940T) 559 560config ARCH_MULTI_V5 561 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 562 depends on !ARCH_MULTI_V6_V7 563 select ARCH_MULTI_V4_V5 564 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 565 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 566 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 567 568config ARCH_MULTI_V4_V5 569 bool 570 571config ARCH_MULTI_V6 572 bool "ARMv6 based platforms (ARM11)" 573 select ARCH_MULTI_V6_V7 574 select CPU_V6K 575 576config ARCH_MULTI_V7 577 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 578 default y 579 select ARCH_MULTI_V6_V7 580 select CPU_V7 581 select HAVE_SMP 582 583config ARCH_MULTI_V6_V7 584 bool 585 select MIGHT_HAVE_CACHE_L2X0 586 587config ARCH_MULTI_CPU_AUTO 588 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 589 select ARCH_MULTI_V5 590 591endmenu 592 593config ARCH_VIRT 594 bool "Dummy Virtual Machine" 595 depends on ARCH_MULTI_V7 596 select ARM_AMBA 597 select ARM_GIC 598 select ARM_GIC_V2M if PCI 599 select ARM_GIC_V3 600 select ARM_GIC_V3_ITS if PCI 601 select ARM_PSCI 602 select HAVE_ARM_ARCH_TIMER 603 select ARCH_SUPPORTS_BIG_ENDIAN 604 605# 606# This is sorted alphabetically by mach-* pathname. However, plat-* 607# Kconfigs may be included either alphabetically (according to the 608# plat- suffix) or along side the corresponding mach-* source. 609# 610source "arch/arm/mach-actions/Kconfig" 611 612source "arch/arm/mach-alpine/Kconfig" 613 614source "arch/arm/mach-artpec/Kconfig" 615 616source "arch/arm/mach-asm9260/Kconfig" 617 618source "arch/arm/mach-aspeed/Kconfig" 619 620source "arch/arm/mach-at91/Kconfig" 621 622source "arch/arm/mach-axxia/Kconfig" 623 624source "arch/arm/mach-bcm/Kconfig" 625 626source "arch/arm/mach-berlin/Kconfig" 627 628source "arch/arm/mach-clps711x/Kconfig" 629 630source "arch/arm/mach-cns3xxx/Kconfig" 631 632source "arch/arm/mach-davinci/Kconfig" 633 634source "arch/arm/mach-digicolor/Kconfig" 635 636source "arch/arm/mach-dove/Kconfig" 637 638source "arch/arm/mach-ep93xx/Kconfig" 639 640source "arch/arm/mach-exynos/Kconfig" 641source "arch/arm/plat-samsung/Kconfig" 642 643source "arch/arm/mach-footbridge/Kconfig" 644 645source "arch/arm/mach-gemini/Kconfig" 646 647source "arch/arm/mach-highbank/Kconfig" 648 649source "arch/arm/mach-hisi/Kconfig" 650 651source "arch/arm/mach-imx/Kconfig" 652 653source "arch/arm/mach-integrator/Kconfig" 654 655source "arch/arm/mach-iop32x/Kconfig" 656 657source "arch/arm/mach-ixp4xx/Kconfig" 658 659source "arch/arm/mach-keystone/Kconfig" 660 661source "arch/arm/mach-lpc32xx/Kconfig" 662 663source "arch/arm/mach-mediatek/Kconfig" 664 665source "arch/arm/mach-meson/Kconfig" 666 667source "arch/arm/mach-milbeaut/Kconfig" 668 669source "arch/arm/mach-mmp/Kconfig" 670 671source "arch/arm/mach-moxart/Kconfig" 672 673source "arch/arm/mach-mv78xx0/Kconfig" 674 675source "arch/arm/mach-mvebu/Kconfig" 676 677source "arch/arm/mach-mxs/Kconfig" 678 679source "arch/arm/mach-nomadik/Kconfig" 680 681source "arch/arm/mach-npcm/Kconfig" 682 683source "arch/arm/mach-nspire/Kconfig" 684 685source "arch/arm/plat-omap/Kconfig" 686 687source "arch/arm/mach-omap1/Kconfig" 688 689source "arch/arm/mach-omap2/Kconfig" 690 691source "arch/arm/mach-orion5x/Kconfig" 692 693source "arch/arm/mach-oxnas/Kconfig" 694 695source "arch/arm/mach-picoxcell/Kconfig" 696 697source "arch/arm/mach-prima2/Kconfig" 698 699source "arch/arm/mach-pxa/Kconfig" 700source "arch/arm/plat-pxa/Kconfig" 701 702source "arch/arm/mach-qcom/Kconfig" 703 704source "arch/arm/mach-rda/Kconfig" 705 706source "arch/arm/mach-realview/Kconfig" 707 708source "arch/arm/mach-rockchip/Kconfig" 709 710source "arch/arm/mach-s3c24xx/Kconfig" 711 712source "arch/arm/mach-s3c64xx/Kconfig" 713 714source "arch/arm/mach-s5pv210/Kconfig" 715 716source "arch/arm/mach-sa1100/Kconfig" 717 718source "arch/arm/mach-shmobile/Kconfig" 719 720source "arch/arm/mach-socfpga/Kconfig" 721 722source "arch/arm/mach-spear/Kconfig" 723 724source "arch/arm/mach-sti/Kconfig" 725 726source "arch/arm/mach-stm32/Kconfig" 727 728source "arch/arm/mach-sunxi/Kconfig" 729 730source "arch/arm/mach-tango/Kconfig" 731 732source "arch/arm/mach-tegra/Kconfig" 733 734source "arch/arm/mach-u300/Kconfig" 735 736source "arch/arm/mach-uniphier/Kconfig" 737 738source "arch/arm/mach-ux500/Kconfig" 739 740source "arch/arm/mach-versatile/Kconfig" 741 742source "arch/arm/mach-vexpress/Kconfig" 743source "arch/arm/plat-versatile/Kconfig" 744 745source "arch/arm/mach-vt8500/Kconfig" 746 747source "arch/arm/mach-zx/Kconfig" 748 749source "arch/arm/mach-zynq/Kconfig" 750 751# ARMv7-M architecture 752config ARCH_EFM32 753 bool "Energy Micro efm32" 754 depends on ARM_SINGLE_ARMV7M 755 select GPIOLIB 756 help 757 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 758 processors. 759 760config ARCH_LPC18XX 761 bool "NXP LPC18xx/LPC43xx" 762 depends on ARM_SINGLE_ARMV7M 763 select ARCH_HAS_RESET_CONTROLLER 764 select ARM_AMBA 765 select CLKSRC_LPC32XX 766 select PINCTRL 767 help 768 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 769 high performance microcontrollers. 770 771config ARCH_MPS2 772 bool "ARM MPS2 platform" 773 depends on ARM_SINGLE_ARMV7M 774 select ARM_AMBA 775 select CLKSRC_MPS2 776 help 777 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 778 with a range of available cores like Cortex-M3/M4/M7. 779 780 Please, note that depends which Application Note is used memory map 781 for the platform may vary, so adjustment of RAM base might be needed. 782 783# Definitions to make life easier 784config ARCH_ACORN 785 bool 786 787config PLAT_IOP 788 bool 789 select GENERIC_CLOCKEVENTS 790 791config PLAT_ORION 792 bool 793 select CLKSRC_MMIO 794 select COMMON_CLK 795 select GENERIC_IRQ_CHIP 796 select IRQ_DOMAIN 797 798config PLAT_ORION_LEGACY 799 bool 800 select PLAT_ORION 801 802config PLAT_PXA 803 bool 804 805config PLAT_VERSATILE 806 bool 807 808source "arch/arm/mm/Kconfig" 809 810config IWMMXT 811 bool "Enable iWMMXt support" 812 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 813 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 814 help 815 Enable support for iWMMXt context switching at run time if 816 running on a CPU that supports it. 817 818if !MMU 819source "arch/arm/Kconfig-nommu" 820endif 821 822config PJ4B_ERRATA_4742 823 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 824 depends on CPU_PJ4B && MACH_ARMADA_370 825 default y 826 help 827 When coming out of either a Wait for Interrupt (WFI) or a Wait for 828 Event (WFE) IDLE states, a specific timing sensitivity exists between 829 the retiring WFI/WFE instructions and the newly issued subsequent 830 instructions. This sensitivity can result in a CPU hang scenario. 831 Workaround: 832 The software must insert either a Data Synchronization Barrier (DSB) 833 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 834 instruction 835 836config ARM_ERRATA_326103 837 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 838 depends on CPU_V6 839 help 840 Executing a SWP instruction to read-only memory does not set bit 11 841 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 842 treat the access as a read, preventing a COW from occurring and 843 causing the faulting task to livelock. 844 845config ARM_ERRATA_411920 846 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 847 depends on CPU_V6 || CPU_V6K 848 help 849 Invalidation of the Instruction Cache operation can 850 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 851 It does not affect the MPCore. This option enables the ARM Ltd. 852 recommended workaround. 853 854config ARM_ERRATA_430973 855 bool "ARM errata: Stale prediction on replaced interworking branch" 856 depends on CPU_V7 857 help 858 This option enables the workaround for the 430973 Cortex-A8 859 r1p* erratum. If a code sequence containing an ARM/Thumb 860 interworking branch is replaced with another code sequence at the 861 same virtual address, whether due to self-modifying code or virtual 862 to physical address re-mapping, Cortex-A8 does not recover from the 863 stale interworking branch prediction. This results in Cortex-A8 864 executing the new code sequence in the incorrect ARM or Thumb state. 865 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 866 and also flushes the branch target cache at every context switch. 867 Note that setting specific bits in the ACTLR register may not be 868 available in non-secure mode. 869 870config ARM_ERRATA_458693 871 bool "ARM errata: Processor deadlock when a false hazard is created" 872 depends on CPU_V7 873 depends on !ARCH_MULTIPLATFORM 874 help 875 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 876 erratum. For very specific sequences of memory operations, it is 877 possible for a hazard condition intended for a cache line to instead 878 be incorrectly associated with a different cache line. This false 879 hazard might then cause a processor deadlock. The workaround enables 880 the L1 caching of the NEON accesses and disables the PLD instruction 881 in the ACTLR register. Note that setting specific bits in the ACTLR 882 register may not be available in non-secure mode. 883 884config ARM_ERRATA_460075 885 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 886 depends on CPU_V7 887 depends on !ARCH_MULTIPLATFORM 888 help 889 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 890 erratum. Any asynchronous access to the L2 cache may encounter a 891 situation in which recent store transactions to the L2 cache are lost 892 and overwritten with stale memory contents from external memory. The 893 workaround disables the write-allocate mode for the L2 cache via the 894 ACTLR register. Note that setting specific bits in the ACTLR register 895 may not be available in non-secure mode. 896 897config ARM_ERRATA_742230 898 bool "ARM errata: DMB operation may be faulty" 899 depends on CPU_V7 && SMP 900 depends on !ARCH_MULTIPLATFORM 901 help 902 This option enables the workaround for the 742230 Cortex-A9 903 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 904 between two write operations may not ensure the correct visibility 905 ordering of the two writes. This workaround sets a specific bit in 906 the diagnostic register of the Cortex-A9 which causes the DMB 907 instruction to behave as a DSB, ensuring the correct behaviour of 908 the two writes. 909 910config ARM_ERRATA_742231 911 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 912 depends on CPU_V7 && SMP 913 depends on !ARCH_MULTIPLATFORM 914 help 915 This option enables the workaround for the 742231 Cortex-A9 916 (r2p0..r2p2) erratum. Under certain conditions, specific to the 917 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 918 accessing some data located in the same cache line, may get corrupted 919 data due to bad handling of the address hazard when the line gets 920 replaced from one of the CPUs at the same time as another CPU is 921 accessing it. This workaround sets specific bits in the diagnostic 922 register of the Cortex-A9 which reduces the linefill issuing 923 capabilities of the processor. 924 925config ARM_ERRATA_643719 926 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 927 depends on CPU_V7 && SMP 928 default y 929 help 930 This option enables the workaround for the 643719 Cortex-A9 (prior to 931 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 932 register returns zero when it should return one. The workaround 933 corrects this value, ensuring cache maintenance operations which use 934 it behave as intended and avoiding data corruption. 935 936config ARM_ERRATA_720789 937 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 938 depends on CPU_V7 939 help 940 This option enables the workaround for the 720789 Cortex-A9 (prior to 941 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 942 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 943 As a consequence of this erratum, some TLB entries which should be 944 invalidated are not, resulting in an incoherency in the system page 945 tables. The workaround changes the TLB flushing routines to invalidate 946 entries regardless of the ASID. 947 948config ARM_ERRATA_743622 949 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 950 depends on CPU_V7 951 depends on !ARCH_MULTIPLATFORM 952 help 953 This option enables the workaround for the 743622 Cortex-A9 954 (r2p*) erratum. Under very rare conditions, a faulty 955 optimisation in the Cortex-A9 Store Buffer may lead to data 956 corruption. This workaround sets a specific bit in the diagnostic 957 register of the Cortex-A9 which disables the Store Buffer 958 optimisation, preventing the defect from occurring. This has no 959 visible impact on the overall performance or power consumption of the 960 processor. 961 962config ARM_ERRATA_751472 963 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 964 depends on CPU_V7 965 depends on !ARCH_MULTIPLATFORM 966 help 967 This option enables the workaround for the 751472 Cortex-A9 (prior 968 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 969 completion of a following broadcasted operation if the second 970 operation is received by a CPU before the ICIALLUIS has completed, 971 potentially leading to corrupted entries in the cache or TLB. 972 973config ARM_ERRATA_754322 974 bool "ARM errata: possible faulty MMU translations following an ASID switch" 975 depends on CPU_V7 976 help 977 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 978 r3p*) erratum. A speculative memory access may cause a page table walk 979 which starts prior to an ASID switch but completes afterwards. This 980 can populate the micro-TLB with a stale entry which may be hit with 981 the new ASID. This workaround places two dsb instructions in the mm 982 switching code so that no page table walks can cross the ASID switch. 983 984config ARM_ERRATA_754327 985 bool "ARM errata: no automatic Store Buffer drain" 986 depends on CPU_V7 && SMP 987 help 988 This option enables the workaround for the 754327 Cortex-A9 (prior to 989 r2p0) erratum. The Store Buffer does not have any automatic draining 990 mechanism and therefore a livelock may occur if an external agent 991 continuously polls a memory location waiting to observe an update. 992 This workaround defines cpu_relax() as smp_mb(), preventing correctly 993 written polling loops from denying visibility of updates to memory. 994 995config ARM_ERRATA_364296 996 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 997 depends on CPU_V6 998 help 999 This options enables the workaround for the 364296 ARM1136 1000 r0p2 erratum (possible cache data corruption with 1001 hit-under-miss enabled). It sets the undocumented bit 31 in 1002 the auxiliary control register and the FI bit in the control 1003 register, thus disabling hit-under-miss without putting the 1004 processor into full low interrupt latency mode. ARM11MPCore 1005 is not affected. 1006 1007config ARM_ERRATA_764369 1008 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1009 depends on CPU_V7 && SMP 1010 help 1011 This option enables the workaround for erratum 764369 1012 affecting Cortex-A9 MPCore with two or more processors (all 1013 current revisions). Under certain timing circumstances, a data 1014 cache line maintenance operation by MVA targeting an Inner 1015 Shareable memory region may fail to proceed up to either the 1016 Point of Coherency or to the Point of Unification of the 1017 system. This workaround adds a DSB instruction before the 1018 relevant cache maintenance functions and sets a specific bit 1019 in the diagnostic control register of the SCU. 1020 1021config ARM_ERRATA_775420 1022 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1023 depends on CPU_V7 1024 help 1025 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1026 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1027 operation aborts with MMU exception, it might cause the processor 1028 to deadlock. This workaround puts DSB before executing ISB if 1029 an abort may occur on cache maintenance. 1030 1031config ARM_ERRATA_798181 1032 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1033 depends on CPU_V7 && SMP 1034 help 1035 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1036 adequately shooting down all use of the old entries. This 1037 option enables the Linux kernel workaround for this erratum 1038 which sends an IPI to the CPUs that are running the same ASID 1039 as the one being invalidated. 1040 1041config ARM_ERRATA_773022 1042 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1043 depends on CPU_V7 1044 help 1045 This option enables the workaround for the 773022 Cortex-A15 1046 (up to r0p4) erratum. In certain rare sequences of code, the 1047 loop buffer may deliver incorrect instructions. This 1048 workaround disables the loop buffer to avoid the erratum. 1049 1050config ARM_ERRATA_818325_852422 1051 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1052 depends on CPU_V7 1053 help 1054 This option enables the workaround for: 1055 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1056 instruction might deadlock. Fixed in r0p1. 1057 - Cortex-A12 852422: Execution of a sequence of instructions might 1058 lead to either a data corruption or a CPU deadlock. Not fixed in 1059 any Cortex-A12 cores yet. 1060 This workaround for all both errata involves setting bit[12] of the 1061 Feature Register. This bit disables an optimisation applied to a 1062 sequence of 2 instructions that use opposing condition codes. 1063 1064config ARM_ERRATA_821420 1065 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1066 depends on CPU_V7 1067 help 1068 This option enables the workaround for the 821420 Cortex-A12 1069 (all revs) erratum. In very rare timing conditions, a sequence 1070 of VMOV to Core registers instructions, for which the second 1071 one is in the shadow of a branch or abort, can lead to a 1072 deadlock when the VMOV instructions are issued out-of-order. 1073 1074config ARM_ERRATA_825619 1075 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1076 depends on CPU_V7 1077 help 1078 This option enables the workaround for the 825619 Cortex-A12 1079 (all revs) erratum. Within rare timing constraints, executing a 1080 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1081 and Device/Strongly-Ordered loads and stores might cause deadlock 1082 1083config ARM_ERRATA_857271 1084 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1085 depends on CPU_V7 1086 help 1087 This option enables the workaround for the 857271 Cortex-A12 1088 (all revs) erratum. Under very rare timing conditions, the CPU might 1089 hang. The workaround is expected to have a < 1% performance impact. 1090 1091config ARM_ERRATA_852421 1092 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1093 depends on CPU_V7 1094 help 1095 This option enables the workaround for the 852421 Cortex-A17 1096 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1097 execution of a DMB ST instruction might fail to properly order 1098 stores from GroupA and stores from GroupB. 1099 1100config ARM_ERRATA_852423 1101 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1102 depends on CPU_V7 1103 help 1104 This option enables the workaround for: 1105 - Cortex-A17 852423: Execution of a sequence of instructions might 1106 lead to either a data corruption or a CPU deadlock. Not fixed in 1107 any Cortex-A17 cores yet. 1108 This is identical to Cortex-A12 erratum 852422. It is a separate 1109 config option from the A12 erratum due to the way errata are checked 1110 for and handled. 1111 1112config ARM_ERRATA_857272 1113 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1114 depends on CPU_V7 1115 help 1116 This option enables the workaround for the 857272 Cortex-A17 erratum. 1117 This erratum is not known to be fixed in any A17 revision. 1118 This is identical to Cortex-A12 erratum 857271. It is a separate 1119 config option from the A12 erratum due to the way errata are checked 1120 for and handled. 1121 1122endmenu 1123 1124source "arch/arm/common/Kconfig" 1125 1126menu "Bus support" 1127 1128config ISA 1129 bool 1130 help 1131 Find out whether you have ISA slots on your motherboard. ISA is the 1132 name of a bus system, i.e. the way the CPU talks to the other stuff 1133 inside your box. Other bus systems are PCI, EISA, MicroChannel 1134 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1135 newer boards don't support it. If you have ISA, say Y, otherwise N. 1136 1137# Select ISA DMA controller support 1138config ISA_DMA 1139 bool 1140 select ISA_DMA_API 1141 1142# Select ISA DMA interface 1143config ISA_DMA_API 1144 bool 1145 1146config PCI_NANOENGINE 1147 bool "BSE nanoEngine PCI support" 1148 depends on SA1100_NANOENGINE 1149 help 1150 Enable PCI on the BSE nanoEngine board. 1151 1152config PCI_HOST_ITE8152 1153 bool 1154 depends on PCI && MACH_ARMCORE 1155 default y 1156 select DMABOUNCE 1157 1158config ARM_ERRATA_814220 1159 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1160 depends on CPU_V7 1161 help 1162 The v7 ARM states that all cache and branch predictor maintenance 1163 operations that do not specify an address execute, relative to 1164 each other, in program order. 1165 However, because of this erratum, an L2 set/way cache maintenance 1166 operation can overtake an L1 set/way cache maintenance operation. 1167 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1168 r0p4, r0p5. 1169 1170endmenu 1171 1172menu "Kernel Features" 1173 1174config HAVE_SMP 1175 bool 1176 help 1177 This option should be selected by machines which have an SMP- 1178 capable CPU. 1179 1180 The only effect of this option is to make the SMP-related 1181 options available to the user for configuration. 1182 1183config SMP 1184 bool "Symmetric Multi-Processing" 1185 depends on CPU_V6K || CPU_V7 1186 depends on GENERIC_CLOCKEVENTS 1187 depends on HAVE_SMP 1188 depends on MMU || ARM_MPU 1189 select IRQ_WORK 1190 help 1191 This enables support for systems with more than one CPU. If you have 1192 a system with only one CPU, say N. If you have a system with more 1193 than one CPU, say Y. 1194 1195 If you say N here, the kernel will run on uni- and multiprocessor 1196 machines, but will use only one CPU of a multiprocessor machine. If 1197 you say Y here, the kernel will run on many, but not all, 1198 uniprocessor machines. On a uniprocessor machine, the kernel 1199 will run faster if you say N here. 1200 1201 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1202 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1203 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1204 1205 If you don't know what to do here, say N. 1206 1207config SMP_ON_UP 1208 bool "Allow booting SMP kernel on uniprocessor systems" 1209 depends on SMP && !XIP_KERNEL && MMU 1210 default y 1211 help 1212 SMP kernels contain instructions which fail on non-SMP processors. 1213 Enabling this option allows the kernel to modify itself to make 1214 these instructions safe. Disabling it allows about 1K of space 1215 savings. 1216 1217 If you don't know what to do here, say Y. 1218 1219config ARM_CPU_TOPOLOGY 1220 bool "Support cpu topology definition" 1221 depends on SMP && CPU_V7 1222 default y 1223 help 1224 Support ARM cpu topology definition. The MPIDR register defines 1225 affinity between processors which is then used to describe the cpu 1226 topology of an ARM System. 1227 1228config SCHED_MC 1229 bool "Multi-core scheduler support" 1230 depends on ARM_CPU_TOPOLOGY 1231 help 1232 Multi-core scheduler support improves the CPU scheduler's decision 1233 making when dealing with multi-core CPU chips at a cost of slightly 1234 increased overhead in some places. If unsure say N here. 1235 1236config SCHED_SMT 1237 bool "SMT scheduler support" 1238 depends on ARM_CPU_TOPOLOGY 1239 help 1240 Improves the CPU scheduler's decision making when dealing with 1241 MultiThreading at a cost of slightly increased overhead in some 1242 places. If unsure say N here. 1243 1244config HAVE_ARM_SCU 1245 bool 1246 help 1247 This option enables support for the ARM snoop control unit 1248 1249config HAVE_ARM_ARCH_TIMER 1250 bool "Architected timer support" 1251 depends on CPU_V7 1252 select ARM_ARCH_TIMER 1253 select GENERIC_CLOCKEVENTS 1254 select GENERIC_GETTIMEOFDAY 1255 help 1256 This option enables support for the ARM architected timer 1257 1258config HAVE_ARM_TWD 1259 bool 1260 help 1261 This options enables support for the ARM timer and watchdog unit 1262 1263config MCPM 1264 bool "Multi-Cluster Power Management" 1265 depends on CPU_V7 && SMP 1266 help 1267 This option provides the common power management infrastructure 1268 for (multi-)cluster based systems, such as big.LITTLE based 1269 systems. 1270 1271config MCPM_QUAD_CLUSTER 1272 bool 1273 depends on MCPM 1274 help 1275 To avoid wasting resources unnecessarily, MCPM only supports up 1276 to 2 clusters by default. 1277 Platforms with 3 or 4 clusters that use MCPM must select this 1278 option to allow the additional clusters to be managed. 1279 1280config BIG_LITTLE 1281 bool "big.LITTLE support (Experimental)" 1282 depends on CPU_V7 && SMP 1283 select MCPM 1284 help 1285 This option enables support selections for the big.LITTLE 1286 system architecture. 1287 1288config BL_SWITCHER 1289 bool "big.LITTLE switcher support" 1290 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1291 select CPU_PM 1292 help 1293 The big.LITTLE "switcher" provides the core functionality to 1294 transparently handle transition between a cluster of A15's 1295 and a cluster of A7's in a big.LITTLE system. 1296 1297config BL_SWITCHER_DUMMY_IF 1298 tristate "Simple big.LITTLE switcher user interface" 1299 depends on BL_SWITCHER && DEBUG_KERNEL 1300 help 1301 This is a simple and dummy char dev interface to control 1302 the big.LITTLE switcher core code. It is meant for 1303 debugging purposes only. 1304 1305choice 1306 prompt "Memory split" 1307 depends on MMU 1308 default VMSPLIT_3G 1309 help 1310 Select the desired split between kernel and user memory. 1311 1312 If you are not absolutely sure what you are doing, leave this 1313 option alone! 1314 1315 config VMSPLIT_3G 1316 bool "3G/1G user/kernel split" 1317 config VMSPLIT_3G_OPT 1318 depends on !ARM_LPAE 1319 bool "3G/1G user/kernel split (for full 1G low memory)" 1320 config VMSPLIT_2G 1321 bool "2G/2G user/kernel split" 1322 config VMSPLIT_1G 1323 bool "1G/3G user/kernel split" 1324endchoice 1325 1326config PAGE_OFFSET 1327 hex 1328 default PHYS_OFFSET if !MMU 1329 default 0x40000000 if VMSPLIT_1G 1330 default 0x80000000 if VMSPLIT_2G 1331 default 0xB0000000 if VMSPLIT_3G_OPT 1332 default 0xC0000000 1333 1334config NR_CPUS 1335 int "Maximum number of CPUs (2-32)" 1336 range 2 32 1337 depends on SMP 1338 default "4" 1339 1340config HOTPLUG_CPU 1341 bool "Support for hot-pluggable CPUs" 1342 depends on SMP 1343 select GENERIC_IRQ_MIGRATION 1344 help 1345 Say Y here to experiment with turning CPUs off and on. CPUs 1346 can be controlled through /sys/devices/system/cpu. 1347 1348config ARM_PSCI 1349 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1350 depends on HAVE_ARM_SMCCC 1351 select ARM_PSCI_FW 1352 help 1353 Say Y here if you want Linux to communicate with system firmware 1354 implementing the PSCI specification for CPU-centric power 1355 management operations described in ARM document number ARM DEN 1356 0022A ("Power State Coordination Interface System Software on 1357 ARM processors"). 1358 1359# The GPIO number here must be sorted by descending number. In case of 1360# a multiplatform kernel, we just want the highest value required by the 1361# selected platforms. 1362config ARCH_NR_GPIO 1363 int 1364 default 2048 if ARCH_SOCFPGA 1365 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1366 ARCH_ZYNQ 1367 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1368 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1369 default 416 if ARCH_SUNXI 1370 default 392 if ARCH_U8500 1371 default 352 if ARCH_VT8500 1372 default 288 if ARCH_ROCKCHIP 1373 default 264 if MACH_H4700 1374 default 0 1375 help 1376 Maximum number of GPIOs in the system. 1377 1378 If unsure, leave the default value. 1379 1380config HZ_FIXED 1381 int 1382 default 200 if ARCH_EBSA110 1383 default 128 if SOC_AT91RM9200 1384 default 0 1385 1386choice 1387 depends on HZ_FIXED = 0 1388 prompt "Timer frequency" 1389 1390config HZ_100 1391 bool "100 Hz" 1392 1393config HZ_200 1394 bool "200 Hz" 1395 1396config HZ_250 1397 bool "250 Hz" 1398 1399config HZ_300 1400 bool "300 Hz" 1401 1402config HZ_500 1403 bool "500 Hz" 1404 1405config HZ_1000 1406 bool "1000 Hz" 1407 1408endchoice 1409 1410config HZ 1411 int 1412 default HZ_FIXED if HZ_FIXED != 0 1413 default 100 if HZ_100 1414 default 200 if HZ_200 1415 default 250 if HZ_250 1416 default 300 if HZ_300 1417 default 500 if HZ_500 1418 default 1000 1419 1420config SCHED_HRTICK 1421 def_bool HIGH_RES_TIMERS 1422 1423config THUMB2_KERNEL 1424 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1425 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1426 default y if CPU_THUMBONLY 1427 select ARM_UNWIND 1428 help 1429 By enabling this option, the kernel will be compiled in 1430 Thumb-2 mode. 1431 1432 If unsure, say N. 1433 1434config THUMB2_AVOID_R_ARM_THM_JUMP11 1435 bool "Work around buggy Thumb-2 short branch relocations in gas" 1436 depends on THUMB2_KERNEL && MODULES 1437 default y 1438 help 1439 Various binutils versions can resolve Thumb-2 branches to 1440 locally-defined, preemptible global symbols as short-range "b.n" 1441 branch instructions. 1442 1443 This is a problem, because there's no guarantee the final 1444 destination of the symbol, or any candidate locations for a 1445 trampoline, are within range of the branch. For this reason, the 1446 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1447 relocation in modules at all, and it makes little sense to add 1448 support. 1449 1450 The symptom is that the kernel fails with an "unsupported 1451 relocation" error when loading some modules. 1452 1453 Until fixed tools are available, passing 1454 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1455 code which hits this problem, at the cost of a bit of extra runtime 1456 stack usage in some cases. 1457 1458 The problem is described in more detail at: 1459 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1460 1461 Only Thumb-2 kernels are affected. 1462 1463 Unless you are sure your tools don't have this problem, say Y. 1464 1465config ARM_PATCH_IDIV 1466 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1467 depends on CPU_32v7 && !XIP_KERNEL 1468 default y 1469 help 1470 The ARM compiler inserts calls to __aeabi_idiv() and 1471 __aeabi_uidiv() when it needs to perform division on signed 1472 and unsigned integers. Some v7 CPUs have support for the sdiv 1473 and udiv instructions that can be used to implement those 1474 functions. 1475 1476 Enabling this option allows the kernel to modify itself to 1477 replace the first two instructions of these library functions 1478 with the sdiv or udiv plus "bx lr" instructions when the CPU 1479 it is running on supports them. Typically this will be faster 1480 and less power intensive than running the original library 1481 code to do integer division. 1482 1483config AEABI 1484 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1485 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1486 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1487 help 1488 This option allows for the kernel to be compiled using the latest 1489 ARM ABI (aka EABI). This is only useful if you are using a user 1490 space environment that is also compiled with EABI. 1491 1492 Since there are major incompatibilities between the legacy ABI and 1493 EABI, especially with regard to structure member alignment, this 1494 option also changes the kernel syscall calling convention to 1495 disambiguate both ABIs and allow for backward compatibility support 1496 (selected with CONFIG_OABI_COMPAT). 1497 1498 To use this you need GCC version 4.0.0 or later. 1499 1500config OABI_COMPAT 1501 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1502 depends on AEABI && !THUMB2_KERNEL 1503 help 1504 This option preserves the old syscall interface along with the 1505 new (ARM EABI) one. It also provides a compatibility layer to 1506 intercept syscalls that have structure arguments which layout 1507 in memory differs between the legacy ABI and the new ARM EABI 1508 (only for non "thumb" binaries). This option adds a tiny 1509 overhead to all syscalls and produces a slightly larger kernel. 1510 1511 The seccomp filter system will not be available when this is 1512 selected, since there is no way yet to sensibly distinguish 1513 between calling conventions during filtering. 1514 1515 If you know you'll be using only pure EABI user space then you 1516 can say N here. If this option is not selected and you attempt 1517 to execute a legacy ABI binary then the result will be 1518 UNPREDICTABLE (in fact it can be predicted that it won't work 1519 at all). If in doubt say N. 1520 1521config ARCH_SPARSEMEM_ENABLE 1522 bool 1523 1524config ARCH_SPARSEMEM_DEFAULT 1525 def_bool ARCH_SPARSEMEM_ENABLE 1526 1527config HAVE_ARCH_PFN_VALID 1528 def_bool y 1529 1530config HIGHMEM 1531 bool "High Memory Support" 1532 depends on MMU 1533 help 1534 The address space of ARM processors is only 4 Gigabytes large 1535 and it has to accommodate user address space, kernel address 1536 space as well as some memory mapped IO. That means that, if you 1537 have a large amount of physical memory and/or IO, not all of the 1538 memory can be "permanently mapped" by the kernel. The physical 1539 memory that is not permanently mapped is called "high memory". 1540 1541 Depending on the selected kernel/user memory split, minimum 1542 vmalloc space and actual amount of RAM, you may not need this 1543 option which should result in a slightly faster kernel. 1544 1545 If unsure, say n. 1546 1547config HIGHPTE 1548 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1549 depends on HIGHMEM 1550 default y 1551 help 1552 The VM uses one page of physical memory for each page table. 1553 For systems with a lot of processes, this can use a lot of 1554 precious low memory, eventually leading to low memory being 1555 consumed by page tables. Setting this option will allow 1556 user-space 2nd level page tables to reside in high memory. 1557 1558config CPU_SW_DOMAIN_PAN 1559 bool "Enable use of CPU domains to implement privileged no-access" 1560 depends on MMU && !ARM_LPAE 1561 default y 1562 help 1563 Increase kernel security by ensuring that normal kernel accesses 1564 are unable to access userspace addresses. This can help prevent 1565 use-after-free bugs becoming an exploitable privilege escalation 1566 by ensuring that magic values (such as LIST_POISON) will always 1567 fault when dereferenced. 1568 1569 CPUs with low-vector mappings use a best-efforts implementation. 1570 Their lower 1MB needs to remain accessible for the vectors, but 1571 the remainder of userspace will become appropriately inaccessible. 1572 1573config HW_PERF_EVENTS 1574 def_bool y 1575 depends on ARM_PMU 1576 1577config SYS_SUPPORTS_HUGETLBFS 1578 def_bool y 1579 depends on ARM_LPAE 1580 1581config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1582 def_bool y 1583 depends on ARM_LPAE 1584 1585config ARCH_WANT_GENERAL_HUGETLB 1586 def_bool y 1587 1588config ARM_MODULE_PLTS 1589 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1590 depends on MODULES 1591 default y 1592 help 1593 Allocate PLTs when loading modules so that jumps and calls whose 1594 targets are too far away for their relative offsets to be encoded 1595 in the instructions themselves can be bounced via veneers in the 1596 module's PLT. This allows modules to be allocated in the generic 1597 vmalloc area after the dedicated module memory area has been 1598 exhausted. The modules will use slightly more memory, but after 1599 rounding up to page size, the actual memory footprint is usually 1600 the same. 1601 1602 Disabling this is usually safe for small single-platform 1603 configurations. If unsure, say y. 1604 1605config FORCE_MAX_ZONEORDER 1606 int "Maximum zone order" 1607 default "12" if SOC_AM33XX 1608 default "9" if SA1111 || ARCH_EFM32 1609 default "11" 1610 help 1611 The kernel memory allocator divides physically contiguous memory 1612 blocks into "zones", where each zone is a power of two number of 1613 pages. This option selects the largest power of two that the kernel 1614 keeps in the memory allocator. If you need to allocate very large 1615 blocks of physically contiguous memory, then you may need to 1616 increase this value. 1617 1618 This config option is actually maximum order plus one. For example, 1619 a value of 11 means that the largest free memory block is 2^10 pages. 1620 1621config ALIGNMENT_TRAP 1622 bool 1623 depends on CPU_CP15_MMU 1624 default y if !ARCH_EBSA110 1625 select HAVE_PROC_CPU if PROC_FS 1626 help 1627 ARM processors cannot fetch/store information which is not 1628 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1629 address divisible by 4. On 32-bit ARM processors, these non-aligned 1630 fetch/store instructions will be emulated in software if you say 1631 here, which has a severe performance impact. This is necessary for 1632 correct operation of some network protocols. With an IP-only 1633 configuration it is safe to say N, otherwise say Y. 1634 1635config UACCESS_WITH_MEMCPY 1636 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1637 depends on MMU 1638 default y if CPU_FEROCEON 1639 help 1640 Implement faster copy_to_user and clear_user methods for CPU 1641 cores where a 8-word STM instruction give significantly higher 1642 memory write throughput than a sequence of individual 32bit stores. 1643 1644 A possible side effect is a slight increase in scheduling latency 1645 between threads sharing the same address space if they invoke 1646 such copy operations with large buffers. 1647 1648 However, if the CPU data cache is using a write-allocate mode, 1649 this option is unlikely to provide any performance gain. 1650 1651config SECCOMP 1652 bool 1653 prompt "Enable seccomp to safely compute untrusted bytecode" 1654 ---help--- 1655 This kernel feature is useful for number crunching applications 1656 that may need to compute untrusted bytecode during their 1657 execution. By using pipes or other transports made available to 1658 the process as file descriptors supporting the read/write 1659 syscalls, it's possible to isolate those applications in 1660 their own address space using seccomp. Once seccomp is 1661 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1662 and the task is only allowed to execute a few safe syscalls 1663 defined by each seccomp mode. 1664 1665config PARAVIRT 1666 bool "Enable paravirtualization code" 1667 help 1668 This changes the kernel so it can modify itself when it is run 1669 under a hypervisor, potentially improving performance significantly 1670 over full virtualization. 1671 1672config PARAVIRT_TIME_ACCOUNTING 1673 bool "Paravirtual steal time accounting" 1674 select PARAVIRT 1675 help 1676 Select this option to enable fine granularity task steal time 1677 accounting. Time spent executing other tasks in parallel with 1678 the current vCPU is discounted from the vCPU power. To account for 1679 that, there can be a small performance impact. 1680 1681 If in doubt, say N here. 1682 1683config XEN_DOM0 1684 def_bool y 1685 depends on XEN 1686 1687config XEN 1688 bool "Xen guest support on ARM" 1689 depends on ARM && AEABI && OF 1690 depends on CPU_V7 && !CPU_V6 1691 depends on !GENERIC_ATOMIC64 1692 depends on MMU 1693 select ARCH_DMA_ADDR_T_64BIT 1694 select ARM_PSCI 1695 select SWIOTLB 1696 select SWIOTLB_XEN 1697 select PARAVIRT 1698 help 1699 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1700 1701config STACKPROTECTOR_PER_TASK 1702 bool "Use a unique stack canary value for each task" 1703 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1704 select GCC_PLUGIN_ARM_SSP_PER_TASK 1705 default y 1706 help 1707 Due to the fact that GCC uses an ordinary symbol reference from 1708 which to load the value of the stack canary, this value can only 1709 change at reboot time on SMP systems, and all tasks running in the 1710 kernel's address space are forced to use the same canary value for 1711 the entire duration that the system is up. 1712 1713 Enable this option to switch to a different method that uses a 1714 different canary value for each task. 1715 1716endmenu 1717 1718menu "Boot options" 1719 1720config USE_OF 1721 bool "Flattened Device Tree support" 1722 select IRQ_DOMAIN 1723 select OF 1724 help 1725 Include support for flattened device tree machine descriptions. 1726 1727config ATAGS 1728 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1729 default y 1730 help 1731 This is the traditional way of passing data to the kernel at boot 1732 time. If you are solely relying on the flattened device tree (or 1733 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1734 to remove ATAGS support from your kernel binary. If unsure, 1735 leave this to y. 1736 1737config DEPRECATED_PARAM_STRUCT 1738 bool "Provide old way to pass kernel parameters" 1739 depends on ATAGS 1740 help 1741 This was deprecated in 2001 and announced to live on for 5 years. 1742 Some old boot loaders still use this way. 1743 1744# Compressed boot loader in ROM. Yes, we really want to ask about 1745# TEXT and BSS so we preserve their values in the config files. 1746config ZBOOT_ROM_TEXT 1747 hex "Compressed ROM boot loader base address" 1748 default "0" 1749 help 1750 The physical address at which the ROM-able zImage is to be 1751 placed in the target. Platforms which normally make use of 1752 ROM-able zImage formats normally set this to a suitable 1753 value in their defconfig file. 1754 1755 If ZBOOT_ROM is not enabled, this has no effect. 1756 1757config ZBOOT_ROM_BSS 1758 hex "Compressed ROM boot loader BSS address" 1759 default "0" 1760 help 1761 The base address of an area of read/write memory in the target 1762 for the ROM-able zImage which must be available while the 1763 decompressor is running. It must be large enough to hold the 1764 entire decompressed kernel plus an additional 128 KiB. 1765 Platforms which normally make use of ROM-able zImage formats 1766 normally set this to a suitable value in their defconfig file. 1767 1768 If ZBOOT_ROM is not enabled, this has no effect. 1769 1770config ZBOOT_ROM 1771 bool "Compressed boot loader in ROM/flash" 1772 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1773 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1774 help 1775 Say Y here if you intend to execute your compressed kernel image 1776 (zImage) directly from ROM or flash. If unsure, say N. 1777 1778config ARM_APPENDED_DTB 1779 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1780 depends on OF 1781 help 1782 With this option, the boot code will look for a device tree binary 1783 (DTB) appended to zImage 1784 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1785 1786 This is meant as a backward compatibility convenience for those 1787 systems with a bootloader that can't be upgraded to accommodate 1788 the documented boot protocol using a device tree. 1789 1790 Beware that there is very little in terms of protection against 1791 this option being confused by leftover garbage in memory that might 1792 look like a DTB header after a reboot if no actual DTB is appended 1793 to zImage. Do not leave this option active in a production kernel 1794 if you don't intend to always append a DTB. Proper passing of the 1795 location into r2 of a bootloader provided DTB is always preferable 1796 to this option. 1797 1798config ARM_ATAG_DTB_COMPAT 1799 bool "Supplement the appended DTB with traditional ATAG information" 1800 depends on ARM_APPENDED_DTB 1801 help 1802 Some old bootloaders can't be updated to a DTB capable one, yet 1803 they provide ATAGs with memory configuration, the ramdisk address, 1804 the kernel cmdline string, etc. Such information is dynamically 1805 provided by the bootloader and can't always be stored in a static 1806 DTB. To allow a device tree enabled kernel to be used with such 1807 bootloaders, this option allows zImage to extract the information 1808 from the ATAG list and store it at run time into the appended DTB. 1809 1810choice 1811 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1812 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1813 1814config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1815 bool "Use bootloader kernel arguments if available" 1816 help 1817 Uses the command-line options passed by the boot loader instead of 1818 the device tree bootargs property. If the boot loader doesn't provide 1819 any, the device tree bootargs property will be used. 1820 1821config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1822 bool "Extend with bootloader kernel arguments" 1823 help 1824 The command-line arguments provided by the boot loader will be 1825 appended to the the device tree bootargs property. 1826 1827endchoice 1828 1829config CMDLINE 1830 string "Default kernel command string" 1831 default "" 1832 help 1833 On some architectures (EBSA110 and CATS), there is currently no way 1834 for the boot loader to pass arguments to the kernel. For these 1835 architectures, you should supply some command-line options at build 1836 time by entering them here. As a minimum, you should specify the 1837 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1838 1839choice 1840 prompt "Kernel command line type" if CMDLINE != "" 1841 default CMDLINE_FROM_BOOTLOADER 1842 1843config CMDLINE_FROM_BOOTLOADER 1844 bool "Use bootloader kernel arguments if available" 1845 help 1846 Uses the command-line options passed by the boot loader. If 1847 the boot loader doesn't provide any, the default kernel command 1848 string provided in CMDLINE will be used. 1849 1850config CMDLINE_EXTEND 1851 bool "Extend bootloader kernel arguments" 1852 help 1853 The command-line arguments provided by the boot loader will be 1854 appended to the default kernel command string. 1855 1856config CMDLINE_FORCE 1857 bool "Always use the default kernel command string" 1858 help 1859 Always use the default kernel command string, even if the boot 1860 loader passes other arguments to the kernel. 1861 This is useful if you cannot or don't want to change the 1862 command-line options your boot loader passes to the kernel. 1863endchoice 1864 1865config XIP_KERNEL 1866 bool "Kernel Execute-In-Place from ROM" 1867 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1868 help 1869 Execute-In-Place allows the kernel to run from non-volatile storage 1870 directly addressable by the CPU, such as NOR flash. This saves RAM 1871 space since the text section of the kernel is not loaded from flash 1872 to RAM. Read-write sections, such as the data section and stack, 1873 are still copied to RAM. The XIP kernel is not compressed since 1874 it has to run directly from flash, so it will take more space to 1875 store it. The flash address used to link the kernel object files, 1876 and for storing it, is configuration dependent. Therefore, if you 1877 say Y here, you must know the proper physical address where to 1878 store the kernel image depending on your own flash memory usage. 1879 1880 Also note that the make target becomes "make xipImage" rather than 1881 "make zImage" or "make Image". The final kernel binary to put in 1882 ROM memory will be arch/arm/boot/xipImage. 1883 1884 If unsure, say N. 1885 1886config XIP_PHYS_ADDR 1887 hex "XIP Kernel Physical Location" 1888 depends on XIP_KERNEL 1889 default "0x00080000" 1890 help 1891 This is the physical address in your flash memory the kernel will 1892 be linked for and stored to. This address is dependent on your 1893 own flash usage. 1894 1895config XIP_DEFLATED_DATA 1896 bool "Store kernel .data section compressed in ROM" 1897 depends on XIP_KERNEL 1898 select ZLIB_INFLATE 1899 help 1900 Before the kernel is actually executed, its .data section has to be 1901 copied to RAM from ROM. This option allows for storing that data 1902 in compressed form and decompressed to RAM rather than merely being 1903 copied, saving some precious ROM space. A possible drawback is a 1904 slightly longer boot delay. 1905 1906config KEXEC 1907 bool "Kexec system call (EXPERIMENTAL)" 1908 depends on (!SMP || PM_SLEEP_SMP) 1909 depends on MMU 1910 select KEXEC_CORE 1911 help 1912 kexec is a system call that implements the ability to shutdown your 1913 current kernel, and to start another kernel. It is like a reboot 1914 but it is independent of the system firmware. And like a reboot 1915 you can start any kernel with it, not just Linux. 1916 1917 It is an ongoing process to be certain the hardware in a machine 1918 is properly shutdown, so do not be surprised if this code does not 1919 initially work for you. 1920 1921config ATAGS_PROC 1922 bool "Export atags in procfs" 1923 depends on ATAGS && KEXEC 1924 default y 1925 help 1926 Should the atags used to boot the kernel be exported in an "atags" 1927 file in procfs. Useful with kexec. 1928 1929config CRASH_DUMP 1930 bool "Build kdump crash kernel (EXPERIMENTAL)" 1931 help 1932 Generate crash dump after being started by kexec. This should 1933 be normally only set in special crash dump kernels which are 1934 loaded in the main kernel with kexec-tools into a specially 1935 reserved region and then later executed after a crash by 1936 kdump/kexec. The crash dump kernel must be compiled to a 1937 memory address not used by the main kernel 1938 1939 For more details see Documentation/admin-guide/kdump/kdump.rst 1940 1941config AUTO_ZRELADDR 1942 bool "Auto calculation of the decompressed kernel image address" 1943 help 1944 ZRELADDR is the physical address where the decompressed kernel 1945 image will be placed. If AUTO_ZRELADDR is selected, the address 1946 will be determined at run-time by masking the current IP with 1947 0xf8000000. This assumes the zImage being placed in the first 128MB 1948 from start of memory. 1949 1950config EFI_STUB 1951 bool 1952 1953config EFI 1954 bool "UEFI runtime support" 1955 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1956 select UCS2_STRING 1957 select EFI_PARAMS_FROM_FDT 1958 select EFI_STUB 1959 select EFI_ARMSTUB 1960 select EFI_RUNTIME_WRAPPERS 1961 ---help--- 1962 This option provides support for runtime services provided 1963 by UEFI firmware (such as non-volatile variables, realtime 1964 clock, and platform reset). A UEFI stub is also provided to 1965 allow the kernel to be booted as an EFI application. This 1966 is only useful for kernels that may run on systems that have 1967 UEFI firmware. 1968 1969config DMI 1970 bool "Enable support for SMBIOS (DMI) tables" 1971 depends on EFI 1972 default y 1973 help 1974 This enables SMBIOS/DMI feature for systems. 1975 1976 This option is only useful on systems that have UEFI firmware. 1977 However, even with this option, the resultant kernel should 1978 continue to boot on existing non-UEFI platforms. 1979 1980 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1981 i.e., the the practice of identifying the platform via DMI to 1982 decide whether certain workarounds for buggy hardware and/or 1983 firmware need to be enabled. This would require the DMI subsystem 1984 to be enabled much earlier than we do on ARM, which is non-trivial. 1985 1986endmenu 1987 1988menu "CPU Power Management" 1989 1990source "drivers/cpufreq/Kconfig" 1991 1992source "drivers/cpuidle/Kconfig" 1993 1994endmenu 1995 1996menu "Floating point emulation" 1997 1998comment "At least one emulation must be selected" 1999 2000config FPE_NWFPE 2001 bool "NWFPE math emulation" 2002 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2003 ---help--- 2004 Say Y to include the NWFPE floating point emulator in the kernel. 2005 This is necessary to run most binaries. Linux does not currently 2006 support floating point hardware so you need to say Y here even if 2007 your machine has an FPA or floating point co-processor podule. 2008 2009 You may say N here if you are going to load the Acorn FPEmulator 2010 early in the bootup. 2011 2012config FPE_NWFPE_XP 2013 bool "Support extended precision" 2014 depends on FPE_NWFPE 2015 help 2016 Say Y to include 80-bit support in the kernel floating-point 2017 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2018 Note that gcc does not generate 80-bit operations by default, 2019 so in most cases this option only enlarges the size of the 2020 floating point emulator without any good reason. 2021 2022 You almost surely want to say N here. 2023 2024config FPE_FASTFPE 2025 bool "FastFPE math emulation (EXPERIMENTAL)" 2026 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2027 ---help--- 2028 Say Y here to include the FAST floating point emulator in the kernel. 2029 This is an experimental much faster emulator which now also has full 2030 precision for the mantissa. It does not support any exceptions. 2031 It is very simple, and approximately 3-6 times faster than NWFPE. 2032 2033 It should be sufficient for most programs. It may be not suitable 2034 for scientific calculations, but you have to check this for yourself. 2035 If you do not feel you need a faster FP emulation you should better 2036 choose NWFPE. 2037 2038config VFP 2039 bool "VFP-format floating point maths" 2040 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2041 help 2042 Say Y to include VFP support code in the kernel. This is needed 2043 if your hardware includes a VFP unit. 2044 2045 Please see <file:Documentation/arm/vfp/release-notes.rst> for 2046 release notes and additional status information. 2047 2048 Say N if your target does not have VFP hardware. 2049 2050config VFPv3 2051 bool 2052 depends on VFP 2053 default y if CPU_V7 2054 2055config NEON 2056 bool "Advanced SIMD (NEON) Extension support" 2057 depends on VFPv3 && CPU_V7 2058 help 2059 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2060 Extension. 2061 2062config KERNEL_MODE_NEON 2063 bool "Support for NEON in kernel mode" 2064 depends on NEON && AEABI 2065 help 2066 Say Y to include support for NEON in kernel mode. 2067 2068endmenu 2069 2070menu "Power management options" 2071 2072source "kernel/power/Kconfig" 2073 2074config ARCH_SUSPEND_POSSIBLE 2075 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2076 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2077 def_bool y 2078 2079config ARM_CPU_SUSPEND 2080 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2081 depends on ARCH_SUSPEND_POSSIBLE 2082 2083config ARCH_HIBERNATION_POSSIBLE 2084 bool 2085 depends on MMU 2086 default y if ARCH_SUSPEND_POSSIBLE 2087 2088endmenu 2089 2090source "drivers/firmware/Kconfig" 2091 2092if CRYPTO 2093source "arch/arm/crypto/Kconfig" 2094endif 2095 2096source "arch/arm/kvm/Kconfig" 2097