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1# SPDX-License-Identifier: GPL-2.0
2config XTENSA
3	def_bool y
4	select ARCH_32BIT_OFF_T
5	select ARCH_HAS_BINFMT_FLAT if !MMU
6	select ARCH_HAS_SYNC_DMA_FOR_CPU
7	select ARCH_HAS_SYNC_DMA_FOR_DEVICE
8	select ARCH_USE_QUEUED_RWLOCKS
9	select ARCH_USE_QUEUED_SPINLOCKS
10	select ARCH_WANT_FRAME_POINTERS
11	select ARCH_WANT_IPC_PARSE_VERSION
12	select BUILDTIME_EXTABLE_SORT
13	select CLONE_BACKWARDS
14	select COMMON_CLK
15	select DMA_REMAP if MMU
16	select GENERIC_ATOMIC64
17	select GENERIC_CLOCKEVENTS
18	select GENERIC_IRQ_SHOW
19	select GENERIC_PCI_IOMAP
20	select GENERIC_SCHED_CLOCK
21	select GENERIC_STRNCPY_FROM_USER if KASAN
22	select HAVE_ARCH_JUMP_LABEL
23	select HAVE_ARCH_KASAN if MMU
24	select HAVE_ARCH_TRACEHOOK
25	select HAVE_COPY_THREAD_TLS
26	select HAVE_DEBUG_KMEMLEAK
27	select HAVE_DMA_CONTIGUOUS
28	select HAVE_EXIT_THREAD
29	select HAVE_FUNCTION_TRACER
30	select HAVE_FUTEX_CMPXCHG if !MMU && FUTEX
31	select HAVE_HW_BREAKPOINT if PERF_EVENTS
32	select HAVE_IRQ_TIME_ACCOUNTING
33	select HAVE_OPROFILE
34	select HAVE_PCI
35	select HAVE_PERF_EVENTS
36	select HAVE_STACKPROTECTOR
37	select HAVE_SYSCALL_TRACEPOINTS
38	select IRQ_DOMAIN
39	select MODULES_USE_ELF_RELA
40	select PERF_USE_VMALLOC
41	select VIRT_TO_BUS
42	help
43	  Xtensa processors are 32-bit RISC machines designed by Tensilica
44	  primarily for embedded systems.  These processors are both
45	  configurable and extensible.  The Linux port to the Xtensa
46	  architecture supports all processor configurations and extensions,
47	  with reasonable minimum requirements.  The Xtensa Linux project has
48	  a home page at <http://www.linux-xtensa.org/>.
49
50config GENERIC_HWEIGHT
51	def_bool y
52
53config ARCH_HAS_ILOG2_U32
54	def_bool n
55
56config ARCH_HAS_ILOG2_U64
57	def_bool n
58
59config NO_IOPORT_MAP
60	def_bool n
61
62config HZ
63	int
64	default 100
65
66config LOCKDEP_SUPPORT
67	def_bool y
68
69config STACKTRACE_SUPPORT
70	def_bool y
71
72config TRACE_IRQFLAGS_SUPPORT
73	def_bool y
74
75config MMU
76	def_bool n
77
78config HAVE_XTENSA_GPIO32
79	def_bool n
80
81config KASAN_SHADOW_OFFSET
82	hex
83	default 0x6e400000
84
85menu "Processor type and features"
86
87choice
88	prompt "Xtensa Processor Configuration"
89	default XTENSA_VARIANT_FSF
90
91config XTENSA_VARIANT_FSF
92	bool "fsf - default (not generic) configuration"
93	select MMU
94
95config XTENSA_VARIANT_DC232B
96	bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
97	select MMU
98	select HAVE_XTENSA_GPIO32
99	help
100	  This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE).
101
102config XTENSA_VARIANT_DC233C
103	bool "dc233c - Diamond 233L Standard Core Rev.C (LE)"
104	select MMU
105	select HAVE_XTENSA_GPIO32
106	help
107	  This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE).
108
109config XTENSA_VARIANT_CUSTOM
110	bool "Custom Xtensa processor configuration"
111	select HAVE_XTENSA_GPIO32
112	help
113	  Select this variant to use a custom Xtensa processor configuration.
114	  You will be prompted for a processor variant CORENAME.
115endchoice
116
117config XTENSA_VARIANT_CUSTOM_NAME
118	string "Xtensa Processor Custom Core Variant Name"
119	depends on XTENSA_VARIANT_CUSTOM
120	help
121	  Provide the name of a custom Xtensa processor variant.
122	  This CORENAME selects arch/xtensa/variant/CORENAME.
123	  Dont forget you have to select MMU if you have one.
124
125config XTENSA_VARIANT_NAME
126	string
127	default "dc232b"			if XTENSA_VARIANT_DC232B
128	default "dc233c"			if XTENSA_VARIANT_DC233C
129	default "fsf"				if XTENSA_VARIANT_FSF
130	default XTENSA_VARIANT_CUSTOM_NAME	if XTENSA_VARIANT_CUSTOM
131
132config XTENSA_VARIANT_MMU
133	bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)"
134	depends on XTENSA_VARIANT_CUSTOM
135	default y
136	select MMU
137	help
138	  Build a Conventional Kernel with full MMU support,
139	  ie: it supports a TLB with auto-loading, page protection.
140
141config XTENSA_VARIANT_HAVE_PERF_EVENTS
142	bool "Core variant has Performance Monitor Module"
143	depends on XTENSA_VARIANT_CUSTOM
144	default n
145	help
146	  Enable if core variant has Performance Monitor Module with
147	  External Registers Interface.
148
149	  If unsure, say N.
150
151config XTENSA_FAKE_NMI
152	bool "Treat PMM IRQ as NMI"
153	depends on XTENSA_VARIANT_HAVE_PERF_EVENTS
154	default n
155	help
156	  If PMM IRQ is the only IRQ at EXCM level it is safe to
157	  treat it as NMI, which improves accuracy of profiling.
158
159	  If there are other interrupts at or above PMM IRQ priority level
160	  but not above the EXCM level, PMM IRQ still may be treated as NMI,
161	  but only if these IRQs are not used. There will be a build warning
162	  saying that this is not safe, and a bugcheck if one of these IRQs
163	  actually fire.
164
165	  If unsure, say N.
166
167config XTENSA_UNALIGNED_USER
168	bool "Unaligned memory access in user space"
169	help
170	  The Xtensa architecture currently does not handle unaligned
171	  memory accesses in hardware but through an exception handler.
172	  Per default, unaligned memory accesses are disabled in user space.
173
174	  Say Y here to enable unaligned memory access in user space.
175
176config HAVE_SMP
177	bool "System Supports SMP (MX)"
178	depends on XTENSA_VARIANT_CUSTOM
179	select XTENSA_MX
180	help
181	  This option is use to indicate that the system-on-a-chip (SOC)
182	  supports Multiprocessing. Multiprocessor support implemented above
183	  the CPU core definition and currently needs to be selected manually.
184
185	  Multiprocessor support in implemented with external cache and
186	  interrupt controllers.
187
188	  The MX interrupt distributer adds Interprocessor Interrupts
189	  and causes the IRQ numbers to be increased by 4 for devices
190	  like the open cores ethernet driver and the serial interface.
191
192	  You still have to select "Enable SMP" to enable SMP on this SOC.
193
194config SMP
195	bool "Enable Symmetric multi-processing support"
196	depends on HAVE_SMP
197	select GENERIC_SMP_IDLE_THREAD
198	help
199	  Enabled SMP Software; allows more than one CPU/CORE
200	  to be activated during startup.
201
202config NR_CPUS
203	depends on SMP
204	int "Maximum number of CPUs (2-32)"
205	range 2 32
206	default "4"
207
208config HOTPLUG_CPU
209	bool "Enable CPU hotplug support"
210	depends on SMP
211	help
212	  Say Y here to allow turning CPUs off and on. CPUs can be
213	  controlled through /sys/devices/system/cpu.
214
215	  Say N if you want to disable CPU hotplug.
216
217config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
218	bool "Initialize Xtensa MMU inside the Linux kernel code"
219	depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B
220	default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM
221	help
222	  Earlier version initialized the MMU in the exception vector
223	  before jumping to _startup in head.S and had an advantage that
224	  it was possible to place a software breakpoint at 'reset' and
225	  then enter your normal kernel breakpoints once the MMU was mapped
226	  to the kernel mappings (0XC0000000).
227
228	  This unfortunately won't work for U-Boot and likely also wont
229	  work for using KEXEC to have a hot kernel ready for doing a
230	  KDUMP.
231
232	  So now the MMU is initialized in head.S but it's necessary to
233	  use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup.
234	  xt-gdb can't place a Software Breakpoint in the  0XD region prior
235	  to mapping the MMU and after mapping even if the area of low memory
236	  was mapped gdb wouldn't remove the breakpoint on hitting it as the
237	  PC wouldn't match. Since Hardware Breakpoints are recommended for
238	  Linux configurations it seems reasonable to just assume they exist
239	  and leave this older mechanism for unfortunate souls that choose
240	  not to follow Tensilica's recommendation.
241
242	  Selecting this will cause U-Boot to set the KERNEL Load and Entry
243	  address at 0x00003000 instead of the mapped std of 0xD0003000.
244
245	  If in doubt, say Y.
246
247config MEMMAP_CACHEATTR
248	hex "Cache attributes for the memory address space"
249	depends on !MMU
250	default 0x22222222
251	help
252	  These cache attributes are set up for noMMU systems. Each hex digit
253	  specifies cache attributes for the corresponding 512MB memory
254	  region: bits 0..3 -- for addresses 0x00000000..0x1fffffff,
255	  bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on.
256
257	  Cache attribute values are specific for the MMU type.
258	  For region protection MMUs:
259	    1: WT cached,
260	    2: cache bypass,
261	    4: WB cached,
262	    f: illegal.
263	  For ful MMU:
264	    bit 0: executable,
265	    bit 1: writable,
266	    bits 2..3:
267	      0: cache bypass,
268	      1: WB cache,
269	      2: WT cache,
270	      3: special (c and e are illegal, f is reserved).
271	  For MPU:
272	    0: illegal,
273	    1: WB cache,
274	    2: WB, no-write-allocate cache,
275	    3: WT cache,
276	    4: cache bypass.
277
278config KSEG_PADDR
279	hex "Physical address of the KSEG mapping"
280	depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU
281	default 0x00000000
282	help
283	  This is the physical address where KSEG is mapped. Please refer to
284	  the chosen KSEG layout help for the required address alignment.
285	  Unpacked kernel image (including vectors) must be located completely
286	  within KSEG.
287	  Physical memory below this address is not available to linux.
288
289	  If unsure, leave the default value here.
290
291config KERNEL_LOAD_ADDRESS
292	hex "Kernel load address"
293	default 0x60003000 if !MMU
294	default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
295	default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
296	help
297	  This is the address where the kernel is loaded.
298	  It is virtual address for MMUv2 configurations and physical address
299	  for all other configurations.
300
301	  If unsure, leave the default value here.
302
303config VECTORS_OFFSET
304	hex "Kernel vectors offset"
305	default 0x00003000
306	help
307	  This is the offset of the kernel image from the relocatable vectors
308	  base.
309
310	  If unsure, leave the default value here.
311
312choice
313	prompt "KSEG layout"
314	depends on MMU
315	default XTENSA_KSEG_MMU_V2
316
317config XTENSA_KSEG_MMU_V2
318	bool "MMUv2: 128MB cached + 128MB uncached"
319	help
320	  MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting
321	  at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000
322	  without cache.
323	  KSEG_PADDR must be aligned to 128MB.
324
325config XTENSA_KSEG_256M
326	bool "256MB cached + 256MB uncached"
327	depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
328	help
329	  TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000
330	  with cache and to 0xc0000000 without cache.
331	  KSEG_PADDR must be aligned to 256MB.
332
333config XTENSA_KSEG_512M
334	bool "512MB cached + 512MB uncached"
335	depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX
336	help
337	  TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000
338	  with cache and to 0xc0000000 without cache.
339	  KSEG_PADDR must be aligned to 256MB.
340
341endchoice
342
343config HIGHMEM
344	bool "High Memory Support"
345	depends on MMU
346	help
347	  Linux can use the full amount of RAM in the system by
348	  default. However, the default MMUv2 setup only maps the
349	  lowermost 128 MB of memory linearly to the areas starting
350	  at 0xd0000000 (cached) and 0xd8000000 (uncached).
351	  When there are more than 128 MB memory in the system not
352	  all of it can be "permanently mapped" by the kernel.
353	  The physical memory that's not permanently mapped is called
354	  "high memory".
355
356	  If you are compiling a kernel which will never run on a
357	  machine with more than 128 MB total physical RAM, answer
358	  N here.
359
360	  If unsure, say Y.
361
362config FAST_SYSCALL_XTENSA
363	bool "Enable fast atomic syscalls"
364	default n
365	help
366	  fast_syscall_xtensa is a syscall that can make atomic operations
367	  on UP kernel when processor has no s32c1i support.
368
369	  This syscall is deprecated. It may have issues when called with
370	  invalid arguments. It is provided only for backwards compatibility.
371	  Only enable it if your userspace software requires it.
372
373	  If unsure, say N.
374
375config FAST_SYSCALL_SPILL_REGISTERS
376	bool "Enable spill registers syscall"
377	default n
378	help
379	  fast_syscall_spill_registers is a syscall that spills all active
380	  register windows of a calling userspace task onto its stack.
381
382	  This syscall is deprecated. It may have issues when called with
383	  invalid arguments. It is provided only for backwards compatibility.
384	  Only enable it if your userspace software requires it.
385
386	  If unsure, say N.
387
388config USER_ABI_CALL0
389	bool
390
391choice
392	prompt "Userspace ABI"
393	default USER_ABI_DEFAULT
394	help
395	  Select supported userspace ABI.
396
397	  If unsure, choose the default ABI.
398
399config USER_ABI_DEFAULT
400	bool "Default ABI only"
401	help
402	  Assume default userspace ABI. For XEA2 cores it is windowed ABI.
403	  call0 ABI binaries may be run on such kernel, but signal delivery
404	  will not work correctly for them.
405
406config USER_ABI_CALL0_ONLY
407	bool "Call0 ABI only"
408	select USER_ABI_CALL0
409	help
410	  Select this option to support only call0 ABI in userspace.
411	  Windowed ABI binaries will crash with a segfault caused by
412	  an illegal instruction exception on the first 'entry' opcode.
413
414	  Choose this option if you're planning to run only user code
415	  built with call0 ABI.
416
417config USER_ABI_CALL0_PROBE
418	bool "Support both windowed and call0 ABI by probing"
419	select USER_ABI_CALL0
420	help
421	  Select this option to support both windowed and call0 userspace
422	  ABIs. When enabled all processes are started with PS.WOE disabled
423	  and a fast user exception handler for an illegal instruction is
424	  used to turn on PS.WOE bit on the first 'entry' opcode executed by
425	  the userspace.
426
427	  This option should be enabled for the kernel that must support
428	  both call0 and windowed ABIs in userspace at the same time.
429
430	  Note that Xtensa ISA does not guarantee that entry opcode will
431	  raise an illegal instruction exception on cores with XEA2 when
432	  PS.WOE is disabled, check whether the target core supports it.
433
434endchoice
435
436endmenu
437
438config XTENSA_CALIBRATE_CCOUNT
439	def_bool n
440	help
441	  On some platforms (XT2000, for example), the CPU clock rate can
442	  vary.  The frequency can be determined, however, by measuring
443	  against a well known, fixed frequency, such as an UART oscillator.
444
445config SERIAL_CONSOLE
446	def_bool n
447
448menu "Platform options"
449
450choice
451	prompt "Xtensa System Type"
452	default XTENSA_PLATFORM_ISS
453
454config XTENSA_PLATFORM_ISS
455	bool "ISS"
456	select XTENSA_CALIBRATE_CCOUNT
457	select SERIAL_CONSOLE
458	help
459	  ISS is an acronym for Tensilica's Instruction Set Simulator.
460
461config XTENSA_PLATFORM_XT2000
462	bool "XT2000"
463	select HAVE_IDE
464	help
465	  XT2000 is the name of Tensilica's feature-rich emulation platform.
466	  This hardware is capable of running a full Linux distribution.
467
468config XTENSA_PLATFORM_XTFPGA
469	bool "XTFPGA"
470	select ETHOC if ETHERNET
471	select PLATFORM_WANT_DEFAULT_MEM if !MMU
472	select SERIAL_CONSOLE
473	select XTENSA_CALIBRATE_CCOUNT
474	help
475	  XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605).
476	  This hardware is capable of running a full Linux distribution.
477
478endchoice
479
480config PLATFORM_NR_IRQS
481	int
482	default 3 if XTENSA_PLATFORM_XT2000
483	default 0
484
485config XTENSA_CPU_CLOCK
486	int "CPU clock rate [MHz]"
487	depends on !XTENSA_CALIBRATE_CCOUNT
488	default 16
489
490config GENERIC_CALIBRATE_DELAY
491	bool "Auto calibration of the BogoMIPS value"
492	help
493	  The BogoMIPS value can easily be derived from the CPU frequency.
494
495config CMDLINE_BOOL
496	bool "Default bootloader kernel arguments"
497
498config CMDLINE
499	string "Initial kernel command string"
500	depends on CMDLINE_BOOL
501	default "console=ttyS0,38400 root=/dev/ram"
502	help
503	  On some architectures (EBSA110 and CATS), there is currently no way
504	  for the boot loader to pass arguments to the kernel. For these
505	  architectures, you should supply some command-line options at build
506	  time by entering them here. As a minimum, you should specify the
507	  memory size and the root device (e.g., mem=64M root=/dev/nfs).
508
509config USE_OF
510	bool "Flattened Device Tree support"
511	select OF
512	select OF_EARLY_FLATTREE
513	help
514	  Include support for flattened device tree machine descriptions.
515
516config BUILTIN_DTB_SOURCE
517	string "DTB to build into the kernel image"
518	depends on OF
519
520config PARSE_BOOTPARAM
521	bool "Parse bootparam block"
522	default y
523	help
524	  Parse parameters passed to the kernel from the bootloader. It may
525	  be disabled if the kernel is known to run without the bootloader.
526
527	  If unsure, say Y.
528
529config BLK_DEV_SIMDISK
530	tristate "Host file-based simulated block device support"
531	default n
532	depends on XTENSA_PLATFORM_ISS && BLOCK
533	help
534	  Create block devices that map to files in the host file system.
535	  Device binding to host file may be changed at runtime via proc
536	  interface provided the device is not in use.
537
538config BLK_DEV_SIMDISK_COUNT
539	int "Number of host file-based simulated block devices"
540	range 1 10
541	depends on BLK_DEV_SIMDISK
542	default 2
543	help
544	  This is the default minimal number of created block devices.
545	  Kernel/module parameter 'simdisk_count' may be used to change this
546	  value at runtime. More file names (but no more than 10) may be
547	  specified as parameters, simdisk_count grows accordingly.
548
549config SIMDISK0_FILENAME
550	string "Host filename for the first simulated device"
551	depends on BLK_DEV_SIMDISK = y
552	default ""
553	help
554	  Attach a first simdisk to a host file. Conventionally, this file
555	  contains a root file system.
556
557config SIMDISK1_FILENAME
558	string "Host filename for the second simulated device"
559	depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1
560	default ""
561	help
562	  Another simulated disk in a host file for a buildroot-independent
563	  storage.
564
565config FORCE_MAX_ZONEORDER
566	int "Maximum zone order"
567	default "11"
568	help
569	  The kernel memory allocator divides physically contiguous memory
570	  blocks into "zones", where each zone is a power of two number of
571	  pages.  This option selects the largest power of two that the kernel
572	  keeps in the memory allocator.  If you need to allocate very large
573	  blocks of physically contiguous memory, then you may need to
574	  increase this value.
575
576	  This config option is actually maximum order plus one. For example,
577	  a value of 11 means that the largest free memory block is 2^10 pages.
578
579config PLATFORM_WANT_DEFAULT_MEM
580	def_bool n
581
582config DEFAULT_MEM_START
583	hex
584	prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM
585	default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM
586	default 0x00000000
587	help
588	  This is the base address used for both PAGE_OFFSET and PHYS_OFFSET
589	  in noMMU configurations.
590
591	  If unsure, leave the default value here.
592
593config XTFPGA_LCD
594	bool "Enable XTFPGA LCD driver"
595	depends on XTENSA_PLATFORM_XTFPGA
596	default n
597	help
598	  There's a 2x16 LCD on most of XTFPGA boards, kernel may output
599	  progress messages there during bootup/shutdown. It may be useful
600	  during board bringup.
601
602	  If unsure, say N.
603
604config XTFPGA_LCD_BASE_ADDR
605	hex "XTFPGA LCD base address"
606	depends on XTFPGA_LCD
607	default "0x0d0c0000"
608	help
609	  Base address of the LCD controller inside KIO region.
610	  Different boards from XTFPGA family have LCD controller at different
611	  addresses. Please consult prototyping user guide for your board for
612	  the correct address. Wrong address here may lead to hardware lockup.
613
614config XTFPGA_LCD_8BIT_ACCESS
615	bool "Use 8-bit access to XTFPGA LCD"
616	depends on XTFPGA_LCD
617	default n
618	help
619	  LCD may be connected with 4- or 8-bit interface, 8-bit access may
620	  only be used with 8-bit interface. Please consult prototyping user
621	  guide for your board for the correct interface width.
622
623endmenu
624
625menu "Power management options"
626
627source "kernel/power/Kconfig"
628
629endmenu
630