1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * PKUnity Direct Memory Access Controller (DMAC) 4 */ 5 6 /* 7 * Interrupt Status Reg DMAC_ISR. 8 */ 9 #define DMAC_ISR (PKUNITY_DMAC_BASE + 0x0020) 10 /* 11 * Interrupt Transfer Complete Status Reg DMAC_ITCSR. 12 */ 13 #define DMAC_ITCSR (PKUNITY_DMAC_BASE + 0x0050) 14 /* 15 * Interrupt Transfer Complete Clear Reg DMAC_ITCCR. 16 */ 17 #define DMAC_ITCCR (PKUNITY_DMAC_BASE + 0x0060) 18 /* 19 * Interrupt Error Status Reg DMAC_IESR. 20 */ 21 #define DMAC_IESR (PKUNITY_DMAC_BASE + 0x0080) 22 /* 23 * Interrupt Error Clear Reg DMAC_IECR. 24 */ 25 #define DMAC_IECR (PKUNITY_DMAC_BASE + 0x0090) 26 /* 27 * Enable Channels Reg DMAC_ENCH. 28 */ 29 #define DMAC_ENCH (PKUNITY_DMAC_BASE + 0x00B0) 30 31 /* 32 * DMA control reg. Space [byte] 33 */ 34 #define DMASp 0x00000100 35 36 /* 37 * Source Addr DMAC_SRCADDR(ch). 38 */ 39 #define DMAC_SRCADDR(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x00) 40 /* 41 * Destination Addr DMAC_DESTADDR(ch). 42 */ 43 #define DMAC_DESTADDR(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x04) 44 /* 45 * Control Reg DMAC_CONTROL(ch). 46 */ 47 #define DMAC_CONTROL(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x0C) 48 /* 49 * Configuration Reg DMAC_CONFIG(ch). 50 */ 51 #define DMAC_CONFIG(ch) (PKUNITY_DMAC_BASE + (ch)*DMASp + 0x10) 52 53 #define DMAC_IR_MASK FMASK(6, 0) 54 /* 55 * select channel (ch) 56 */ 57 #define DMAC_CHANNEL(ch) FIELD(1, 1, (ch)) 58 59 #define DMAC_CONTROL_SIZE_BYTE(v) (FIELD((v), 12, 14) | \ 60 FIELD(0, 3, 9) | FIELD(0, 3, 6)) 61 #define DMAC_CONTROL_SIZE_HWORD(v) (FIELD((v) >> 1, 12, 14) | \ 62 FIELD(1, 3, 9) | FIELD(1, 3, 6)) 63 #define DMAC_CONTROL_SIZE_WORD(v) (FIELD((v) >> 2, 12, 14) | \ 64 FIELD(2, 3, 9) | FIELD(2, 3, 6)) 65 #define DMAC_CONTROL_DI FIELD(1, 1, 13) 66 #define DMAC_CONTROL_SI FIELD(1, 1, 12) 67 #define DMAC_CONTROL_BURST_1BYTE (FIELD(0, 3, 3) | FIELD(0, 3, 0)) 68 #define DMAC_CONTROL_BURST_4BYTE (FIELD(3, 3, 3) | FIELD(3, 3, 0)) 69 #define DMAC_CONTROL_BURST_8BYTE (FIELD(5, 3, 3) | FIELD(5, 3, 0)) 70 #define DMAC_CONTROL_BURST_16BYTE (FIELD(7, 3, 3) | FIELD(7, 3, 0)) 71 72 #define DMAC_CONFIG_UART0_WR (FIELD(2, 4, 11) | FIELD(1, 2, 1)) 73 #define DMAC_CONFIG_UART0_RD (FIELD(2, 4, 7) | FIELD(2, 2, 1)) 74 #define DMAC_CONFIG_UART1_WR (FIELD(3, 4, 11) | FIELD(1, 2, 1)) 75 #define DMAC_CONFIG_UART1RD (FIELD(3, 4, 7) | FIELD(2, 2, 1)) 76 #define DMAC_CONFIG_AC97WR (FIELD(4, 4, 11) | FIELD(1, 2, 1)) 77 #define DMAC_CONFIG_AC97RD (FIELD(4, 4, 7) | FIELD(2, 2, 1)) 78 #define DMAC_CONFIG_MMCWR (FIELD(7, 4, 11) | FIELD(1, 2, 1)) 79 #define DMAC_CONFIG_MMCRD (FIELD(7, 4, 7) | FIELD(2, 2, 1)) 80 #define DMAC_CONFIG_MASKITC FIELD(1, 1, 4) 81 #define DMAC_CONFIG_MASKIE FIELD(1, 1, 3) 82 #define DMAC_CONFIG_EN FIELD(1, 1, 0) 83