1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 4 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 5 */ 6 7 #ifndef __ARM_KVM_ARM_H__ 8 #define __ARM_KVM_ARM_H__ 9 10 #include <linux/const.h> 11 #include <linux/types.h> 12 13 /* Hyp Configuration Register (HCR) bits */ 14 #define HCR_TGE (1 << 27) 15 #define HCR_TVM (1 << 26) 16 #define HCR_TTLB (1 << 25) 17 #define HCR_TPU (1 << 24) 18 #define HCR_TPC (1 << 23) 19 #define HCR_TSW (1 << 22) 20 #define HCR_TAC (1 << 21) 21 #define HCR_TIDCP (1 << 20) 22 #define HCR_TSC (1 << 19) 23 #define HCR_TID3 (1 << 18) 24 #define HCR_TID2 (1 << 17) 25 #define HCR_TID1 (1 << 16) 26 #define HCR_TID0 (1 << 15) 27 #define HCR_TWE (1 << 14) 28 #define HCR_TWI (1 << 13) 29 #define HCR_DC (1 << 12) 30 #define HCR_BSU (3 << 10) 31 #define HCR_BSU_IS (1 << 10) 32 #define HCR_FB (1 << 9) 33 #define HCR_VA (1 << 8) 34 #define HCR_VI (1 << 7) 35 #define HCR_VF (1 << 6) 36 #define HCR_AMO (1 << 5) 37 #define HCR_IMO (1 << 4) 38 #define HCR_FMO (1 << 3) 39 #define HCR_PTW (1 << 2) 40 #define HCR_SWIO (1 << 1) 41 #define HCR_VM 1 42 43 /* 44 * The bits we set in HCR: 45 * TAC: Trap ACTLR 46 * TSC: Trap SMC 47 * TVM: Trap VM ops (until MMU and caches are on) 48 * TSW: Trap cache operations by set/way 49 * TWI: Trap WFI 50 * TWE: Trap WFE 51 * TIDCP: Trap L2CTLR/L2ECTLR 52 * BSU_IS: Upgrade barriers to the inner shareable domain 53 * FB: Force broadcast of all maintainance operations 54 * AMO: Override CPSR.A and enable signaling with VA 55 * IMO: Override CPSR.I and enable signaling with VI 56 * FMO: Override CPSR.F and enable signaling with VF 57 * SWIO: Turn set/way invalidates into set/way clean+invalidate 58 */ 59 #define HCR_GUEST_MASK (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \ 60 HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \ 61 HCR_TVM | HCR_TWE | HCR_SWIO | HCR_TIDCP) 62 63 /* System Control Register (SCTLR) bits */ 64 #define SCTLR_TE (1 << 30) 65 #define SCTLR_EE (1 << 25) 66 #define SCTLR_V (1 << 13) 67 68 /* Hyp System Control Register (HSCTLR) bits */ 69 #define HSCTLR_TE (1 << 30) 70 #define HSCTLR_EE (1 << 25) 71 #define HSCTLR_FI (1 << 21) 72 #define HSCTLR_WXN (1 << 19) 73 #define HSCTLR_I (1 << 12) 74 #define HSCTLR_C (1 << 2) 75 #define HSCTLR_A (1 << 1) 76 #define HSCTLR_M 1 77 #define HSCTLR_MASK (HSCTLR_M | HSCTLR_A | HSCTLR_C | HSCTLR_I | \ 78 HSCTLR_WXN | HSCTLR_FI | HSCTLR_EE | HSCTLR_TE) 79 80 /* TTBCR and HTCR Registers bits */ 81 #define TTBCR_EAE (1 << 31) 82 #define TTBCR_IMP (1 << 30) 83 #define TTBCR_SH1 (3 << 28) 84 #define TTBCR_ORGN1 (3 << 26) 85 #define TTBCR_IRGN1 (3 << 24) 86 #define TTBCR_EPD1 (1 << 23) 87 #define TTBCR_A1 (1 << 22) 88 #define TTBCR_T1SZ (7 << 16) 89 #define TTBCR_SH0 (3 << 12) 90 #define TTBCR_ORGN0 (3 << 10) 91 #define TTBCR_IRGN0 (3 << 8) 92 #define TTBCR_EPD0 (1 << 7) 93 #define TTBCR_T0SZ (7 << 0) 94 #define HTCR_MASK (TTBCR_T0SZ | TTBCR_IRGN0 | TTBCR_ORGN0 | TTBCR_SH0) 95 96 /* Hyp System Trap Register */ 97 #define HSTR_T(x) (1 << x) 98 #define HSTR_TTEE (1 << 16) 99 #define HSTR_TJDBX (1 << 17) 100 101 /* Hyp Coprocessor Trap Register */ 102 #define HCPTR_TCP(x) (1 << x) 103 #define HCPTR_TCP_MASK (0x3fff) 104 #define HCPTR_TASE (1 << 15) 105 #define HCPTR_TTA (1 << 20) 106 #define HCPTR_TCPAC (1 << 31) 107 108 /* Hyp Debug Configuration Register bits */ 109 #define HDCR_TDRA (1 << 11) 110 #define HDCR_TDOSA (1 << 10) 111 #define HDCR_TDA (1 << 9) 112 #define HDCR_TDE (1 << 8) 113 #define HDCR_HPME (1 << 7) 114 #define HDCR_TPM (1 << 6) 115 #define HDCR_TPMCR (1 << 5) 116 #define HDCR_HPMN_MASK (0x1F) 117 118 /* 119 * The architecture supports 40-bit IPA as input to the 2nd stage translations 120 * and PTRS_PER_S2_PGD becomes 1024, because each entry covers 1GB of address 121 * space. 122 */ 123 #define KVM_PHYS_SHIFT (40) 124 125 #define PTRS_PER_S2_PGD (_AC(1, ULL) << (KVM_PHYS_SHIFT - 30)) 126 127 /* Virtualization Translation Control Register (VTCR) bits */ 128 #define VTCR_SH0 (3 << 12) 129 #define VTCR_ORGN0 (3 << 10) 130 #define VTCR_IRGN0 (3 << 8) 131 #define VTCR_SL0 (3 << 6) 132 #define VTCR_S (1 << 4) 133 #define VTCR_T0SZ (0xf) 134 #define VTCR_MASK (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0 | VTCR_SL0 | \ 135 VTCR_S | VTCR_T0SZ) 136 #define VTCR_HTCR_SH (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0) 137 #define VTCR_SL_L2 (0 << 6) /* Starting-level: 2 */ 138 #define VTCR_SL_L1 (1 << 6) /* Starting-level: 1 */ 139 #define KVM_VTCR_SL0 VTCR_SL_L1 140 /* stage-2 input address range defined as 2^(32-T0SZ) */ 141 #define KVM_T0SZ (32 - KVM_PHYS_SHIFT) 142 #define KVM_VTCR_T0SZ (KVM_T0SZ & VTCR_T0SZ) 143 #define KVM_VTCR_S ((KVM_VTCR_T0SZ << 1) & VTCR_S) 144 145 /* Virtualization Translation Table Base Register (VTTBR) bits */ 146 #if KVM_VTCR_SL0 == VTCR_SL_L2 /* see ARM DDI 0406C: B4-1720 */ 147 #define VTTBR_X (14 - KVM_T0SZ) 148 #else 149 #define VTTBR_X (5 - KVM_T0SZ) 150 #endif 151 #define VTTBR_CNP_BIT _AC(1, UL) 152 #define VTTBR_BADDR_MASK (((_AC(1, ULL) << (40 - VTTBR_X)) - 1) << VTTBR_X) 153 #define VTTBR_VMID_SHIFT _AC(48, ULL) 154 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) 155 156 /* Hyp Syndrome Register (HSR) bits */ 157 #define HSR_EC_SHIFT (26) 158 #define HSR_EC (_AC(0x3f, UL) << HSR_EC_SHIFT) 159 #define HSR_IL (_AC(1, UL) << 25) 160 #define HSR_ISS (HSR_IL - 1) 161 #define HSR_ISV_SHIFT (24) 162 #define HSR_ISV (_AC(1, UL) << HSR_ISV_SHIFT) 163 #define HSR_SRT_SHIFT (16) 164 #define HSR_SRT_MASK (0xf << HSR_SRT_SHIFT) 165 #define HSR_FSC (0x3f) 166 #define HSR_FSC_TYPE (0x3c) 167 #define HSR_SSE (1 << 21) 168 #define HSR_WNR (1 << 6) 169 #define HSR_CV_SHIFT (24) 170 #define HSR_CV (_AC(1, UL) << HSR_CV_SHIFT) 171 #define HSR_COND_SHIFT (20) 172 #define HSR_COND (_AC(0xf, UL) << HSR_COND_SHIFT) 173 174 #define FSC_FAULT (0x04) 175 #define FSC_ACCESS (0x08) 176 #define FSC_PERM (0x0c) 177 #define FSC_SEA (0x10) 178 #define FSC_SEA_TTW0 (0x14) 179 #define FSC_SEA_TTW1 (0x15) 180 #define FSC_SEA_TTW2 (0x16) 181 #define FSC_SEA_TTW3 (0x17) 182 #define FSC_SECC (0x18) 183 #define FSC_SECC_TTW0 (0x1c) 184 #define FSC_SECC_TTW1 (0x1d) 185 #define FSC_SECC_TTW2 (0x1e) 186 #define FSC_SECC_TTW3 (0x1f) 187 188 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ 189 #define HPFAR_MASK (~0xf) 190 191 #define HSR_EC_UNKNOWN (0x00) 192 #define HSR_EC_WFI (0x01) 193 #define HSR_EC_CP15_32 (0x03) 194 #define HSR_EC_CP15_64 (0x04) 195 #define HSR_EC_CP14_MR (0x05) 196 #define HSR_EC_CP14_LS (0x06) 197 #define HSR_EC_CP_0_13 (0x07) 198 #define HSR_EC_CP10_ID (0x08) 199 #define HSR_EC_JAZELLE (0x09) 200 #define HSR_EC_BXJ (0x0A) 201 #define HSR_EC_CP14_64 (0x0C) 202 #define HSR_EC_SVC_HYP (0x11) 203 #define HSR_EC_HVC (0x12) 204 #define HSR_EC_SMC (0x13) 205 #define HSR_EC_IABT (0x20) 206 #define HSR_EC_IABT_HYP (0x21) 207 #define HSR_EC_DABT (0x24) 208 #define HSR_EC_DABT_HYP (0x25) 209 #define HSR_EC_MAX (0x3f) 210 211 #define HSR_WFI_IS_WFE (_AC(1, UL) << 0) 212 213 #define HSR_HVC_IMM_MASK ((_AC(1, UL) << 16) - 1) 214 215 #define HSR_DABT_S1PTW (_AC(1, UL) << 7) 216 #define HSR_DABT_CM (_AC(1, UL) << 8) 217 218 #define kvm_arm_exception_type \ 219 {0, "RESET" }, \ 220 {1, "UNDEFINED" }, \ 221 {2, "SOFTWARE" }, \ 222 {3, "PREF_ABORT" }, \ 223 {4, "DATA_ABORT" }, \ 224 {5, "IRQ" }, \ 225 {6, "FIQ" }, \ 226 {7, "HVC" } 227 228 #define HSRECN(x) { HSR_EC_##x, #x } 229 230 #define kvm_arm_exception_class \ 231 HSRECN(UNKNOWN), HSRECN(WFI), HSRECN(CP15_32), HSRECN(CP15_64), \ 232 HSRECN(CP14_MR), HSRECN(CP14_LS), HSRECN(CP_0_13), HSRECN(CP10_ID), \ 233 HSRECN(JAZELLE), HSRECN(BXJ), HSRECN(CP14_64), HSRECN(SVC_HYP), \ 234 HSRECN(HVC), HSRECN(SMC), HSRECN(IABT), HSRECN(IABT_HYP), \ 235 HSRECN(DABT), HSRECN(DABT_HYP) 236 237 238 #endif /* __ARM_KVM_ARM_H__ */ 239