1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_POWERPC_BOOK3S_64_HASH_4K_H
3 #define _ASM_POWERPC_BOOK3S_64_HASH_4K_H
4
5 #define H_PTE_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps: 2^9 x 4KB = 2MB
6 #define H_PMD_INDEX_SIZE 7 // size: 8B << 7 = 1KB, maps: 2^7 x 2MB = 256MB
7 #define H_PUD_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps: 2^9 x 256MB = 128GB
8 #define H_PGD_INDEX_SIZE 9 // size: 8B << 9 = 4KB, maps: 2^9 x 128GB = 64TB
9
10 /*
11 * Each context is 512TB. But on 4k we restrict our max TASK size to 64TB
12 * Hence also limit max EA bits to 64TB.
13 */
14 #define MAX_EA_BITS_PER_CONTEXT 46
15
16
17 /*
18 * Our page table limit us to 64TB. For 64TB physical memory, we only need 64GB
19 * of vmemmap space. To better support sparse memory layout, we use 61TB
20 * linear map range, 1TB of vmalloc, 1TB of I/O and 1TB of vmememmap.
21 */
22 #define REGION_SHIFT (40)
23 #define H_KERN_MAP_SIZE (ASM_CONST(1) << REGION_SHIFT)
24
25 /*
26 * Define the address range of the kernel non-linear virtual area (61TB)
27 */
28 #define H_KERN_VIRT_START ASM_CONST(0xc0003d0000000000)
29
30 #ifndef __ASSEMBLY__
31 #define H_PTE_TABLE_SIZE (sizeof(pte_t) << H_PTE_INDEX_SIZE)
32 #define H_PMD_TABLE_SIZE (sizeof(pmd_t) << H_PMD_INDEX_SIZE)
33 #define H_PUD_TABLE_SIZE (sizeof(pud_t) << H_PUD_INDEX_SIZE)
34 #define H_PGD_TABLE_SIZE (sizeof(pgd_t) << H_PGD_INDEX_SIZE)
35
36 #define H_PAGE_F_GIX_SHIFT 53
37 #define H_PAGE_F_SECOND _RPAGE_RPN44 /* HPTE is in 2ndary HPTEG */
38 #define H_PAGE_F_GIX (_RPAGE_RPN43 | _RPAGE_RPN42 | _RPAGE_RPN41)
39 #define H_PAGE_BUSY _RPAGE_RSV1 /* software: PTE & hash are busy */
40 #define H_PAGE_HASHPTE _RPAGE_RSV2 /* software: PTE & hash are busy */
41
42 /* PTE flags to conserve for HPTE identification */
43 #define _PAGE_HPTEFLAGS (H_PAGE_BUSY | H_PAGE_HASHPTE | \
44 H_PAGE_F_SECOND | H_PAGE_F_GIX)
45 /*
46 * Not supported by 4k linux page size
47 */
48 #define H_PAGE_4K_PFN 0x0
49 #define H_PAGE_THP_HUGE 0x0
50 #define H_PAGE_COMBO 0x0
51
52 /* 8 bytes per each pte entry */
53 #define H_PTE_FRAG_SIZE_SHIFT (H_PTE_INDEX_SIZE + 3)
54 #define H_PTE_FRAG_NR (PAGE_SIZE >> H_PTE_FRAG_SIZE_SHIFT)
55 #define H_PMD_FRAG_SIZE_SHIFT (H_PMD_INDEX_SIZE + 3)
56 #define H_PMD_FRAG_NR (PAGE_SIZE >> H_PMD_FRAG_SIZE_SHIFT)
57
58 /* memory key bits, only 8 keys supported */
59 #define H_PTE_PKEY_BIT0 0
60 #define H_PTE_PKEY_BIT1 0
61 #define H_PTE_PKEY_BIT2 _RPAGE_RSV3
62 #define H_PTE_PKEY_BIT3 _RPAGE_RSV4
63 #define H_PTE_PKEY_BIT4 _RPAGE_RSV5
64
65 /*
66 * On all 4K setups, remap_4k_pfn() equates to remap_pfn_range()
67 */
68 #define remap_4k_pfn(vma, addr, pfn, prot) \
69 remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
70
71 #ifdef CONFIG_HUGETLB_PAGE
hash__hugepd_ok(hugepd_t hpd)72 static inline int hash__hugepd_ok(hugepd_t hpd)
73 {
74 unsigned long hpdval = hpd_val(hpd);
75 /*
76 * if it is not a pte and have hugepd shift mask
77 * set, then it is a hugepd directory pointer
78 */
79 if (!(hpdval & _PAGE_PTE) && (hpdval & _PAGE_PRESENT) &&
80 ((hpdval & HUGEPD_SHIFT_MASK) != 0))
81 return true;
82 return false;
83 }
84 #endif
85
86 /*
87 * 4K PTE format is different from 64K PTE format. Saving the hash_slot is just
88 * a matter of returning the PTE bits that need to be modified. On 64K PTE,
89 * things are a little more involved and hence needs many more parameters to
90 * accomplish the same. However we want to abstract this out from the caller by
91 * keeping the prototype consistent across the two formats.
92 */
pte_set_hidx(pte_t * ptep,real_pte_t rpte,unsigned int subpg_index,unsigned long hidx,int offset)93 static inline unsigned long pte_set_hidx(pte_t *ptep, real_pte_t rpte,
94 unsigned int subpg_index, unsigned long hidx,
95 int offset)
96 {
97 return (hidx << H_PAGE_F_GIX_SHIFT) &
98 (H_PAGE_F_SECOND | H_PAGE_F_GIX);
99 }
100
101 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
102
get_hpte_slot_array(pmd_t * pmdp)103 static inline char *get_hpte_slot_array(pmd_t *pmdp)
104 {
105 BUG();
106 return NULL;
107 }
108
hpte_valid(unsigned char * hpte_slot_array,int index)109 static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index)
110 {
111 BUG();
112 return 0;
113 }
114
hpte_hash_index(unsigned char * hpte_slot_array,int index)115 static inline unsigned int hpte_hash_index(unsigned char *hpte_slot_array,
116 int index)
117 {
118 BUG();
119 return 0;
120 }
121
mark_hpte_slot_valid(unsigned char * hpte_slot_array,unsigned int index,unsigned int hidx)122 static inline void mark_hpte_slot_valid(unsigned char *hpte_slot_array,
123 unsigned int index, unsigned int hidx)
124 {
125 BUG();
126 }
127
hash__pmd_trans_huge(pmd_t pmd)128 static inline int hash__pmd_trans_huge(pmd_t pmd)
129 {
130 return 0;
131 }
132
hash__pmd_same(pmd_t pmd_a,pmd_t pmd_b)133 static inline int hash__pmd_same(pmd_t pmd_a, pmd_t pmd_b)
134 {
135 BUG();
136 return 0;
137 }
138
hash__pmd_mkhuge(pmd_t pmd)139 static inline pmd_t hash__pmd_mkhuge(pmd_t pmd)
140 {
141 BUG();
142 return pmd;
143 }
144
145 extern unsigned long hash__pmd_hugepage_update(struct mm_struct *mm,
146 unsigned long addr, pmd_t *pmdp,
147 unsigned long clr, unsigned long set);
148 extern pmd_t hash__pmdp_collapse_flush(struct vm_area_struct *vma,
149 unsigned long address, pmd_t *pmdp);
150 extern void hash__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
151 pgtable_t pgtable);
152 extern pgtable_t hash__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp);
153 extern pmd_t hash__pmdp_huge_get_and_clear(struct mm_struct *mm,
154 unsigned long addr, pmd_t *pmdp);
155 extern int hash__has_transparent_hugepage(void);
156 #endif
157
hash__pmd_mkdevmap(pmd_t pmd)158 static inline pmd_t hash__pmd_mkdevmap(pmd_t pmd)
159 {
160 BUG();
161 return pmd;
162 }
163
164 #endif /* !__ASSEMBLY__ */
165
166 #endif /* _ASM_POWERPC_BOOK3S_64_HASH_4K_H */
167