1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ASM_SH_CPU_SH5_IRQ_H 3 #define __ASM_SH_CPU_SH5_IRQ_H 4 5 /* 6 * include/asm-sh/cpu-sh5/irq.h 7 * 8 * Copyright (C) 2000, 2001 Paolo Alberelli 9 */ 10 11 12 /* 13 * Encoded IRQs are not considered worth to be supported. 14 * Main reason is that there's no per-encoded-interrupt 15 * enable/disable mechanism (as there was in SH3/4). 16 * An all enabled/all disabled is worth only if there's 17 * a cascaded IC to disable/enable/ack on. Until such 18 * IC is available there's no such support. 19 * 20 * Presumably Encoded IRQs may use extra IRQs beyond 64, 21 * below. Some logic must be added to cope with IRQ_IRL? 22 * in an exclusive way. 23 * 24 * Priorities are set at Platform level, when IRQ_IRL0-3 25 * are set to 0 Encoding is allowed. Otherwise it's not 26 * allowed. 27 */ 28 29 /* Independent IRQs */ 30 #define IRQ_IRL0 0 31 #define IRQ_IRL1 1 32 #define IRQ_IRL2 2 33 #define IRQ_IRL3 3 34 35 #define IRQ_INTA 4 36 #define IRQ_INTB 5 37 #define IRQ_INTC 6 38 #define IRQ_INTD 7 39 40 #define IRQ_SERR 12 41 #define IRQ_ERR 13 42 #define IRQ_PWR3 14 43 #define IRQ_PWR2 15 44 #define IRQ_PWR1 16 45 #define IRQ_PWR0 17 46 47 #define IRQ_DMTE0 18 48 #define IRQ_DMTE1 19 49 #define IRQ_DMTE2 20 50 #define IRQ_DMTE3 21 51 #define IRQ_DAERR 22 52 53 #define IRQ_TUNI0 32 54 #define IRQ_TUNI1 33 55 #define IRQ_TUNI2 34 56 #define IRQ_TICPI2 35 57 58 #define IRQ_ATI 36 59 #define IRQ_PRI 37 60 #define IRQ_CUI 38 61 62 #define IRQ_ERI 39 63 #define IRQ_RXI 40 64 #define IRQ_BRI 41 65 #define IRQ_TXI 42 66 67 #define IRQ_ITI 63 68 69 #define NR_INTC_IRQS 64 70 71 #ifdef CONFIG_SH_CAYMAN 72 #define NR_EXT_IRQS 32 73 #define START_EXT_IRQS 64 74 75 /* PCI bus 2 uses encoded external interrupts on the Cayman board */ 76 #define IRQ_P2INTA (START_EXT_IRQS + (3*8) + 0) 77 #define IRQ_P2INTB (START_EXT_IRQS + (3*8) + 1) 78 #define IRQ_P2INTC (START_EXT_IRQS + (3*8) + 2) 79 #define IRQ_P2INTD (START_EXT_IRQS + (3*8) + 3) 80 81 #define I8042_KBD_IRQ (START_EXT_IRQS + 2) 82 #define I8042_AUX_IRQ (START_EXT_IRQS + 6) 83 84 #define IRQ_CFCARD (START_EXT_IRQS + 7) 85 #define IRQ_PCMCIA (0) 86 87 #else 88 #define NR_EXT_IRQS 0 89 #endif 90 91 /* Default IRQs, fixed */ 92 #define TIMER_IRQ IRQ_TUNI0 93 #define RTC_IRQ IRQ_CUI 94 95 /* Default Priorities, Platform may choose differently */ 96 #define NO_PRIORITY 0 /* Disabled */ 97 #define TIMER_PRIORITY 2 98 #define RTC_PRIORITY TIMER_PRIORITY 99 #define SCIF_PRIORITY 3 100 #define INTD_PRIORITY 3 101 #define IRL3_PRIORITY 4 102 #define INTC_PRIORITY 6 103 #define IRL2_PRIORITY 7 104 #define INTB_PRIORITY 9 105 #define IRL1_PRIORITY 10 106 #define INTA_PRIORITY 12 107 #define IRL0_PRIORITY 13 108 #define TOP_PRIORITY 15 109 110 extern int intc_evt_to_irq[(0xE20/0x20)+1]; 111 extern int platform_int_priority[NR_INTC_IRQS]; 112 113 #endif /* __ASM_SH_CPU_SH5_IRQ_H */ 114