1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Performance events: 4 * 5 * Copyright (C) 2008-2009, Thomas Gleixner <tglx@linutronix.de> 6 * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar 7 * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra 8 * 9 * Data type definitions, declarations, prototypes. 10 * 11 * Started by: Thomas Gleixner and Ingo Molnar 12 * 13 * For licencing details see kernel-base/COPYING 14 */ 15 #ifndef _UAPI_LINUX_PERF_EVENT_H 16 #define _UAPI_LINUX_PERF_EVENT_H 17 18 #include <linux/types.h> 19 #include <linux/ioctl.h> 20 #include <asm/byteorder.h> 21 22 /* 23 * User-space ABI bits: 24 */ 25 26 /* 27 * attr.type 28 */ 29 enum perf_type_id { 30 PERF_TYPE_HARDWARE = 0, 31 PERF_TYPE_SOFTWARE = 1, 32 PERF_TYPE_TRACEPOINT = 2, 33 PERF_TYPE_HW_CACHE = 3, 34 PERF_TYPE_RAW = 4, 35 PERF_TYPE_BREAKPOINT = 5, 36 37 PERF_TYPE_MAX, /* non-ABI */ 38 }; 39 40 /* 41 * Generalized performance event event_id types, used by the 42 * attr.event_id parameter of the sys_perf_event_open() 43 * syscall: 44 */ 45 enum perf_hw_id { 46 /* 47 * Common hardware events, generalized by the kernel: 48 */ 49 PERF_COUNT_HW_CPU_CYCLES = 0, 50 PERF_COUNT_HW_INSTRUCTIONS = 1, 51 PERF_COUNT_HW_CACHE_REFERENCES = 2, 52 PERF_COUNT_HW_CACHE_MISSES = 3, 53 PERF_COUNT_HW_BRANCH_INSTRUCTIONS = 4, 54 PERF_COUNT_HW_BRANCH_MISSES = 5, 55 PERF_COUNT_HW_BUS_CYCLES = 6, 56 PERF_COUNT_HW_STALLED_CYCLES_FRONTEND = 7, 57 PERF_COUNT_HW_STALLED_CYCLES_BACKEND = 8, 58 PERF_COUNT_HW_REF_CPU_CYCLES = 9, 59 60 PERF_COUNT_HW_MAX, /* non-ABI */ 61 }; 62 63 /* 64 * Generalized hardware cache events: 65 * 66 * { L1-D, L1-I, LLC, ITLB, DTLB, BPU, NODE } x 67 * { read, write, prefetch } x 68 * { accesses, misses } 69 */ 70 enum perf_hw_cache_id { 71 PERF_COUNT_HW_CACHE_L1D = 0, 72 PERF_COUNT_HW_CACHE_L1I = 1, 73 PERF_COUNT_HW_CACHE_LL = 2, 74 PERF_COUNT_HW_CACHE_DTLB = 3, 75 PERF_COUNT_HW_CACHE_ITLB = 4, 76 PERF_COUNT_HW_CACHE_BPU = 5, 77 PERF_COUNT_HW_CACHE_NODE = 6, 78 79 PERF_COUNT_HW_CACHE_MAX, /* non-ABI */ 80 }; 81 82 enum perf_hw_cache_op_id { 83 PERF_COUNT_HW_CACHE_OP_READ = 0, 84 PERF_COUNT_HW_CACHE_OP_WRITE = 1, 85 PERF_COUNT_HW_CACHE_OP_PREFETCH = 2, 86 87 PERF_COUNT_HW_CACHE_OP_MAX, /* non-ABI */ 88 }; 89 90 enum perf_hw_cache_op_result_id { 91 PERF_COUNT_HW_CACHE_RESULT_ACCESS = 0, 92 PERF_COUNT_HW_CACHE_RESULT_MISS = 1, 93 94 PERF_COUNT_HW_CACHE_RESULT_MAX, /* non-ABI */ 95 }; 96 97 /* 98 * Special "software" events provided by the kernel, even if the hardware 99 * does not support performance events. These events measure various 100 * physical and sw events of the kernel (and allow the profiling of them as 101 * well): 102 */ 103 enum perf_sw_ids { 104 PERF_COUNT_SW_CPU_CLOCK = 0, 105 PERF_COUNT_SW_TASK_CLOCK = 1, 106 PERF_COUNT_SW_PAGE_FAULTS = 2, 107 PERF_COUNT_SW_CONTEXT_SWITCHES = 3, 108 PERF_COUNT_SW_CPU_MIGRATIONS = 4, 109 PERF_COUNT_SW_PAGE_FAULTS_MIN = 5, 110 PERF_COUNT_SW_PAGE_FAULTS_MAJ = 6, 111 PERF_COUNT_SW_ALIGNMENT_FAULTS = 7, 112 PERF_COUNT_SW_EMULATION_FAULTS = 8, 113 PERF_COUNT_SW_DUMMY = 9, 114 PERF_COUNT_SW_BPF_OUTPUT = 10, 115 116 PERF_COUNT_SW_MAX, /* non-ABI */ 117 }; 118 119 /* 120 * Bits that can be set in attr.sample_type to request information 121 * in the overflow packets. 122 */ 123 enum perf_event_sample_format { 124 PERF_SAMPLE_IP = 1U << 0, 125 PERF_SAMPLE_TID = 1U << 1, 126 PERF_SAMPLE_TIME = 1U << 2, 127 PERF_SAMPLE_ADDR = 1U << 3, 128 PERF_SAMPLE_READ = 1U << 4, 129 PERF_SAMPLE_CALLCHAIN = 1U << 5, 130 PERF_SAMPLE_ID = 1U << 6, 131 PERF_SAMPLE_CPU = 1U << 7, 132 PERF_SAMPLE_PERIOD = 1U << 8, 133 PERF_SAMPLE_STREAM_ID = 1U << 9, 134 PERF_SAMPLE_RAW = 1U << 10, 135 PERF_SAMPLE_BRANCH_STACK = 1U << 11, 136 PERF_SAMPLE_REGS_USER = 1U << 12, 137 PERF_SAMPLE_STACK_USER = 1U << 13, 138 PERF_SAMPLE_WEIGHT = 1U << 14, 139 PERF_SAMPLE_DATA_SRC = 1U << 15, 140 PERF_SAMPLE_IDENTIFIER = 1U << 16, 141 PERF_SAMPLE_TRANSACTION = 1U << 17, 142 PERF_SAMPLE_REGS_INTR = 1U << 18, 143 PERF_SAMPLE_PHYS_ADDR = 1U << 19, 144 145 PERF_SAMPLE_MAX = 1U << 20, /* non-ABI */ 146 147 __PERF_SAMPLE_CALLCHAIN_EARLY = 1ULL << 63, /* non-ABI; internal use */ 148 }; 149 150 /* 151 * values to program into branch_sample_type when PERF_SAMPLE_BRANCH is set 152 * 153 * If the user does not pass priv level information via branch_sample_type, 154 * the kernel uses the event's priv level. Branch and event priv levels do 155 * not have to match. Branch priv level is checked for permissions. 156 * 157 * The branch types can be combined, however BRANCH_ANY covers all types 158 * of branches and therefore it supersedes all the other types. 159 */ 160 enum perf_branch_sample_type_shift { 161 PERF_SAMPLE_BRANCH_USER_SHIFT = 0, /* user branches */ 162 PERF_SAMPLE_BRANCH_KERNEL_SHIFT = 1, /* kernel branches */ 163 PERF_SAMPLE_BRANCH_HV_SHIFT = 2, /* hypervisor branches */ 164 165 PERF_SAMPLE_BRANCH_ANY_SHIFT = 3, /* any branch types */ 166 PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT = 4, /* any call branch */ 167 PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT = 5, /* any return branch */ 168 PERF_SAMPLE_BRANCH_IND_CALL_SHIFT = 6, /* indirect calls */ 169 PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT = 7, /* transaction aborts */ 170 PERF_SAMPLE_BRANCH_IN_TX_SHIFT = 8, /* in transaction */ 171 PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */ 172 PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */ 173 174 PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */ 175 PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT = 12, /* indirect jumps */ 176 PERF_SAMPLE_BRANCH_CALL_SHIFT = 13, /* direct call */ 177 178 PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT = 14, /* no flags */ 179 PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT = 15, /* no cycles */ 180 181 PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT = 16, /* save branch type */ 182 183 PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */ 184 }; 185 186 enum perf_branch_sample_type { 187 PERF_SAMPLE_BRANCH_USER = 1U << PERF_SAMPLE_BRANCH_USER_SHIFT, 188 PERF_SAMPLE_BRANCH_KERNEL = 1U << PERF_SAMPLE_BRANCH_KERNEL_SHIFT, 189 PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT, 190 191 PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT, 192 PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT, 193 PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT, 194 PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT, 195 PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT, 196 PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT, 197 PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT, 198 PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT, 199 200 PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT, 201 PERF_SAMPLE_BRANCH_IND_JUMP = 1U << PERF_SAMPLE_BRANCH_IND_JUMP_SHIFT, 202 PERF_SAMPLE_BRANCH_CALL = 1U << PERF_SAMPLE_BRANCH_CALL_SHIFT, 203 204 PERF_SAMPLE_BRANCH_NO_FLAGS = 1U << PERF_SAMPLE_BRANCH_NO_FLAGS_SHIFT, 205 PERF_SAMPLE_BRANCH_NO_CYCLES = 1U << PERF_SAMPLE_BRANCH_NO_CYCLES_SHIFT, 206 207 PERF_SAMPLE_BRANCH_TYPE_SAVE = 208 1U << PERF_SAMPLE_BRANCH_TYPE_SAVE_SHIFT, 209 210 PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT, 211 }; 212 213 /* 214 * Common flow change classification 215 */ 216 enum { 217 PERF_BR_UNKNOWN = 0, /* unknown */ 218 PERF_BR_COND = 1, /* conditional */ 219 PERF_BR_UNCOND = 2, /* unconditional */ 220 PERF_BR_IND = 3, /* indirect */ 221 PERF_BR_CALL = 4, /* function call */ 222 PERF_BR_IND_CALL = 5, /* indirect function call */ 223 PERF_BR_RET = 6, /* function return */ 224 PERF_BR_SYSCALL = 7, /* syscall */ 225 PERF_BR_SYSRET = 8, /* syscall return */ 226 PERF_BR_COND_CALL = 9, /* conditional function call */ 227 PERF_BR_COND_RET = 10, /* conditional function return */ 228 PERF_BR_MAX, 229 }; 230 231 #define PERF_SAMPLE_BRANCH_PLM_ALL \ 232 (PERF_SAMPLE_BRANCH_USER|\ 233 PERF_SAMPLE_BRANCH_KERNEL|\ 234 PERF_SAMPLE_BRANCH_HV) 235 236 /* 237 * Values to determine ABI of the registers dump. 238 */ 239 enum perf_sample_regs_abi { 240 PERF_SAMPLE_REGS_ABI_NONE = 0, 241 PERF_SAMPLE_REGS_ABI_32 = 1, 242 PERF_SAMPLE_REGS_ABI_64 = 2, 243 }; 244 245 /* 246 * Values for the memory transaction event qualifier, mostly for 247 * abort events. Multiple bits can be set. 248 */ 249 enum { 250 PERF_TXN_ELISION = (1 << 0), /* From elision */ 251 PERF_TXN_TRANSACTION = (1 << 1), /* From transaction */ 252 PERF_TXN_SYNC = (1 << 2), /* Instruction is related */ 253 PERF_TXN_ASYNC = (1 << 3), /* Instruction not related */ 254 PERF_TXN_RETRY = (1 << 4), /* Retry possible */ 255 PERF_TXN_CONFLICT = (1 << 5), /* Conflict abort */ 256 PERF_TXN_CAPACITY_WRITE = (1 << 6), /* Capacity write abort */ 257 PERF_TXN_CAPACITY_READ = (1 << 7), /* Capacity read abort */ 258 259 PERF_TXN_MAX = (1 << 8), /* non-ABI */ 260 261 /* bits 32..63 are reserved for the abort code */ 262 263 PERF_TXN_ABORT_MASK = (0xffffffffULL << 32), 264 PERF_TXN_ABORT_SHIFT = 32, 265 }; 266 267 /* 268 * The format of the data returned by read() on a perf event fd, 269 * as specified by attr.read_format: 270 * 271 * struct read_format { 272 * { u64 value; 273 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 274 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 275 * { u64 id; } && PERF_FORMAT_ID 276 * { u64 lost; } && PERF_FORMAT_LOST 277 * } && !PERF_FORMAT_GROUP 278 * 279 * { u64 nr; 280 * { u64 time_enabled; } && PERF_FORMAT_TOTAL_TIME_ENABLED 281 * { u64 time_running; } && PERF_FORMAT_TOTAL_TIME_RUNNING 282 * { u64 value; 283 * { u64 id; } && PERF_FORMAT_ID 284 * { u64 lost; } && PERF_FORMAT_LOST 285 * } cntr[nr]; 286 * } && PERF_FORMAT_GROUP 287 * }; 288 */ 289 enum perf_event_read_format { 290 PERF_FORMAT_TOTAL_TIME_ENABLED = 1U << 0, 291 PERF_FORMAT_TOTAL_TIME_RUNNING = 1U << 1, 292 PERF_FORMAT_ID = 1U << 2, 293 PERF_FORMAT_GROUP = 1U << 3, 294 PERF_FORMAT_LOST = 1U << 4, 295 296 PERF_FORMAT_MAX = 1U << 5, /* non-ABI */ 297 }; 298 299 #define PERF_ATTR_SIZE_VER0 64 /* sizeof first published struct */ 300 #define PERF_ATTR_SIZE_VER1 72 /* add: config2 */ 301 #define PERF_ATTR_SIZE_VER2 80 /* add: branch_sample_type */ 302 #define PERF_ATTR_SIZE_VER3 96 /* add: sample_regs_user */ 303 /* add: sample_stack_user */ 304 #define PERF_ATTR_SIZE_VER4 104 /* add: sample_regs_intr */ 305 #define PERF_ATTR_SIZE_VER5 112 /* add: aux_watermark */ 306 307 /* 308 * Hardware event_id to monitor via a performance monitoring event: 309 * 310 * @sample_max_stack: Max number of frame pointers in a callchain, 311 * should be < /proc/sys/kernel/perf_event_max_stack 312 */ 313 struct perf_event_attr { 314 315 /* 316 * Major type: hardware/software/tracepoint/etc. 317 */ 318 __u32 type; 319 320 /* 321 * Size of the attr structure, for fwd/bwd compat. 322 */ 323 __u32 size; 324 325 /* 326 * Type specific configuration information. 327 */ 328 __u64 config; 329 330 union { 331 __u64 sample_period; 332 __u64 sample_freq; 333 }; 334 335 __u64 sample_type; 336 __u64 read_format; 337 338 __u64 disabled : 1, /* off by default */ 339 inherit : 1, /* children inherit it */ 340 pinned : 1, /* must always be on PMU */ 341 exclusive : 1, /* only group on PMU */ 342 exclude_user : 1, /* don't count user */ 343 exclude_kernel : 1, /* ditto kernel */ 344 exclude_hv : 1, /* ditto hypervisor */ 345 exclude_idle : 1, /* don't count when idle */ 346 mmap : 1, /* include mmap data */ 347 comm : 1, /* include comm data */ 348 freq : 1, /* use freq, not period */ 349 inherit_stat : 1, /* per task counts */ 350 enable_on_exec : 1, /* next exec enables */ 351 task : 1, /* trace fork/exit */ 352 watermark : 1, /* wakeup_watermark */ 353 /* 354 * precise_ip: 355 * 356 * 0 - SAMPLE_IP can have arbitrary skid 357 * 1 - SAMPLE_IP must have constant skid 358 * 2 - SAMPLE_IP requested to have 0 skid 359 * 3 - SAMPLE_IP must have 0 skid 360 * 361 * See also PERF_RECORD_MISC_EXACT_IP 362 */ 363 precise_ip : 2, /* skid constraint */ 364 mmap_data : 1, /* non-exec mmap data */ 365 sample_id_all : 1, /* sample_type all events */ 366 367 exclude_host : 1, /* don't count in host */ 368 exclude_guest : 1, /* don't count in guest */ 369 370 exclude_callchain_kernel : 1, /* exclude kernel callchains */ 371 exclude_callchain_user : 1, /* exclude user callchains */ 372 mmap2 : 1, /* include mmap with inode data */ 373 comm_exec : 1, /* flag comm events that are due to an exec */ 374 use_clockid : 1, /* use @clockid for time fields */ 375 context_switch : 1, /* context switch data */ 376 write_backward : 1, /* Write ring buffer from end to beginning */ 377 namespaces : 1, /* include namespaces data */ 378 ksymbol : 1, /* include ksymbol events */ 379 bpf_event : 1, /* include bpf events */ 380 aux_output : 1, /* generate AUX records instead of events */ 381 __reserved_1 : 32; 382 383 union { 384 __u32 wakeup_events; /* wakeup every n events */ 385 __u32 wakeup_watermark; /* bytes before wakeup */ 386 }; 387 388 __u32 bp_type; 389 union { 390 __u64 bp_addr; 391 __u64 kprobe_func; /* for perf_kprobe */ 392 __u64 uprobe_path; /* for perf_uprobe */ 393 __u64 config1; /* extension of config */ 394 }; 395 union { 396 __u64 bp_len; 397 __u64 kprobe_addr; /* when kprobe_func == NULL */ 398 __u64 probe_offset; /* for perf_[k,u]probe */ 399 __u64 config2; /* extension of config1 */ 400 }; 401 __u64 branch_sample_type; /* enum perf_branch_sample_type */ 402 403 /* 404 * Defines set of user regs to dump on samples. 405 * See asm/perf_regs.h for details. 406 */ 407 __u64 sample_regs_user; 408 409 /* 410 * Defines size of the user stack to dump on samples. 411 */ 412 __u32 sample_stack_user; 413 414 __s32 clockid; 415 /* 416 * Defines set of regs to dump for each sample 417 * state captured on: 418 * - precise = 0: PMU interrupt 419 * - precise > 0: sampled instruction 420 * 421 * See asm/perf_regs.h for details. 422 */ 423 __u64 sample_regs_intr; 424 425 /* 426 * Wakeup watermark for AUX area 427 */ 428 __u32 aux_watermark; 429 __u16 sample_max_stack; 430 __u16 __reserved_2; /* align to __u64 */ 431 }; 432 433 /* 434 * Structure used by below PERF_EVENT_IOC_QUERY_BPF command 435 * to query bpf programs attached to the same perf tracepoint 436 * as the given perf event. 437 */ 438 struct perf_event_query_bpf { 439 /* 440 * The below ids array length 441 */ 442 __u32 ids_len; 443 /* 444 * Set by the kernel to indicate the number of 445 * available programs 446 */ 447 __u32 prog_cnt; 448 /* 449 * User provided buffer to store program ids 450 */ 451 __u32 ids[0]; 452 }; 453 454 /* 455 * Ioctls that can be done on a perf event fd: 456 */ 457 #define PERF_EVENT_IOC_ENABLE _IO ('$', 0) 458 #define PERF_EVENT_IOC_DISABLE _IO ('$', 1) 459 #define PERF_EVENT_IOC_REFRESH _IO ('$', 2) 460 #define PERF_EVENT_IOC_RESET _IO ('$', 3) 461 #define PERF_EVENT_IOC_PERIOD _IOW('$', 4, __u64) 462 #define PERF_EVENT_IOC_SET_OUTPUT _IO ('$', 5) 463 #define PERF_EVENT_IOC_SET_FILTER _IOW('$', 6, char *) 464 #define PERF_EVENT_IOC_ID _IOR('$', 7, __u64 *) 465 #define PERF_EVENT_IOC_SET_BPF _IOW('$', 8, __u32) 466 #define PERF_EVENT_IOC_PAUSE_OUTPUT _IOW('$', 9, __u32) 467 #define PERF_EVENT_IOC_QUERY_BPF _IOWR('$', 10, struct perf_event_query_bpf *) 468 #define PERF_EVENT_IOC_MODIFY_ATTRIBUTES _IOW('$', 11, struct perf_event_attr *) 469 470 enum perf_event_ioc_flags { 471 PERF_IOC_FLAG_GROUP = 1U << 0, 472 }; 473 474 /* 475 * Structure of the page that can be mapped via mmap 476 */ 477 struct perf_event_mmap_page { 478 __u32 version; /* version number of this structure */ 479 __u32 compat_version; /* lowest version this is compat with */ 480 481 /* 482 * Bits needed to read the hw events in user-space. 483 * 484 * u32 seq, time_mult, time_shift, index, width; 485 * u64 count, enabled, running; 486 * u64 cyc, time_offset; 487 * s64 pmc = 0; 488 * 489 * do { 490 * seq = pc->lock; 491 * barrier() 492 * 493 * enabled = pc->time_enabled; 494 * running = pc->time_running; 495 * 496 * if (pc->cap_usr_time && enabled != running) { 497 * cyc = rdtsc(); 498 * time_offset = pc->time_offset; 499 * time_mult = pc->time_mult; 500 * time_shift = pc->time_shift; 501 * } 502 * 503 * index = pc->index; 504 * count = pc->offset; 505 * if (pc->cap_user_rdpmc && index) { 506 * width = pc->pmc_width; 507 * pmc = rdpmc(index - 1); 508 * } 509 * 510 * barrier(); 511 * } while (pc->lock != seq); 512 * 513 * NOTE: for obvious reason this only works on self-monitoring 514 * processes. 515 */ 516 __u32 lock; /* seqlock for synchronization */ 517 __u32 index; /* hardware event identifier */ 518 __s64 offset; /* add to hardware event value */ 519 __u64 time_enabled; /* time event active */ 520 __u64 time_running; /* time event on cpu */ 521 union { 522 __u64 capabilities; 523 struct { 524 __u64 cap_bit0 : 1, /* Always 0, deprecated, see commit 860f085b74e9 */ 525 cap_bit0_is_deprecated : 1, /* Always 1, signals that bit 0 is zero */ 526 527 cap_user_rdpmc : 1, /* The RDPMC instruction can be used to read counts */ 528 cap_user_time : 1, /* The time_* fields are used */ 529 cap_user_time_zero : 1, /* The time_zero field is used */ 530 cap_____res : 59; 531 }; 532 }; 533 534 /* 535 * If cap_user_rdpmc this field provides the bit-width of the value 536 * read using the rdpmc() or equivalent instruction. This can be used 537 * to sign extend the result like: 538 * 539 * pmc <<= 64 - width; 540 * pmc >>= 64 - width; // signed shift right 541 * count += pmc; 542 */ 543 __u16 pmc_width; 544 545 /* 546 * If cap_usr_time the below fields can be used to compute the time 547 * delta since time_enabled (in ns) using rdtsc or similar. 548 * 549 * u64 quot, rem; 550 * u64 delta; 551 * 552 * quot = (cyc >> time_shift); 553 * rem = cyc & (((u64)1 << time_shift) - 1); 554 * delta = time_offset + quot * time_mult + 555 * ((rem * time_mult) >> time_shift); 556 * 557 * Where time_offset,time_mult,time_shift and cyc are read in the 558 * seqcount loop described above. This delta can then be added to 559 * enabled and possible running (if index), improving the scaling: 560 * 561 * enabled += delta; 562 * if (index) 563 * running += delta; 564 * 565 * quot = count / running; 566 * rem = count % running; 567 * count = quot * enabled + (rem * enabled) / running; 568 */ 569 __u16 time_shift; 570 __u32 time_mult; 571 __u64 time_offset; 572 /* 573 * If cap_usr_time_zero, the hardware clock (e.g. TSC) can be calculated 574 * from sample timestamps. 575 * 576 * time = timestamp - time_zero; 577 * quot = time / time_mult; 578 * rem = time % time_mult; 579 * cyc = (quot << time_shift) + (rem << time_shift) / time_mult; 580 * 581 * And vice versa: 582 * 583 * quot = cyc >> time_shift; 584 * rem = cyc & (((u64)1 << time_shift) - 1); 585 * timestamp = time_zero + quot * time_mult + 586 * ((rem * time_mult) >> time_shift); 587 */ 588 __u64 time_zero; 589 __u32 size; /* Header size up to __reserved[] fields. */ 590 591 /* 592 * Hole for extension of the self monitor capabilities 593 */ 594 595 __u8 __reserved[118*8+4]; /* align to 1k. */ 596 597 /* 598 * Control data for the mmap() data buffer. 599 * 600 * User-space reading the @data_head value should issue an smp_rmb(), 601 * after reading this value. 602 * 603 * When the mapping is PROT_WRITE the @data_tail value should be 604 * written by userspace to reflect the last read data, after issueing 605 * an smp_mb() to separate the data read from the ->data_tail store. 606 * In this case the kernel will not over-write unread data. 607 * 608 * See perf_output_put_handle() for the data ordering. 609 * 610 * data_{offset,size} indicate the location and size of the perf record 611 * buffer within the mmapped area. 612 */ 613 __u64 data_head; /* head in the data section */ 614 __u64 data_tail; /* user-space written tail */ 615 __u64 data_offset; /* where the buffer starts */ 616 __u64 data_size; /* data buffer size */ 617 618 /* 619 * AUX area is defined by aux_{offset,size} fields that should be set 620 * by the userspace, so that 621 * 622 * aux_offset >= data_offset + data_size 623 * 624 * prior to mmap()ing it. Size of the mmap()ed area should be aux_size. 625 * 626 * Ring buffer pointers aux_{head,tail} have the same semantics as 627 * data_{head,tail} and same ordering rules apply. 628 */ 629 __u64 aux_head; 630 __u64 aux_tail; 631 __u64 aux_offset; 632 __u64 aux_size; 633 }; 634 635 #define PERF_RECORD_MISC_CPUMODE_MASK (7 << 0) 636 #define PERF_RECORD_MISC_CPUMODE_UNKNOWN (0 << 0) 637 #define PERF_RECORD_MISC_KERNEL (1 << 0) 638 #define PERF_RECORD_MISC_USER (2 << 0) 639 #define PERF_RECORD_MISC_HYPERVISOR (3 << 0) 640 #define PERF_RECORD_MISC_GUEST_KERNEL (4 << 0) 641 #define PERF_RECORD_MISC_GUEST_USER (5 << 0) 642 643 /* 644 * Indicates that /proc/PID/maps parsing are truncated by time out. 645 */ 646 #define PERF_RECORD_MISC_PROC_MAP_PARSE_TIMEOUT (1 << 12) 647 /* 648 * Following PERF_RECORD_MISC_* are used on different 649 * events, so can reuse the same bit position: 650 * 651 * PERF_RECORD_MISC_MMAP_DATA - PERF_RECORD_MMAP* events 652 * PERF_RECORD_MISC_COMM_EXEC - PERF_RECORD_COMM event 653 * PERF_RECORD_MISC_FORK_EXEC - PERF_RECORD_FORK event (perf internal) 654 * PERF_RECORD_MISC_SWITCH_OUT - PERF_RECORD_SWITCH* events 655 */ 656 #define PERF_RECORD_MISC_MMAP_DATA (1 << 13) 657 #define PERF_RECORD_MISC_COMM_EXEC (1 << 13) 658 #define PERF_RECORD_MISC_FORK_EXEC (1 << 13) 659 #define PERF_RECORD_MISC_SWITCH_OUT (1 << 13) 660 /* 661 * These PERF_RECORD_MISC_* flags below are safely reused 662 * for the following events: 663 * 664 * PERF_RECORD_MISC_EXACT_IP - PERF_RECORD_SAMPLE of precise events 665 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT - PERF_RECORD_SWITCH* events 666 * 667 * 668 * PERF_RECORD_MISC_EXACT_IP: 669 * Indicates that the content of PERF_SAMPLE_IP points to 670 * the actual instruction that triggered the event. See also 671 * perf_event_attr::precise_ip. 672 * 673 * PERF_RECORD_MISC_SWITCH_OUT_PREEMPT: 674 * Indicates that thread was preempted in TASK_RUNNING state. 675 */ 676 #define PERF_RECORD_MISC_EXACT_IP (1 << 14) 677 #define PERF_RECORD_MISC_SWITCH_OUT_PREEMPT (1 << 14) 678 /* 679 * Reserve the last bit to indicate some extended misc field 680 */ 681 #define PERF_RECORD_MISC_EXT_RESERVED (1 << 15) 682 683 struct perf_event_header { 684 __u32 type; 685 __u16 misc; 686 __u16 size; 687 }; 688 689 struct perf_ns_link_info { 690 __u64 dev; 691 __u64 ino; 692 }; 693 694 enum { 695 NET_NS_INDEX = 0, 696 UTS_NS_INDEX = 1, 697 IPC_NS_INDEX = 2, 698 PID_NS_INDEX = 3, 699 USER_NS_INDEX = 4, 700 MNT_NS_INDEX = 5, 701 CGROUP_NS_INDEX = 6, 702 703 NR_NAMESPACES, /* number of available namespaces */ 704 }; 705 706 enum perf_event_type { 707 708 /* 709 * If perf_event_attr.sample_id_all is set then all event types will 710 * have the sample_type selected fields related to where/when 711 * (identity) an event took place (TID, TIME, ID, STREAM_ID, CPU, 712 * IDENTIFIER) described in PERF_RECORD_SAMPLE below, it will be stashed 713 * just after the perf_event_header and the fields already present for 714 * the existing fields, i.e. at the end of the payload. That way a newer 715 * perf.data file will be supported by older perf tools, with these new 716 * optional fields being ignored. 717 * 718 * struct sample_id { 719 * { u32 pid, tid; } && PERF_SAMPLE_TID 720 * { u64 time; } && PERF_SAMPLE_TIME 721 * { u64 id; } && PERF_SAMPLE_ID 722 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 723 * { u32 cpu, res; } && PERF_SAMPLE_CPU 724 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 725 * } && perf_event_attr::sample_id_all 726 * 727 * Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. The 728 * advantage of PERF_SAMPLE_IDENTIFIER is that its position is fixed 729 * relative to header.size. 730 */ 731 732 /* 733 * The MMAP events record the PROT_EXEC mappings so that we can 734 * correlate userspace IPs to code. They have the following structure: 735 * 736 * struct { 737 * struct perf_event_header header; 738 * 739 * u32 pid, tid; 740 * u64 addr; 741 * u64 len; 742 * u64 pgoff; 743 * char filename[]; 744 * struct sample_id sample_id; 745 * }; 746 */ 747 PERF_RECORD_MMAP = 1, 748 749 /* 750 * struct { 751 * struct perf_event_header header; 752 * u64 id; 753 * u64 lost; 754 * struct sample_id sample_id; 755 * }; 756 */ 757 PERF_RECORD_LOST = 2, 758 759 /* 760 * struct { 761 * struct perf_event_header header; 762 * 763 * u32 pid, tid; 764 * char comm[]; 765 * struct sample_id sample_id; 766 * }; 767 */ 768 PERF_RECORD_COMM = 3, 769 770 /* 771 * struct { 772 * struct perf_event_header header; 773 * u32 pid, ppid; 774 * u32 tid, ptid; 775 * u64 time; 776 * struct sample_id sample_id; 777 * }; 778 */ 779 PERF_RECORD_EXIT = 4, 780 781 /* 782 * struct { 783 * struct perf_event_header header; 784 * u64 time; 785 * u64 id; 786 * u64 stream_id; 787 * struct sample_id sample_id; 788 * }; 789 */ 790 PERF_RECORD_THROTTLE = 5, 791 PERF_RECORD_UNTHROTTLE = 6, 792 793 /* 794 * struct { 795 * struct perf_event_header header; 796 * u32 pid, ppid; 797 * u32 tid, ptid; 798 * u64 time; 799 * struct sample_id sample_id; 800 * }; 801 */ 802 PERF_RECORD_FORK = 7, 803 804 /* 805 * struct { 806 * struct perf_event_header header; 807 * u32 pid, tid; 808 * 809 * struct read_format values; 810 * struct sample_id sample_id; 811 * }; 812 */ 813 PERF_RECORD_READ = 8, 814 815 /* 816 * struct { 817 * struct perf_event_header header; 818 * 819 * # 820 * # Note that PERF_SAMPLE_IDENTIFIER duplicates PERF_SAMPLE_ID. 821 * # The advantage of PERF_SAMPLE_IDENTIFIER is that its position 822 * # is fixed relative to header. 823 * # 824 * 825 * { u64 id; } && PERF_SAMPLE_IDENTIFIER 826 * { u64 ip; } && PERF_SAMPLE_IP 827 * { u32 pid, tid; } && PERF_SAMPLE_TID 828 * { u64 time; } && PERF_SAMPLE_TIME 829 * { u64 addr; } && PERF_SAMPLE_ADDR 830 * { u64 id; } && PERF_SAMPLE_ID 831 * { u64 stream_id;} && PERF_SAMPLE_STREAM_ID 832 * { u32 cpu, res; } && PERF_SAMPLE_CPU 833 * { u64 period; } && PERF_SAMPLE_PERIOD 834 * 835 * { struct read_format values; } && PERF_SAMPLE_READ 836 * 837 * { u64 nr, 838 * u64 ips[nr]; } && PERF_SAMPLE_CALLCHAIN 839 * 840 * # 841 * # The RAW record below is opaque data wrt the ABI 842 * # 843 * # That is, the ABI doesn't make any promises wrt to 844 * # the stability of its content, it may vary depending 845 * # on event, hardware, kernel version and phase of 846 * # the moon. 847 * # 848 * # In other words, PERF_SAMPLE_RAW contents are not an ABI. 849 * # 850 * 851 * { u32 size; 852 * char data[size];}&& PERF_SAMPLE_RAW 853 * 854 * { u64 nr; 855 * { u64 from, to, flags } lbr[nr];} && PERF_SAMPLE_BRANCH_STACK 856 * 857 * { u64 abi; # enum perf_sample_regs_abi 858 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER 859 * 860 * { u64 size; 861 * char data[size]; 862 * u64 dyn_size; } && PERF_SAMPLE_STACK_USER 863 * 864 * { u64 weight; } && PERF_SAMPLE_WEIGHT 865 * { u64 data_src; } && PERF_SAMPLE_DATA_SRC 866 * { u64 transaction; } && PERF_SAMPLE_TRANSACTION 867 * { u64 abi; # enum perf_sample_regs_abi 868 * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR 869 * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR 870 * }; 871 */ 872 PERF_RECORD_SAMPLE = 9, 873 874 /* 875 * The MMAP2 records are an augmented version of MMAP, they add 876 * maj, min, ino numbers to be used to uniquely identify each mapping 877 * 878 * struct { 879 * struct perf_event_header header; 880 * 881 * u32 pid, tid; 882 * u64 addr; 883 * u64 len; 884 * u64 pgoff; 885 * u32 maj; 886 * u32 min; 887 * u64 ino; 888 * u64 ino_generation; 889 * u32 prot, flags; 890 * char filename[]; 891 * struct sample_id sample_id; 892 * }; 893 */ 894 PERF_RECORD_MMAP2 = 10, 895 896 /* 897 * Records that new data landed in the AUX buffer part. 898 * 899 * struct { 900 * struct perf_event_header header; 901 * 902 * u64 aux_offset; 903 * u64 aux_size; 904 * u64 flags; 905 * struct sample_id sample_id; 906 * }; 907 */ 908 PERF_RECORD_AUX = 11, 909 910 /* 911 * Indicates that instruction trace has started 912 * 913 * struct { 914 * struct perf_event_header header; 915 * u32 pid; 916 * u32 tid; 917 * struct sample_id sample_id; 918 * }; 919 */ 920 PERF_RECORD_ITRACE_START = 12, 921 922 /* 923 * Records the dropped/lost sample number. 924 * 925 * struct { 926 * struct perf_event_header header; 927 * 928 * u64 lost; 929 * struct sample_id sample_id; 930 * }; 931 */ 932 PERF_RECORD_LOST_SAMPLES = 13, 933 934 /* 935 * Records a context switch in or out (flagged by 936 * PERF_RECORD_MISC_SWITCH_OUT). See also 937 * PERF_RECORD_SWITCH_CPU_WIDE. 938 * 939 * struct { 940 * struct perf_event_header header; 941 * struct sample_id sample_id; 942 * }; 943 */ 944 PERF_RECORD_SWITCH = 14, 945 946 /* 947 * CPU-wide version of PERF_RECORD_SWITCH with next_prev_pid and 948 * next_prev_tid that are the next (switching out) or previous 949 * (switching in) pid/tid. 950 * 951 * struct { 952 * struct perf_event_header header; 953 * u32 next_prev_pid; 954 * u32 next_prev_tid; 955 * struct sample_id sample_id; 956 * }; 957 */ 958 PERF_RECORD_SWITCH_CPU_WIDE = 15, 959 960 /* 961 * struct { 962 * struct perf_event_header header; 963 * u32 pid; 964 * u32 tid; 965 * u64 nr_namespaces; 966 * { u64 dev, inode; } [nr_namespaces]; 967 * struct sample_id sample_id; 968 * }; 969 */ 970 PERF_RECORD_NAMESPACES = 16, 971 972 /* 973 * Record ksymbol register/unregister events: 974 * 975 * struct { 976 * struct perf_event_header header; 977 * u64 addr; 978 * u32 len; 979 * u16 ksym_type; 980 * u16 flags; 981 * char name[]; 982 * struct sample_id sample_id; 983 * }; 984 */ 985 PERF_RECORD_KSYMBOL = 17, 986 987 /* 988 * Record bpf events: 989 * enum perf_bpf_event_type { 990 * PERF_BPF_EVENT_UNKNOWN = 0, 991 * PERF_BPF_EVENT_PROG_LOAD = 1, 992 * PERF_BPF_EVENT_PROG_UNLOAD = 2, 993 * }; 994 * 995 * struct { 996 * struct perf_event_header header; 997 * u16 type; 998 * u16 flags; 999 * u32 id; 1000 * u8 tag[BPF_TAG_SIZE]; 1001 * struct sample_id sample_id; 1002 * }; 1003 */ 1004 PERF_RECORD_BPF_EVENT = 18, 1005 1006 PERF_RECORD_MAX, /* non-ABI */ 1007 }; 1008 1009 enum perf_record_ksymbol_type { 1010 PERF_RECORD_KSYMBOL_TYPE_UNKNOWN = 0, 1011 PERF_RECORD_KSYMBOL_TYPE_BPF = 1, 1012 PERF_RECORD_KSYMBOL_TYPE_MAX /* non-ABI */ 1013 }; 1014 1015 #define PERF_RECORD_KSYMBOL_FLAGS_UNREGISTER (1 << 0) 1016 1017 enum perf_bpf_event_type { 1018 PERF_BPF_EVENT_UNKNOWN = 0, 1019 PERF_BPF_EVENT_PROG_LOAD = 1, 1020 PERF_BPF_EVENT_PROG_UNLOAD = 2, 1021 PERF_BPF_EVENT_MAX, /* non-ABI */ 1022 }; 1023 1024 #define PERF_MAX_STACK_DEPTH 127 1025 #define PERF_MAX_CONTEXTS_PER_STACK 8 1026 1027 enum perf_callchain_context { 1028 PERF_CONTEXT_HV = (__u64)-32, 1029 PERF_CONTEXT_KERNEL = (__u64)-128, 1030 PERF_CONTEXT_USER = (__u64)-512, 1031 1032 PERF_CONTEXT_GUEST = (__u64)-2048, 1033 PERF_CONTEXT_GUEST_KERNEL = (__u64)-2176, 1034 PERF_CONTEXT_GUEST_USER = (__u64)-2560, 1035 1036 PERF_CONTEXT_MAX = (__u64)-4095, 1037 }; 1038 1039 /** 1040 * PERF_RECORD_AUX::flags bits 1041 */ 1042 #define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */ 1043 #define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */ 1044 #define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */ 1045 #define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */ 1046 1047 #define PERF_FLAG_FD_NO_GROUP (1UL << 0) 1048 #define PERF_FLAG_FD_OUTPUT (1UL << 1) 1049 #define PERF_FLAG_PID_CGROUP (1UL << 2) /* pid=cgroup id, per-cpu mode only */ 1050 #define PERF_FLAG_FD_CLOEXEC (1UL << 3) /* O_CLOEXEC */ 1051 1052 #if defined(__LITTLE_ENDIAN_BITFIELD) 1053 union perf_mem_data_src { 1054 __u64 val; 1055 struct { 1056 __u64 mem_op:5, /* type of opcode */ 1057 mem_lvl:14, /* memory hierarchy level */ 1058 mem_snoop:5, /* snoop mode */ 1059 mem_lock:2, /* lock instr */ 1060 mem_dtlb:7, /* tlb access */ 1061 mem_lvl_num:4, /* memory hierarchy level number */ 1062 mem_remote:1, /* remote */ 1063 mem_snoopx:2, /* snoop mode, ext */ 1064 mem_rsvd:24; 1065 }; 1066 }; 1067 #elif defined(__BIG_ENDIAN_BITFIELD) 1068 union perf_mem_data_src { 1069 __u64 val; 1070 struct { 1071 __u64 mem_rsvd:24, 1072 mem_snoopx:2, /* snoop mode, ext */ 1073 mem_remote:1, /* remote */ 1074 mem_lvl_num:4, /* memory hierarchy level number */ 1075 mem_dtlb:7, /* tlb access */ 1076 mem_lock:2, /* lock instr */ 1077 mem_snoop:5, /* snoop mode */ 1078 mem_lvl:14, /* memory hierarchy level */ 1079 mem_op:5; /* type of opcode */ 1080 }; 1081 }; 1082 #else 1083 #error "Unknown endianness" 1084 #endif 1085 1086 /* type of opcode (load/store/prefetch,code) */ 1087 #define PERF_MEM_OP_NA 0x01 /* not available */ 1088 #define PERF_MEM_OP_LOAD 0x02 /* load instruction */ 1089 #define PERF_MEM_OP_STORE 0x04 /* store instruction */ 1090 #define PERF_MEM_OP_PFETCH 0x08 /* prefetch */ 1091 #define PERF_MEM_OP_EXEC 0x10 /* code (execution) */ 1092 #define PERF_MEM_OP_SHIFT 0 1093 1094 /* memory hierarchy (memory level, hit or miss) */ 1095 #define PERF_MEM_LVL_NA 0x01 /* not available */ 1096 #define PERF_MEM_LVL_HIT 0x02 /* hit level */ 1097 #define PERF_MEM_LVL_MISS 0x04 /* miss level */ 1098 #define PERF_MEM_LVL_L1 0x08 /* L1 */ 1099 #define PERF_MEM_LVL_LFB 0x10 /* Line Fill Buffer */ 1100 #define PERF_MEM_LVL_L2 0x20 /* L2 */ 1101 #define PERF_MEM_LVL_L3 0x40 /* L3 */ 1102 #define PERF_MEM_LVL_LOC_RAM 0x80 /* Local DRAM */ 1103 #define PERF_MEM_LVL_REM_RAM1 0x100 /* Remote DRAM (1 hop) */ 1104 #define PERF_MEM_LVL_REM_RAM2 0x200 /* Remote DRAM (2 hops) */ 1105 #define PERF_MEM_LVL_REM_CCE1 0x400 /* Remote Cache (1 hop) */ 1106 #define PERF_MEM_LVL_REM_CCE2 0x800 /* Remote Cache (2 hops) */ 1107 #define PERF_MEM_LVL_IO 0x1000 /* I/O memory */ 1108 #define PERF_MEM_LVL_UNC 0x2000 /* Uncached memory */ 1109 #define PERF_MEM_LVL_SHIFT 5 1110 1111 #define PERF_MEM_REMOTE_REMOTE 0x01 /* Remote */ 1112 #define PERF_MEM_REMOTE_SHIFT 37 1113 1114 #define PERF_MEM_LVLNUM_L1 0x01 /* L1 */ 1115 #define PERF_MEM_LVLNUM_L2 0x02 /* L2 */ 1116 #define PERF_MEM_LVLNUM_L3 0x03 /* L3 */ 1117 #define PERF_MEM_LVLNUM_L4 0x04 /* L4 */ 1118 /* 5-0xa available */ 1119 #define PERF_MEM_LVLNUM_ANY_CACHE 0x0b /* Any cache */ 1120 #define PERF_MEM_LVLNUM_LFB 0x0c /* LFB */ 1121 #define PERF_MEM_LVLNUM_RAM 0x0d /* RAM */ 1122 #define PERF_MEM_LVLNUM_PMEM 0x0e /* PMEM */ 1123 #define PERF_MEM_LVLNUM_NA 0x0f /* N/A */ 1124 1125 #define PERF_MEM_LVLNUM_SHIFT 33 1126 1127 /* snoop mode */ 1128 #define PERF_MEM_SNOOP_NA 0x01 /* not available */ 1129 #define PERF_MEM_SNOOP_NONE 0x02 /* no snoop */ 1130 #define PERF_MEM_SNOOP_HIT 0x04 /* snoop hit */ 1131 #define PERF_MEM_SNOOP_MISS 0x08 /* snoop miss */ 1132 #define PERF_MEM_SNOOP_HITM 0x10 /* snoop hit modified */ 1133 #define PERF_MEM_SNOOP_SHIFT 19 1134 1135 #define PERF_MEM_SNOOPX_FWD 0x01 /* forward */ 1136 /* 1 free */ 1137 #define PERF_MEM_SNOOPX_SHIFT 38 1138 1139 /* locked instruction */ 1140 #define PERF_MEM_LOCK_NA 0x01 /* not available */ 1141 #define PERF_MEM_LOCK_LOCKED 0x02 /* locked transaction */ 1142 #define PERF_MEM_LOCK_SHIFT 24 1143 1144 /* TLB access */ 1145 #define PERF_MEM_TLB_NA 0x01 /* not available */ 1146 #define PERF_MEM_TLB_HIT 0x02 /* hit level */ 1147 #define PERF_MEM_TLB_MISS 0x04 /* miss level */ 1148 #define PERF_MEM_TLB_L1 0x08 /* L1 */ 1149 #define PERF_MEM_TLB_L2 0x10 /* L2 */ 1150 #define PERF_MEM_TLB_WK 0x20 /* Hardware Walker*/ 1151 #define PERF_MEM_TLB_OS 0x40 /* OS fault handler */ 1152 #define PERF_MEM_TLB_SHIFT 26 1153 1154 #define PERF_MEM_S(a, s) \ 1155 (((__u64)PERF_MEM_##a##_##s) << PERF_MEM_##a##_SHIFT) 1156 1157 /* 1158 * single taken branch record layout: 1159 * 1160 * from: source instruction (may not always be a branch insn) 1161 * to: branch target 1162 * mispred: branch target was mispredicted 1163 * predicted: branch target was predicted 1164 * 1165 * support for mispred, predicted is optional. In case it 1166 * is not supported mispred = predicted = 0. 1167 * 1168 * in_tx: running in a hardware transaction 1169 * abort: aborting a hardware transaction 1170 * cycles: cycles from last branch (or 0 if not supported) 1171 * type: branch type 1172 */ 1173 struct perf_branch_entry { 1174 __u64 from; 1175 __u64 to; 1176 __u64 mispred:1, /* target mispredicted */ 1177 predicted:1,/* target predicted */ 1178 in_tx:1, /* in transaction */ 1179 abort:1, /* transaction abort */ 1180 cycles:16, /* cycle count to last branch */ 1181 type:4, /* branch type */ 1182 reserved:40; 1183 }; 1184 1185 #endif /* _UAPI_LINUX_PERF_EVENT_H */ 1186