• Home
  • Line#
  • Scopes#
  • Navigate#
  • Raw
  • Download
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #ifndef _ASM_X86_INSN_H
3 #define _ASM_X86_INSN_H
4 /*
5  * x86 instruction analysis
6  *
7  * Copyright (C) IBM Corporation, 2009
8  */
9 
10 /* insn_attr_t is defined in inat.h */
11 #include <asm/inat.h>
12 
13 struct insn_field {
14 	union {
15 		insn_value_t value;
16 		insn_byte_t bytes[4];
17 	};
18 	/* !0 if we've run insn_get_xxx() for this field */
19 	unsigned char got;
20 	unsigned char nbytes;
21 };
22 
23 struct insn {
24 	struct insn_field prefixes;	/*
25 					 * Prefixes
26 					 * prefixes.bytes[3]: last prefix
27 					 */
28 	struct insn_field rex_prefix;	/* REX prefix */
29 	struct insn_field vex_prefix;	/* VEX prefix */
30 	struct insn_field opcode;	/*
31 					 * opcode.bytes[0]: opcode1
32 					 * opcode.bytes[1]: opcode2
33 					 * opcode.bytes[2]: opcode3
34 					 */
35 	struct insn_field modrm;
36 	struct insn_field sib;
37 	struct insn_field displacement;
38 	union {
39 		struct insn_field immediate;
40 		struct insn_field moffset1;	/* for 64bit MOV */
41 		struct insn_field immediate1;	/* for 64bit imm or off16/32 */
42 	};
43 	union {
44 		struct insn_field moffset2;	/* for 64bit MOV */
45 		struct insn_field immediate2;	/* for 64bit imm or seg16 */
46 	};
47 
48 	int	emulate_prefix_size;
49 	insn_attr_t attr;
50 	unsigned char opnd_bytes;
51 	unsigned char addr_bytes;
52 	unsigned char length;
53 	unsigned char x86_64;
54 
55 	const insn_byte_t *kaddr;	/* kernel address of insn to analyze */
56 	const insn_byte_t *end_kaddr;	/* kernel address of last insn in buffer */
57 	const insn_byte_t *next_byte;
58 };
59 
60 #define MAX_INSN_SIZE	15
61 
62 #define X86_MODRM_MOD(modrm) (((modrm) & 0xc0) >> 6)
63 #define X86_MODRM_REG(modrm) (((modrm) & 0x38) >> 3)
64 #define X86_MODRM_RM(modrm) ((modrm) & 0x07)
65 
66 #define X86_SIB_SCALE(sib) (((sib) & 0xc0) >> 6)
67 #define X86_SIB_INDEX(sib) (((sib) & 0x38) >> 3)
68 #define X86_SIB_BASE(sib) ((sib) & 0x07)
69 
70 #define X86_REX_W(rex) ((rex) & 8)
71 #define X86_REX_R(rex) ((rex) & 4)
72 #define X86_REX_X(rex) ((rex) & 2)
73 #define X86_REX_B(rex) ((rex) & 1)
74 
75 /* VEX bit flags  */
76 #define X86_VEX_W(vex)	((vex) & 0x80)	/* VEX3 Byte2 */
77 #define X86_VEX_R(vex)	((vex) & 0x80)	/* VEX2/3 Byte1 */
78 #define X86_VEX_X(vex)	((vex) & 0x40)	/* VEX3 Byte1 */
79 #define X86_VEX_B(vex)	((vex) & 0x20)	/* VEX3 Byte1 */
80 #define X86_VEX_L(vex)	((vex) & 0x04)	/* VEX3 Byte2, VEX2 Byte1 */
81 /* VEX bit fields */
82 #define X86_EVEX_M(vex)	((vex) & 0x03)		/* EVEX Byte1 */
83 #define X86_VEX3_M(vex)	((vex) & 0x1f)		/* VEX3 Byte1 */
84 #define X86_VEX2_M	1			/* VEX2.M always 1 */
85 #define X86_VEX_V(vex)	(((vex) & 0x78) >> 3)	/* VEX3 Byte2, VEX2 Byte1 */
86 #define X86_VEX_P(vex)	((vex) & 0x03)		/* VEX3 Byte2, VEX2 Byte1 */
87 #define X86_VEX_M_MAX	0x1f			/* VEX3.M Maximum value */
88 
89 extern void insn_init(struct insn *insn, const void *kaddr, int buf_len, int x86_64);
90 extern void insn_get_prefixes(struct insn *insn);
91 extern void insn_get_opcode(struct insn *insn);
92 extern void insn_get_modrm(struct insn *insn);
93 extern void insn_get_sib(struct insn *insn);
94 extern void insn_get_displacement(struct insn *insn);
95 extern void insn_get_immediate(struct insn *insn);
96 extern void insn_get_length(struct insn *insn);
97 
98 /* Attribute will be determined after getting ModRM (for opcode groups) */
insn_get_attribute(struct insn * insn)99 static inline void insn_get_attribute(struct insn *insn)
100 {
101 	insn_get_modrm(insn);
102 }
103 
104 /* Instruction uses RIP-relative addressing */
105 extern int insn_rip_relative(struct insn *insn);
106 
107 /* Init insn for kernel text */
kernel_insn_init(struct insn * insn,const void * kaddr,int buf_len)108 static inline void kernel_insn_init(struct insn *insn,
109 				    const void *kaddr, int buf_len)
110 {
111 #ifdef CONFIG_X86_64
112 	insn_init(insn, kaddr, buf_len, 1);
113 #else /* CONFIG_X86_32 */
114 	insn_init(insn, kaddr, buf_len, 0);
115 #endif
116 }
117 
insn_is_avx(struct insn * insn)118 static inline int insn_is_avx(struct insn *insn)
119 {
120 	if (!insn->prefixes.got)
121 		insn_get_prefixes(insn);
122 	return (insn->vex_prefix.value != 0);
123 }
124 
insn_is_evex(struct insn * insn)125 static inline int insn_is_evex(struct insn *insn)
126 {
127 	if (!insn->prefixes.got)
128 		insn_get_prefixes(insn);
129 	return (insn->vex_prefix.nbytes == 4);
130 }
131 
insn_has_emulate_prefix(struct insn * insn)132 static inline int insn_has_emulate_prefix(struct insn *insn)
133 {
134 	return !!insn->emulate_prefix_size;
135 }
136 
137 /* Ensure this instruction is decoded completely */
insn_complete(struct insn * insn)138 static inline int insn_complete(struct insn *insn)
139 {
140 	return insn->opcode.got && insn->modrm.got && insn->sib.got &&
141 		insn->displacement.got && insn->immediate.got;
142 }
143 
insn_vex_m_bits(struct insn * insn)144 static inline insn_byte_t insn_vex_m_bits(struct insn *insn)
145 {
146 	if (insn->vex_prefix.nbytes == 2)	/* 2 bytes VEX */
147 		return X86_VEX2_M;
148 	else if (insn->vex_prefix.nbytes == 3)	/* 3 bytes VEX */
149 		return X86_VEX3_M(insn->vex_prefix.bytes[1]);
150 	else					/* EVEX */
151 		return X86_EVEX_M(insn->vex_prefix.bytes[1]);
152 }
153 
insn_vex_p_bits(struct insn * insn)154 static inline insn_byte_t insn_vex_p_bits(struct insn *insn)
155 {
156 	if (insn->vex_prefix.nbytes == 2)	/* 2 bytes VEX */
157 		return X86_VEX_P(insn->vex_prefix.bytes[1]);
158 	else
159 		return X86_VEX_P(insn->vex_prefix.bytes[2]);
160 }
161 
162 /* Get the last prefix id from last prefix or VEX prefix */
insn_last_prefix_id(struct insn * insn)163 static inline int insn_last_prefix_id(struct insn *insn)
164 {
165 	if (insn_is_avx(insn))
166 		return insn_vex_p_bits(insn);	/* VEX_p is a SIMD prefix id */
167 
168 	if (insn->prefixes.bytes[3])
169 		return inat_get_last_prefix_id(insn->prefixes.bytes[3]);
170 
171 	return 0;
172 }
173 
174 /* Offset of each field from kaddr */
insn_offset_rex_prefix(struct insn * insn)175 static inline int insn_offset_rex_prefix(struct insn *insn)
176 {
177 	return insn->prefixes.nbytes;
178 }
insn_offset_vex_prefix(struct insn * insn)179 static inline int insn_offset_vex_prefix(struct insn *insn)
180 {
181 	return insn_offset_rex_prefix(insn) + insn->rex_prefix.nbytes;
182 }
insn_offset_opcode(struct insn * insn)183 static inline int insn_offset_opcode(struct insn *insn)
184 {
185 	return insn_offset_vex_prefix(insn) + insn->vex_prefix.nbytes;
186 }
insn_offset_modrm(struct insn * insn)187 static inline int insn_offset_modrm(struct insn *insn)
188 {
189 	return insn_offset_opcode(insn) + insn->opcode.nbytes;
190 }
insn_offset_sib(struct insn * insn)191 static inline int insn_offset_sib(struct insn *insn)
192 {
193 	return insn_offset_modrm(insn) + insn->modrm.nbytes;
194 }
insn_offset_displacement(struct insn * insn)195 static inline int insn_offset_displacement(struct insn *insn)
196 {
197 	return insn_offset_sib(insn) + insn->sib.nbytes;
198 }
insn_offset_immediate(struct insn * insn)199 static inline int insn_offset_immediate(struct insn *insn)
200 {
201 	return insn_offset_displacement(insn) + insn->displacement.nbytes;
202 }
203 
204 /**
205  * for_each_insn_prefix() -- Iterate prefixes in the instruction
206  * @insn: Pointer to struct insn.
207  * @idx:  Index storage.
208  * @prefix: Prefix byte.
209  *
210  * Iterate prefix bytes of given @insn. Each prefix byte is stored in @prefix
211  * and the index is stored in @idx (note that this @idx is just for a cursor,
212  * do not change it.)
213  * Since prefixes.nbytes can be bigger than 4 if some prefixes
214  * are repeated, it cannot be used for looping over the prefixes.
215  */
216 #define for_each_insn_prefix(insn, idx, prefix)	\
217 	for (idx = 0; idx < ARRAY_SIZE(insn->prefixes.bytes) && (prefix = insn->prefixes.bytes[idx]) != 0; idx++)
218 
219 #define POP_SS_OPCODE 0x1f
220 #define MOV_SREG_OPCODE 0x8e
221 
222 /*
223  * Intel SDM Vol.3A 6.8.3 states;
224  * "Any single-step trap that would be delivered following the MOV to SS
225  * instruction or POP to SS instruction (because EFLAGS.TF is 1) is
226  * suppressed."
227  * This function returns true if @insn is MOV SS or POP SS. On these
228  * instructions, single stepping is suppressed.
229  */
insn_masking_exception(struct insn * insn)230 static inline int insn_masking_exception(struct insn *insn)
231 {
232 	return insn->opcode.bytes[0] == POP_SS_OPCODE ||
233 		(insn->opcode.bytes[0] == MOV_SREG_OPCODE &&
234 		 X86_MODRM_REG(insn->modrm.bytes[0]) == 2);
235 }
236 
237 #endif /* _ASM_X86_INSN_H */
238