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1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Shared support code for AMD K8 northbridges and derivates.
4  * Copyright 2006 Andi Kleen, SUSE Labs.
5  */
6 
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 
9 #include <linux/types.h>
10 #include <linux/slab.h>
11 #include <linux/init.h>
12 #include <linux/errno.h>
13 #include <linux/export.h>
14 #include <linux/spinlock.h>
15 #include <linux/pci_ids.h>
16 #include <asm/amd_nb.h>
17 
18 #define PCI_DEVICE_ID_AMD_17H_ROOT	0x1450
19 #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT	0x15d0
20 #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT	0x1480
21 #define PCI_DEVICE_ID_AMD_17H_M60H_ROOT	0x1630
22 #define PCI_DEVICE_ID_AMD_17H_DF_F4	0x1464
23 #define PCI_DEVICE_ID_AMD_17H_M10H_DF_F4 0x15ec
24 #define PCI_DEVICE_ID_AMD_17H_M30H_DF_F4 0x1494
25 #define PCI_DEVICE_ID_AMD_17H_M60H_DF_F4 0x144c
26 #define PCI_DEVICE_ID_AMD_17H_M70H_DF_F4 0x1444
27 #define PCI_DEVICE_ID_AMD_19H_DF_F4	0x1654
28 
29 /* Protect the PCI config register pairs used for SMN and DF indirect access. */
30 static DEFINE_MUTEX(smn_mutex);
31 
32 static u32 *flush_words;
33 
34 static const struct pci_device_id amd_root_ids[] = {
35 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_ROOT) },
36 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_ROOT) },
37 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_ROOT) },
38 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_ROOT) },
39 	{}
40 };
41 
42 
43 #define PCI_DEVICE_ID_AMD_CNB17H_F4     0x1704
44 
45 const struct pci_device_id amd_nb_misc_ids[] = {
46 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB_MISC) },
47 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
48 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
49 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },
50 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },
51 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F3) },
52 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },
53 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F3) },
54 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F3) },
55 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F3) },
56 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F3) },
57 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F3) },
58 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
59 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F3) },
60 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F3) },
61 	{}
62 };
63 EXPORT_SYMBOL_GPL(amd_nb_misc_ids);
64 
65 static const struct pci_device_id amd_nb_link_ids[] = {
66 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
67 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
68 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
69 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
70 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
71 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_DF_F4) },
72 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M10H_DF_F4) },
73 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M30H_DF_F4) },
74 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M60H_DF_F4) },
75 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_17H_M70H_DF_F4) },
76 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_19H_DF_F4) },
77 	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CNB17H_F4) },
78 	{}
79 };
80 
81 static const struct pci_device_id hygon_root_ids[] = {
82 	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_ROOT) },
83 	{}
84 };
85 
86 static const struct pci_device_id hygon_nb_misc_ids[] = {
87 	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F3) },
88 	{}
89 };
90 
91 static const struct pci_device_id hygon_nb_link_ids[] = {
92 	{ PCI_DEVICE(PCI_VENDOR_ID_HYGON, PCI_DEVICE_ID_AMD_17H_DF_F4) },
93 	{}
94 };
95 
96 const struct amd_nb_bus_dev_range amd_nb_bus_dev_ranges[] __initconst = {
97 	{ 0x00, 0x18, 0x20 },
98 	{ 0xff, 0x00, 0x20 },
99 	{ 0xfe, 0x00, 0x20 },
100 	{ }
101 };
102 
103 static struct amd_northbridge_info amd_northbridges;
104 
amd_nb_num(void)105 u16 amd_nb_num(void)
106 {
107 	return amd_northbridges.num;
108 }
109 EXPORT_SYMBOL_GPL(amd_nb_num);
110 
amd_nb_has_feature(unsigned int feature)111 bool amd_nb_has_feature(unsigned int feature)
112 {
113 	return ((amd_northbridges.flags & feature) == feature);
114 }
115 EXPORT_SYMBOL_GPL(amd_nb_has_feature);
116 
node_to_amd_nb(int node)117 struct amd_northbridge *node_to_amd_nb(int node)
118 {
119 	return (node < amd_northbridges.num) ? &amd_northbridges.nb[node] : NULL;
120 }
121 EXPORT_SYMBOL_GPL(node_to_amd_nb);
122 
next_northbridge(struct pci_dev * dev,const struct pci_device_id * ids)123 static struct pci_dev *next_northbridge(struct pci_dev *dev,
124 					const struct pci_device_id *ids)
125 {
126 	do {
127 		dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, dev);
128 		if (!dev)
129 			break;
130 	} while (!pci_match_id(ids, dev));
131 	return dev;
132 }
133 
__amd_smn_rw(u16 node,u32 address,u32 * value,bool write)134 static int __amd_smn_rw(u16 node, u32 address, u32 *value, bool write)
135 {
136 	struct pci_dev *root;
137 	int err = -ENODEV;
138 
139 	if (node >= amd_northbridges.num)
140 		goto out;
141 
142 	root = node_to_amd_nb(node)->root;
143 	if (!root)
144 		goto out;
145 
146 	mutex_lock(&smn_mutex);
147 
148 	err = pci_write_config_dword(root, 0x60, address);
149 	if (err) {
150 		pr_warn("Error programming SMN address 0x%x.\n", address);
151 		goto out_unlock;
152 	}
153 
154 	err = (write ? pci_write_config_dword(root, 0x64, *value)
155 		     : pci_read_config_dword(root, 0x64, value));
156 	if (err)
157 		pr_warn("Error %s SMN address 0x%x.\n",
158 			(write ? "writing to" : "reading from"), address);
159 
160 out_unlock:
161 	mutex_unlock(&smn_mutex);
162 
163 out:
164 	return err;
165 }
166 
amd_smn_read(u16 node,u32 address,u32 * value)167 int amd_smn_read(u16 node, u32 address, u32 *value)
168 {
169 	return __amd_smn_rw(node, address, value, false);
170 }
171 EXPORT_SYMBOL_GPL(amd_smn_read);
172 
amd_smn_write(u16 node,u32 address,u32 value)173 int amd_smn_write(u16 node, u32 address, u32 value)
174 {
175 	return __amd_smn_rw(node, address, &value, true);
176 }
177 EXPORT_SYMBOL_GPL(amd_smn_write);
178 
179 /*
180  * Data Fabric Indirect Access uses FICAA/FICAD.
181  *
182  * Fabric Indirect Configuration Access Address (FICAA): Constructed based
183  * on the device's Instance Id and the PCI function and register offset of
184  * the desired register.
185  *
186  * Fabric Indirect Configuration Access Data (FICAD): There are FICAD LO
187  * and FICAD HI registers but so far we only need the LO register.
188  */
amd_df_indirect_read(u16 node,u8 func,u16 reg,u8 instance_id,u32 * lo)189 int amd_df_indirect_read(u16 node, u8 func, u16 reg, u8 instance_id, u32 *lo)
190 {
191 	struct pci_dev *F4;
192 	u32 ficaa;
193 	int err = -ENODEV;
194 
195 	if (node >= amd_northbridges.num)
196 		goto out;
197 
198 	F4 = node_to_amd_nb(node)->link;
199 	if (!F4)
200 		goto out;
201 
202 	ficaa  = 1;
203 	ficaa |= reg & 0x3FC;
204 	ficaa |= (func & 0x7) << 11;
205 	ficaa |= instance_id << 16;
206 
207 	mutex_lock(&smn_mutex);
208 
209 	err = pci_write_config_dword(F4, 0x5C, ficaa);
210 	if (err) {
211 		pr_warn("Error writing DF Indirect FICAA, FICAA=0x%x\n", ficaa);
212 		goto out_unlock;
213 	}
214 
215 	err = pci_read_config_dword(F4, 0x98, lo);
216 	if (err)
217 		pr_warn("Error reading DF Indirect FICAD LO, FICAA=0x%x.\n", ficaa);
218 
219 out_unlock:
220 	mutex_unlock(&smn_mutex);
221 
222 out:
223 	return err;
224 }
225 EXPORT_SYMBOL_GPL(amd_df_indirect_read);
226 
amd_cache_northbridges(void)227 int amd_cache_northbridges(void)
228 {
229 	const struct pci_device_id *misc_ids = amd_nb_misc_ids;
230 	const struct pci_device_id *link_ids = amd_nb_link_ids;
231 	const struct pci_device_id *root_ids = amd_root_ids;
232 	struct pci_dev *root, *misc, *link;
233 	struct amd_northbridge *nb;
234 	u16 roots_per_misc = 0;
235 	u16 misc_count = 0;
236 	u16 root_count = 0;
237 	u16 i, j;
238 
239 	if (amd_northbridges.num)
240 		return 0;
241 
242 	if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) {
243 		root_ids = hygon_root_ids;
244 		misc_ids = hygon_nb_misc_ids;
245 		link_ids = hygon_nb_link_ids;
246 	}
247 
248 	misc = NULL;
249 	while ((misc = next_northbridge(misc, misc_ids)) != NULL)
250 		misc_count++;
251 
252 	if (!misc_count)
253 		return -ENODEV;
254 
255 	root = NULL;
256 	while ((root = next_northbridge(root, root_ids)) != NULL)
257 		root_count++;
258 
259 	if (root_count) {
260 		roots_per_misc = root_count / misc_count;
261 
262 		/*
263 		 * There should be _exactly_ N roots for each DF/SMN
264 		 * interface.
265 		 */
266 		if (!roots_per_misc || (root_count % roots_per_misc)) {
267 			pr_info("Unsupported AMD DF/PCI configuration found\n");
268 			return -ENODEV;
269 		}
270 	}
271 
272 	nb = kcalloc(misc_count, sizeof(struct amd_northbridge), GFP_KERNEL);
273 	if (!nb)
274 		return -ENOMEM;
275 
276 	amd_northbridges.nb = nb;
277 	amd_northbridges.num = misc_count;
278 
279 	link = misc = root = NULL;
280 	for (i = 0; i < amd_northbridges.num; i++) {
281 		node_to_amd_nb(i)->root = root =
282 			next_northbridge(root, root_ids);
283 		node_to_amd_nb(i)->misc = misc =
284 			next_northbridge(misc, misc_ids);
285 		node_to_amd_nb(i)->link = link =
286 			next_northbridge(link, link_ids);
287 
288 		/*
289 		 * If there are more PCI root devices than data fabric/
290 		 * system management network interfaces, then the (N)
291 		 * PCI roots per DF/SMN interface are functionally the
292 		 * same (for DF/SMN access) and N-1 are redundant.  N-1
293 		 * PCI roots should be skipped per DF/SMN interface so
294 		 * the following DF/SMN interfaces get mapped to
295 		 * correct PCI roots.
296 		 */
297 		for (j = 1; j < roots_per_misc; j++)
298 			root = next_northbridge(root, root_ids);
299 	}
300 
301 	if (amd_gart_present())
302 		amd_northbridges.flags |= AMD_NB_GART;
303 
304 	/*
305 	 * Check for L3 cache presence.
306 	 */
307 	if (!cpuid_edx(0x80000006))
308 		return 0;
309 
310 	/*
311 	 * Some CPU families support L3 Cache Index Disable. There are some
312 	 * limitations because of E382 and E388 on family 0x10.
313 	 */
314 	if (boot_cpu_data.x86 == 0x10 &&
315 	    boot_cpu_data.x86_model >= 0x8 &&
316 	    (boot_cpu_data.x86_model > 0x9 ||
317 	     boot_cpu_data.x86_stepping >= 0x1))
318 		amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
319 
320 	if (boot_cpu_data.x86 == 0x15)
321 		amd_northbridges.flags |= AMD_NB_L3_INDEX_DISABLE;
322 
323 	/* L3 cache partitioning is supported on family 0x15 */
324 	if (boot_cpu_data.x86 == 0x15)
325 		amd_northbridges.flags |= AMD_NB_L3_PARTITIONING;
326 
327 	return 0;
328 }
329 EXPORT_SYMBOL_GPL(amd_cache_northbridges);
330 
331 /*
332  * Ignores subdevice/subvendor but as far as I can figure out
333  * they're useless anyways
334  */
early_is_amd_nb(u32 device)335 bool __init early_is_amd_nb(u32 device)
336 {
337 	const struct pci_device_id *misc_ids = amd_nb_misc_ids;
338 	const struct pci_device_id *id;
339 	u32 vendor = device & 0xffff;
340 
341 	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
342 	    boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
343 		return false;
344 
345 	if (boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
346 		misc_ids = hygon_nb_misc_ids;
347 
348 	device >>= 16;
349 	for (id = misc_ids; id->vendor; id++)
350 		if (vendor == id->vendor && device == id->device)
351 			return true;
352 	return false;
353 }
354 
amd_get_mmconfig_range(struct resource * res)355 struct resource *amd_get_mmconfig_range(struct resource *res)
356 {
357 	u32 address;
358 	u64 base, msr;
359 	unsigned int segn_busn_bits;
360 
361 	if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD &&
362 	    boot_cpu_data.x86_vendor != X86_VENDOR_HYGON)
363 		return NULL;
364 
365 	/* assume all cpus from fam10h have mmconfig */
366 	if (boot_cpu_data.x86 < 0x10)
367 		return NULL;
368 
369 	address = MSR_FAM10H_MMIO_CONF_BASE;
370 	rdmsrl(address, msr);
371 
372 	/* mmconfig is not enabled */
373 	if (!(msr & FAM10H_MMIO_CONF_ENABLE))
374 		return NULL;
375 
376 	base = msr & (FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT);
377 
378 	segn_busn_bits = (msr >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
379 			 FAM10H_MMIO_CONF_BUSRANGE_MASK;
380 
381 	res->flags = IORESOURCE_MEM;
382 	res->start = base;
383 	res->end = base + (1ULL<<(segn_busn_bits + 20)) - 1;
384 	return res;
385 }
386 
amd_get_subcaches(int cpu)387 int amd_get_subcaches(int cpu)
388 {
389 	struct pci_dev *link = node_to_amd_nb(amd_get_nb_id(cpu))->link;
390 	unsigned int mask;
391 
392 	if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING))
393 		return 0;
394 
395 	pci_read_config_dword(link, 0x1d4, &mask);
396 
397 	return (mask >> (4 * cpu_data(cpu).cpu_core_id)) & 0xf;
398 }
399 
amd_set_subcaches(int cpu,unsigned long mask)400 int amd_set_subcaches(int cpu, unsigned long mask)
401 {
402 	static unsigned int reset, ban;
403 	struct amd_northbridge *nb = node_to_amd_nb(amd_get_nb_id(cpu));
404 	unsigned int reg;
405 	int cuid;
406 
407 	if (!amd_nb_has_feature(AMD_NB_L3_PARTITIONING) || mask > 0xf)
408 		return -EINVAL;
409 
410 	/* if necessary, collect reset state of L3 partitioning and BAN mode */
411 	if (reset == 0) {
412 		pci_read_config_dword(nb->link, 0x1d4, &reset);
413 		pci_read_config_dword(nb->misc, 0x1b8, &ban);
414 		ban &= 0x180000;
415 	}
416 
417 	/* deactivate BAN mode if any subcaches are to be disabled */
418 	if (mask != 0xf) {
419 		pci_read_config_dword(nb->misc, 0x1b8, &reg);
420 		pci_write_config_dword(nb->misc, 0x1b8, reg & ~0x180000);
421 	}
422 
423 	cuid = cpu_data(cpu).cpu_core_id;
424 	mask <<= 4 * cuid;
425 	mask |= (0xf ^ (1 << cuid)) << 26;
426 
427 	pci_write_config_dword(nb->link, 0x1d4, mask);
428 
429 	/* reset BAN mode if L3 partitioning returned to reset state */
430 	pci_read_config_dword(nb->link, 0x1d4, &reg);
431 	if (reg == reset) {
432 		pci_read_config_dword(nb->misc, 0x1b8, &reg);
433 		reg &= ~0x180000;
434 		pci_write_config_dword(nb->misc, 0x1b8, reg | ban);
435 	}
436 
437 	return 0;
438 }
439 
amd_cache_gart(void)440 static void amd_cache_gart(void)
441 {
442 	u16 i;
443 
444 	if (!amd_nb_has_feature(AMD_NB_GART))
445 		return;
446 
447 	flush_words = kmalloc_array(amd_northbridges.num, sizeof(u32), GFP_KERNEL);
448 	if (!flush_words) {
449 		amd_northbridges.flags &= ~AMD_NB_GART;
450 		pr_notice("Cannot initialize GART flush words, GART support disabled\n");
451 		return;
452 	}
453 
454 	for (i = 0; i != amd_northbridges.num; i++)
455 		pci_read_config_dword(node_to_amd_nb(i)->misc, 0x9c, &flush_words[i]);
456 }
457 
amd_flush_garts(void)458 void amd_flush_garts(void)
459 {
460 	int flushed, i;
461 	unsigned long flags;
462 	static DEFINE_SPINLOCK(gart_lock);
463 
464 	if (!amd_nb_has_feature(AMD_NB_GART))
465 		return;
466 
467 	/*
468 	 * Avoid races between AGP and IOMMU. In theory it's not needed
469 	 * but I'm not sure if the hardware won't lose flush requests
470 	 * when another is pending. This whole thing is so expensive anyways
471 	 * that it doesn't matter to serialize more. -AK
472 	 */
473 	spin_lock_irqsave(&gart_lock, flags);
474 	flushed = 0;
475 	for (i = 0; i < amd_northbridges.num; i++) {
476 		pci_write_config_dword(node_to_amd_nb(i)->misc, 0x9c,
477 				       flush_words[i] | 1);
478 		flushed++;
479 	}
480 	for (i = 0; i < amd_northbridges.num; i++) {
481 		u32 w;
482 		/* Make sure the hardware actually executed the flush*/
483 		for (;;) {
484 			pci_read_config_dword(node_to_amd_nb(i)->misc,
485 					      0x9c, &w);
486 			if (!(w & 1))
487 				break;
488 			cpu_relax();
489 		}
490 	}
491 	spin_unlock_irqrestore(&gart_lock, flags);
492 	if (!flushed)
493 		pr_notice("nothing to flush?\n");
494 }
495 EXPORT_SYMBOL_GPL(amd_flush_garts);
496 
__fix_erratum_688(void * info)497 static void __fix_erratum_688(void *info)
498 {
499 #define MSR_AMD64_IC_CFG 0xC0011021
500 
501 	msr_set_bit(MSR_AMD64_IC_CFG, 3);
502 	msr_set_bit(MSR_AMD64_IC_CFG, 14);
503 }
504 
505 /* Apply erratum 688 fix so machines without a BIOS fix work. */
fix_erratum_688(void)506 static __init void fix_erratum_688(void)
507 {
508 	struct pci_dev *F4;
509 	u32 val;
510 
511 	if (boot_cpu_data.x86 != 0x14)
512 		return;
513 
514 	if (!amd_northbridges.num)
515 		return;
516 
517 	F4 = node_to_amd_nb(0)->link;
518 	if (!F4)
519 		return;
520 
521 	if (pci_read_config_dword(F4, 0x164, &val))
522 		return;
523 
524 	if (val & BIT(2))
525 		return;
526 
527 	on_each_cpu(__fix_erratum_688, NULL, 0);
528 
529 	pr_info("x86/cpu/AMD: CPU erratum 688 worked around\n");
530 }
531 
init_amd_nbs(void)532 static __init int init_amd_nbs(void)
533 {
534 	amd_cache_northbridges();
535 	amd_cache_gart();
536 
537 	fix_erratum_688();
538 
539 	return 0;
540 }
541 
542 /* This has to go after the PCI subsystem */
543 fs_initcall(init_amd_nbs);
544