1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Local APIC related interfaces to support IOAPIC, MSI, etc.
4 *
5 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Moved from arch/x86/kernel/apic/io_apic.c.
7 * Jiang Liu <jiang.liu@linux.intel.com>
8 * Enable support of hierarchical irqdomains
9 */
10 #include <linux/interrupt.h>
11 #include <linux/irq.h>
12 #include <linux/seq_file.h>
13 #include <linux/init.h>
14 #include <linux/compiler.h>
15 #include <linux/slab.h>
16 #include <asm/irqdomain.h>
17 #include <asm/hw_irq.h>
18 #include <asm/traps.h>
19 #include <asm/apic.h>
20 #include <asm/i8259.h>
21 #include <asm/desc.h>
22 #include <asm/irq_remapping.h>
23
24 #include <asm/trace/irq_vectors.h>
25
26 struct apic_chip_data {
27 struct irq_cfg hw_irq_cfg;
28 unsigned int vector;
29 unsigned int prev_vector;
30 unsigned int cpu;
31 unsigned int prev_cpu;
32 unsigned int irq;
33 struct hlist_node clist;
34 unsigned int move_in_progress : 1,
35 is_managed : 1,
36 can_reserve : 1,
37 has_reserved : 1;
38 };
39
40 struct irq_domain *x86_vector_domain;
41 EXPORT_SYMBOL_GPL(x86_vector_domain);
42 static DEFINE_RAW_SPINLOCK(vector_lock);
43 static cpumask_var_t vector_searchmask;
44 static struct irq_chip lapic_controller;
45 static struct irq_matrix *vector_matrix;
46 #ifdef CONFIG_SMP
47 static DEFINE_PER_CPU(struct hlist_head, cleanup_list);
48 #endif
49
lock_vector_lock(void)50 void lock_vector_lock(void)
51 {
52 /* Used to the online set of cpus does not change
53 * during assign_irq_vector.
54 */
55 raw_spin_lock(&vector_lock);
56 }
57
unlock_vector_lock(void)58 void unlock_vector_lock(void)
59 {
60 raw_spin_unlock(&vector_lock);
61 }
62
init_irq_alloc_info(struct irq_alloc_info * info,const struct cpumask * mask)63 void init_irq_alloc_info(struct irq_alloc_info *info,
64 const struct cpumask *mask)
65 {
66 memset(info, 0, sizeof(*info));
67 info->mask = mask;
68 }
69
copy_irq_alloc_info(struct irq_alloc_info * dst,struct irq_alloc_info * src)70 void copy_irq_alloc_info(struct irq_alloc_info *dst, struct irq_alloc_info *src)
71 {
72 if (src)
73 *dst = *src;
74 else
75 memset(dst, 0, sizeof(*dst));
76 }
77
apic_chip_data(struct irq_data * irqd)78 static struct apic_chip_data *apic_chip_data(struct irq_data *irqd)
79 {
80 if (!irqd)
81 return NULL;
82
83 while (irqd->parent_data)
84 irqd = irqd->parent_data;
85
86 return irqd->chip_data;
87 }
88
irqd_cfg(struct irq_data * irqd)89 struct irq_cfg *irqd_cfg(struct irq_data *irqd)
90 {
91 struct apic_chip_data *apicd = apic_chip_data(irqd);
92
93 return apicd ? &apicd->hw_irq_cfg : NULL;
94 }
95 EXPORT_SYMBOL_GPL(irqd_cfg);
96
irq_cfg(unsigned int irq)97 struct irq_cfg *irq_cfg(unsigned int irq)
98 {
99 return irqd_cfg(irq_get_irq_data(irq));
100 }
101
alloc_apic_chip_data(int node)102 static struct apic_chip_data *alloc_apic_chip_data(int node)
103 {
104 struct apic_chip_data *apicd;
105
106 apicd = kzalloc_node(sizeof(*apicd), GFP_KERNEL, node);
107 if (apicd)
108 INIT_HLIST_NODE(&apicd->clist);
109 return apicd;
110 }
111
free_apic_chip_data(struct apic_chip_data * apicd)112 static void free_apic_chip_data(struct apic_chip_data *apicd)
113 {
114 kfree(apicd);
115 }
116
apic_update_irq_cfg(struct irq_data * irqd,unsigned int vector,unsigned int cpu)117 static void apic_update_irq_cfg(struct irq_data *irqd, unsigned int vector,
118 unsigned int cpu)
119 {
120 struct apic_chip_data *apicd = apic_chip_data(irqd);
121
122 lockdep_assert_held(&vector_lock);
123
124 apicd->hw_irq_cfg.vector = vector;
125 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu);
126 irq_data_update_effective_affinity(irqd, cpumask_of(cpu));
127 trace_vector_config(irqd->irq, vector, cpu,
128 apicd->hw_irq_cfg.dest_apicid);
129 }
130
apic_update_vector(struct irq_data * irqd,unsigned int newvec,unsigned int newcpu)131 static void apic_update_vector(struct irq_data *irqd, unsigned int newvec,
132 unsigned int newcpu)
133 {
134 struct apic_chip_data *apicd = apic_chip_data(irqd);
135 struct irq_desc *desc = irq_data_to_desc(irqd);
136 bool managed = irqd_affinity_is_managed(irqd);
137
138 lockdep_assert_held(&vector_lock);
139
140 trace_vector_update(irqd->irq, newvec, newcpu, apicd->vector,
141 apicd->cpu);
142
143 /*
144 * If there is no vector associated or if the associated vector is
145 * the shutdown vector, which is associated to make PCI/MSI
146 * shutdown mode work, then there is nothing to release. Clear out
147 * prev_vector for this and the offlined target case.
148 */
149 apicd->prev_vector = 0;
150 if (!apicd->vector || apicd->vector == MANAGED_IRQ_SHUTDOWN_VECTOR)
151 goto setnew;
152 /*
153 * If the target CPU of the previous vector is online, then mark
154 * the vector as move in progress and store it for cleanup when the
155 * first interrupt on the new vector arrives. If the target CPU is
156 * offline then the regular release mechanism via the cleanup
157 * vector is not possible and the vector can be immediately freed
158 * in the underlying matrix allocator.
159 */
160 if (cpu_online(apicd->cpu)) {
161 apicd->move_in_progress = true;
162 apicd->prev_vector = apicd->vector;
163 apicd->prev_cpu = apicd->cpu;
164 } else {
165 irq_matrix_free(vector_matrix, apicd->cpu, apicd->vector,
166 managed);
167 }
168
169 setnew:
170 apicd->vector = newvec;
171 apicd->cpu = newcpu;
172 BUG_ON(!IS_ERR_OR_NULL(per_cpu(vector_irq, newcpu)[newvec]));
173 per_cpu(vector_irq, newcpu)[newvec] = desc;
174 }
175
vector_assign_managed_shutdown(struct irq_data * irqd)176 static void vector_assign_managed_shutdown(struct irq_data *irqd)
177 {
178 unsigned int cpu = cpumask_first(cpu_online_mask);
179
180 apic_update_irq_cfg(irqd, MANAGED_IRQ_SHUTDOWN_VECTOR, cpu);
181 }
182
reserve_managed_vector(struct irq_data * irqd)183 static int reserve_managed_vector(struct irq_data *irqd)
184 {
185 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
186 struct apic_chip_data *apicd = apic_chip_data(irqd);
187 unsigned long flags;
188 int ret;
189
190 raw_spin_lock_irqsave(&vector_lock, flags);
191 apicd->is_managed = true;
192 ret = irq_matrix_reserve_managed(vector_matrix, affmsk);
193 raw_spin_unlock_irqrestore(&vector_lock, flags);
194 trace_vector_reserve_managed(irqd->irq, ret);
195 return ret;
196 }
197
reserve_irq_vector_locked(struct irq_data * irqd)198 static void reserve_irq_vector_locked(struct irq_data *irqd)
199 {
200 struct apic_chip_data *apicd = apic_chip_data(irqd);
201
202 irq_matrix_reserve(vector_matrix);
203 apicd->can_reserve = true;
204 apicd->has_reserved = true;
205 irqd_set_can_reserve(irqd);
206 trace_vector_reserve(irqd->irq, 0);
207 vector_assign_managed_shutdown(irqd);
208 }
209
reserve_irq_vector(struct irq_data * irqd)210 static int reserve_irq_vector(struct irq_data *irqd)
211 {
212 unsigned long flags;
213
214 raw_spin_lock_irqsave(&vector_lock, flags);
215 reserve_irq_vector_locked(irqd);
216 raw_spin_unlock_irqrestore(&vector_lock, flags);
217 return 0;
218 }
219
220 static int
assign_vector_locked(struct irq_data * irqd,const struct cpumask * dest)221 assign_vector_locked(struct irq_data *irqd, const struct cpumask *dest)
222 {
223 struct apic_chip_data *apicd = apic_chip_data(irqd);
224 bool resvd = apicd->has_reserved;
225 unsigned int cpu = apicd->cpu;
226 int vector = apicd->vector;
227
228 lockdep_assert_held(&vector_lock);
229
230 /*
231 * If the current target CPU is online and in the new requested
232 * affinity mask, there is no point in moving the interrupt from
233 * one CPU to another.
234 */
235 if (vector && cpu_online(cpu) && cpumask_test_cpu(cpu, dest))
236 return 0;
237
238 /*
239 * Careful here. @apicd might either have move_in_progress set or
240 * be enqueued for cleanup. Assigning a new vector would either
241 * leave a stale vector on some CPU around or in case of a pending
242 * cleanup corrupt the hlist.
243 */
244 if (apicd->move_in_progress || !hlist_unhashed(&apicd->clist))
245 return -EBUSY;
246
247 vector = irq_matrix_alloc(vector_matrix, dest, resvd, &cpu);
248 trace_vector_alloc(irqd->irq, vector, resvd, vector);
249 if (vector < 0)
250 return vector;
251 apic_update_vector(irqd, vector, cpu);
252 apic_update_irq_cfg(irqd, vector, cpu);
253
254 return 0;
255 }
256
assign_irq_vector(struct irq_data * irqd,const struct cpumask * dest)257 static int assign_irq_vector(struct irq_data *irqd, const struct cpumask *dest)
258 {
259 unsigned long flags;
260 int ret;
261
262 raw_spin_lock_irqsave(&vector_lock, flags);
263 cpumask_and(vector_searchmask, dest, cpu_online_mask);
264 ret = assign_vector_locked(irqd, vector_searchmask);
265 raw_spin_unlock_irqrestore(&vector_lock, flags);
266 return ret;
267 }
268
assign_irq_vector_any_locked(struct irq_data * irqd)269 static int assign_irq_vector_any_locked(struct irq_data *irqd)
270 {
271 /* Get the affinity mask - either irq_default_affinity or (user) set */
272 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
273 int node = irq_data_get_node(irqd);
274
275 if (node != NUMA_NO_NODE) {
276 /* Try the intersection of @affmsk and node mask */
277 cpumask_and(vector_searchmask, cpumask_of_node(node), affmsk);
278 if (!assign_vector_locked(irqd, vector_searchmask))
279 return 0;
280 }
281
282 /* Try the full affinity mask */
283 cpumask_and(vector_searchmask, affmsk, cpu_online_mask);
284 if (!assign_vector_locked(irqd, vector_searchmask))
285 return 0;
286
287 if (node != NUMA_NO_NODE) {
288 /* Try the node mask */
289 if (!assign_vector_locked(irqd, cpumask_of_node(node)))
290 return 0;
291 }
292
293 /* Try the full online mask */
294 return assign_vector_locked(irqd, cpu_online_mask);
295 }
296
297 static int
assign_irq_vector_policy(struct irq_data * irqd,struct irq_alloc_info * info)298 assign_irq_vector_policy(struct irq_data *irqd, struct irq_alloc_info *info)
299 {
300 if (irqd_affinity_is_managed(irqd))
301 return reserve_managed_vector(irqd);
302 if (info->mask)
303 return assign_irq_vector(irqd, info->mask);
304 /*
305 * Make only a global reservation with no guarantee. A real vector
306 * is associated at activation time.
307 */
308 return reserve_irq_vector(irqd);
309 }
310
311 static int
assign_managed_vector(struct irq_data * irqd,const struct cpumask * dest)312 assign_managed_vector(struct irq_data *irqd, const struct cpumask *dest)
313 {
314 const struct cpumask *affmsk = irq_data_get_affinity_mask(irqd);
315 struct apic_chip_data *apicd = apic_chip_data(irqd);
316 int vector, cpu;
317
318 cpumask_and(vector_searchmask, dest, affmsk);
319
320 /* set_affinity might call here for nothing */
321 if (apicd->vector && cpumask_test_cpu(apicd->cpu, vector_searchmask))
322 return 0;
323 vector = irq_matrix_alloc_managed(vector_matrix, vector_searchmask,
324 &cpu);
325 trace_vector_alloc_managed(irqd->irq, vector, vector);
326 if (vector < 0)
327 return vector;
328 apic_update_vector(irqd, vector, cpu);
329 apic_update_irq_cfg(irqd, vector, cpu);
330 return 0;
331 }
332
clear_irq_vector(struct irq_data * irqd)333 static void clear_irq_vector(struct irq_data *irqd)
334 {
335 struct apic_chip_data *apicd = apic_chip_data(irqd);
336 bool managed = irqd_affinity_is_managed(irqd);
337 unsigned int vector = apicd->vector;
338
339 lockdep_assert_held(&vector_lock);
340
341 if (!vector)
342 return;
343
344 trace_vector_clear(irqd->irq, vector, apicd->cpu, apicd->prev_vector,
345 apicd->prev_cpu);
346
347 per_cpu(vector_irq, apicd->cpu)[vector] = VECTOR_SHUTDOWN;
348 irq_matrix_free(vector_matrix, apicd->cpu, vector, managed);
349 apicd->vector = 0;
350
351 /* Clean up move in progress */
352 vector = apicd->prev_vector;
353 if (!vector)
354 return;
355
356 per_cpu(vector_irq, apicd->prev_cpu)[vector] = VECTOR_SHUTDOWN;
357 irq_matrix_free(vector_matrix, apicd->prev_cpu, vector, managed);
358 apicd->prev_vector = 0;
359 apicd->move_in_progress = 0;
360 hlist_del_init(&apicd->clist);
361 }
362
x86_vector_deactivate(struct irq_domain * dom,struct irq_data * irqd)363 static void x86_vector_deactivate(struct irq_domain *dom, struct irq_data *irqd)
364 {
365 struct apic_chip_data *apicd = apic_chip_data(irqd);
366 unsigned long flags;
367
368 trace_vector_deactivate(irqd->irq, apicd->is_managed,
369 apicd->can_reserve, false);
370
371 /* Regular fixed assigned interrupt */
372 if (!apicd->is_managed && !apicd->can_reserve)
373 return;
374 /* If the interrupt has a global reservation, nothing to do */
375 if (apicd->has_reserved)
376 return;
377
378 raw_spin_lock_irqsave(&vector_lock, flags);
379 clear_irq_vector(irqd);
380 if (apicd->can_reserve)
381 reserve_irq_vector_locked(irqd);
382 else
383 vector_assign_managed_shutdown(irqd);
384 raw_spin_unlock_irqrestore(&vector_lock, flags);
385 }
386
activate_reserved(struct irq_data * irqd)387 static int activate_reserved(struct irq_data *irqd)
388 {
389 struct apic_chip_data *apicd = apic_chip_data(irqd);
390 int ret;
391
392 ret = assign_irq_vector_any_locked(irqd);
393 if (!ret) {
394 apicd->has_reserved = false;
395 /*
396 * Core might have disabled reservation mode after
397 * allocating the irq descriptor. Ideally this should
398 * happen before allocation time, but that would require
399 * completely convoluted ways of transporting that
400 * information.
401 */
402 if (!irqd_can_reserve(irqd))
403 apicd->can_reserve = false;
404 }
405
406 /*
407 * Check to ensure that the effective affinity mask is a subset
408 * the user supplied affinity mask, and warn the user if it is not
409 */
410 if (!cpumask_subset(irq_data_get_effective_affinity_mask(irqd),
411 irq_data_get_affinity_mask(irqd))) {
412 pr_warn("irq %u: Affinity broken due to vector space exhaustion.\n",
413 irqd->irq);
414 }
415
416 return ret;
417 }
418
activate_managed(struct irq_data * irqd)419 static int activate_managed(struct irq_data *irqd)
420 {
421 const struct cpumask *dest = irq_data_get_affinity_mask(irqd);
422 int ret;
423
424 cpumask_and(vector_searchmask, dest, cpu_online_mask);
425 if (WARN_ON_ONCE(cpumask_empty(vector_searchmask))) {
426 /* Something in the core code broke! Survive gracefully */
427 pr_err("Managed startup for irq %u, but no CPU\n", irqd->irq);
428 return -EINVAL;
429 }
430
431 ret = assign_managed_vector(irqd, vector_searchmask);
432 /*
433 * This should not happen. The vector reservation got buggered. Handle
434 * it gracefully.
435 */
436 if (WARN_ON_ONCE(ret < 0)) {
437 pr_err("Managed startup irq %u, no vector available\n",
438 irqd->irq);
439 }
440 return ret;
441 }
442
x86_vector_activate(struct irq_domain * dom,struct irq_data * irqd,bool reserve)443 static int x86_vector_activate(struct irq_domain *dom, struct irq_data *irqd,
444 bool reserve)
445 {
446 struct apic_chip_data *apicd = apic_chip_data(irqd);
447 unsigned long flags;
448 int ret = 0;
449
450 trace_vector_activate(irqd->irq, apicd->is_managed,
451 apicd->can_reserve, reserve);
452
453 raw_spin_lock_irqsave(&vector_lock, flags);
454 if (!apicd->can_reserve && !apicd->is_managed)
455 assign_irq_vector_any_locked(irqd);
456 else if (reserve || irqd_is_managed_and_shutdown(irqd))
457 vector_assign_managed_shutdown(irqd);
458 else if (apicd->is_managed)
459 ret = activate_managed(irqd);
460 else if (apicd->has_reserved)
461 ret = activate_reserved(irqd);
462 raw_spin_unlock_irqrestore(&vector_lock, flags);
463 return ret;
464 }
465
vector_free_reserved_and_managed(struct irq_data * irqd)466 static void vector_free_reserved_and_managed(struct irq_data *irqd)
467 {
468 const struct cpumask *dest = irq_data_get_affinity_mask(irqd);
469 struct apic_chip_data *apicd = apic_chip_data(irqd);
470
471 trace_vector_teardown(irqd->irq, apicd->is_managed,
472 apicd->has_reserved);
473
474 if (apicd->has_reserved)
475 irq_matrix_remove_reserved(vector_matrix);
476 if (apicd->is_managed)
477 irq_matrix_remove_managed(vector_matrix, dest);
478 }
479
x86_vector_free_irqs(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)480 static void x86_vector_free_irqs(struct irq_domain *domain,
481 unsigned int virq, unsigned int nr_irqs)
482 {
483 struct apic_chip_data *apicd;
484 struct irq_data *irqd;
485 unsigned long flags;
486 int i;
487
488 for (i = 0; i < nr_irqs; i++) {
489 irqd = irq_domain_get_irq_data(x86_vector_domain, virq + i);
490 if (irqd && irqd->chip_data) {
491 raw_spin_lock_irqsave(&vector_lock, flags);
492 clear_irq_vector(irqd);
493 vector_free_reserved_and_managed(irqd);
494 apicd = irqd->chip_data;
495 irq_domain_reset_irq_data(irqd);
496 raw_spin_unlock_irqrestore(&vector_lock, flags);
497 free_apic_chip_data(apicd);
498 }
499 }
500 }
501
vector_configure_legacy(unsigned int virq,struct irq_data * irqd,struct apic_chip_data * apicd)502 static bool vector_configure_legacy(unsigned int virq, struct irq_data *irqd,
503 struct apic_chip_data *apicd)
504 {
505 unsigned long flags;
506 bool realloc = false;
507
508 apicd->vector = ISA_IRQ_VECTOR(virq);
509 apicd->cpu = 0;
510
511 raw_spin_lock_irqsave(&vector_lock, flags);
512 /*
513 * If the interrupt is activated, then it must stay at this vector
514 * position. That's usually the timer interrupt (0).
515 */
516 if (irqd_is_activated(irqd)) {
517 trace_vector_setup(virq, true, 0);
518 apic_update_irq_cfg(irqd, apicd->vector, apicd->cpu);
519 } else {
520 /* Release the vector */
521 apicd->can_reserve = true;
522 irqd_set_can_reserve(irqd);
523 clear_irq_vector(irqd);
524 realloc = true;
525 }
526 raw_spin_unlock_irqrestore(&vector_lock, flags);
527 return realloc;
528 }
529
x86_vector_alloc_irqs(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)530 static int x86_vector_alloc_irqs(struct irq_domain *domain, unsigned int virq,
531 unsigned int nr_irqs, void *arg)
532 {
533 struct irq_alloc_info *info = arg;
534 struct apic_chip_data *apicd;
535 struct irq_data *irqd;
536 int i, err, node;
537
538 if (disable_apic)
539 return -ENXIO;
540
541 /* Currently vector allocator can't guarantee contiguous allocations */
542 if ((info->flags & X86_IRQ_ALLOC_CONTIGUOUS_VECTORS) && nr_irqs > 1)
543 return -ENOSYS;
544
545 for (i = 0; i < nr_irqs; i++) {
546 irqd = irq_domain_get_irq_data(domain, virq + i);
547 BUG_ON(!irqd);
548 node = irq_data_get_node(irqd);
549 WARN_ON_ONCE(irqd->chip_data);
550 apicd = alloc_apic_chip_data(node);
551 if (!apicd) {
552 err = -ENOMEM;
553 goto error;
554 }
555
556 apicd->irq = virq + i;
557 irqd->chip = &lapic_controller;
558 irqd->chip_data = apicd;
559 irqd->hwirq = virq + i;
560 irqd_set_single_target(irqd);
561
562 /* Don't invoke affinity setter on deactivated interrupts */
563 irqd_set_affinity_on_activate(irqd);
564
565 /*
566 * Legacy vectors are already assigned when the IOAPIC
567 * takes them over. They stay on the same vector. This is
568 * required for check_timer() to work correctly as it might
569 * switch back to legacy mode. Only update the hardware
570 * config.
571 */
572 if (info->flags & X86_IRQ_ALLOC_LEGACY) {
573 if (!vector_configure_legacy(virq + i, irqd, apicd))
574 continue;
575 }
576
577 err = assign_irq_vector_policy(irqd, info);
578 trace_vector_setup(virq + i, false, err);
579 if (err) {
580 irqd->chip_data = NULL;
581 free_apic_chip_data(apicd);
582 goto error;
583 }
584 }
585
586 return 0;
587
588 error:
589 x86_vector_free_irqs(domain, virq, i);
590 return err;
591 }
592
593 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS
x86_vector_debug_show(struct seq_file * m,struct irq_domain * d,struct irq_data * irqd,int ind)594 static void x86_vector_debug_show(struct seq_file *m, struct irq_domain *d,
595 struct irq_data *irqd, int ind)
596 {
597 struct apic_chip_data apicd;
598 unsigned long flags;
599 int irq;
600
601 if (!irqd) {
602 irq_matrix_debug_show(m, vector_matrix, ind);
603 return;
604 }
605
606 irq = irqd->irq;
607 if (irq < nr_legacy_irqs() && !test_bit(irq, &io_apic_irqs)) {
608 seq_printf(m, "%*sVector: %5d\n", ind, "", ISA_IRQ_VECTOR(irq));
609 seq_printf(m, "%*sTarget: Legacy PIC all CPUs\n", ind, "");
610 return;
611 }
612
613 if (!irqd->chip_data) {
614 seq_printf(m, "%*sVector: Not assigned\n", ind, "");
615 return;
616 }
617
618 raw_spin_lock_irqsave(&vector_lock, flags);
619 memcpy(&apicd, irqd->chip_data, sizeof(apicd));
620 raw_spin_unlock_irqrestore(&vector_lock, flags);
621
622 seq_printf(m, "%*sVector: %5u\n", ind, "", apicd.vector);
623 seq_printf(m, "%*sTarget: %5u\n", ind, "", apicd.cpu);
624 if (apicd.prev_vector) {
625 seq_printf(m, "%*sPrevious vector: %5u\n", ind, "", apicd.prev_vector);
626 seq_printf(m, "%*sPrevious target: %5u\n", ind, "", apicd.prev_cpu);
627 }
628 seq_printf(m, "%*smove_in_progress: %u\n", ind, "", apicd.move_in_progress ? 1 : 0);
629 seq_printf(m, "%*sis_managed: %u\n", ind, "", apicd.is_managed ? 1 : 0);
630 seq_printf(m, "%*scan_reserve: %u\n", ind, "", apicd.can_reserve ? 1 : 0);
631 seq_printf(m, "%*shas_reserved: %u\n", ind, "", apicd.has_reserved ? 1 : 0);
632 seq_printf(m, "%*scleanup_pending: %u\n", ind, "", !hlist_unhashed(&apicd.clist));
633 }
634 #endif
635
636 static const struct irq_domain_ops x86_vector_domain_ops = {
637 .alloc = x86_vector_alloc_irqs,
638 .free = x86_vector_free_irqs,
639 .activate = x86_vector_activate,
640 .deactivate = x86_vector_deactivate,
641 #ifdef CONFIG_GENERIC_IRQ_DEBUGFS
642 .debug_show = x86_vector_debug_show,
643 #endif
644 };
645
arch_probe_nr_irqs(void)646 int __init arch_probe_nr_irqs(void)
647 {
648 int nr;
649
650 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
651 nr_irqs = NR_VECTORS * nr_cpu_ids;
652
653 nr = (gsi_top + nr_legacy_irqs()) + 8 * nr_cpu_ids;
654 #if defined(CONFIG_PCI_MSI)
655 /*
656 * for MSI and HT dyn irq
657 */
658 if (gsi_top <= NR_IRQS_LEGACY)
659 nr += 8 * nr_cpu_ids;
660 else
661 nr += gsi_top * 16;
662 #endif
663 if (nr < nr_irqs)
664 nr_irqs = nr;
665
666 /*
667 * We don't know if PIC is present at this point so we need to do
668 * probe() to get the right number of legacy IRQs.
669 */
670 return legacy_pic->probe();
671 }
672
lapic_assign_legacy_vector(unsigned int irq,bool replace)673 void lapic_assign_legacy_vector(unsigned int irq, bool replace)
674 {
675 /*
676 * Use assign system here so it wont get accounted as allocated
677 * and moveable in the cpu hotplug check and it prevents managed
678 * irq reservation from touching it.
679 */
680 irq_matrix_assign_system(vector_matrix, ISA_IRQ_VECTOR(irq), replace);
681 }
682
lapic_update_legacy_vectors(void)683 void __init lapic_update_legacy_vectors(void)
684 {
685 unsigned int i;
686
687 if (IS_ENABLED(CONFIG_X86_IO_APIC) && nr_ioapics > 0)
688 return;
689
690 /*
691 * If the IO/APIC is disabled via config, kernel command line or
692 * lack of enumeration then all legacy interrupts are routed
693 * through the PIC. Make sure that they are marked as legacy
694 * vectors. PIC_CASCADE_IRQ has already been marked in
695 * lapic_assign_system_vectors().
696 */
697 for (i = 0; i < nr_legacy_irqs(); i++) {
698 if (i != PIC_CASCADE_IR)
699 lapic_assign_legacy_vector(i, true);
700 }
701 }
702
lapic_assign_system_vectors(void)703 void __init lapic_assign_system_vectors(void)
704 {
705 unsigned int i, vector = 0;
706
707 for_each_set_bit_from(vector, system_vectors, NR_VECTORS)
708 irq_matrix_assign_system(vector_matrix, vector, false);
709
710 if (nr_legacy_irqs() > 1)
711 lapic_assign_legacy_vector(PIC_CASCADE_IR, false);
712
713 /* System vectors are reserved, online it */
714 irq_matrix_online(vector_matrix);
715
716 /* Mark the preallocated legacy interrupts */
717 for (i = 0; i < nr_legacy_irqs(); i++) {
718 if (i != PIC_CASCADE_IR)
719 irq_matrix_assign(vector_matrix, ISA_IRQ_VECTOR(i));
720 }
721 }
722
arch_early_irq_init(void)723 int __init arch_early_irq_init(void)
724 {
725 struct fwnode_handle *fn;
726
727 fn = irq_domain_alloc_named_fwnode("VECTOR");
728 BUG_ON(!fn);
729 x86_vector_domain = irq_domain_create_tree(fn, &x86_vector_domain_ops,
730 NULL);
731 BUG_ON(x86_vector_domain == NULL);
732 irq_set_default_host(x86_vector_domain);
733
734 arch_init_msi_domain(x86_vector_domain);
735
736 BUG_ON(!alloc_cpumask_var(&vector_searchmask, GFP_KERNEL));
737
738 /*
739 * Allocate the vector matrix allocator data structure and limit the
740 * search area.
741 */
742 vector_matrix = irq_alloc_matrix(NR_VECTORS, FIRST_EXTERNAL_VECTOR,
743 FIRST_SYSTEM_VECTOR);
744 BUG_ON(!vector_matrix);
745
746 return arch_early_ioapic_init();
747 }
748
749 #ifdef CONFIG_SMP
750
__setup_vector_irq(int vector)751 static struct irq_desc *__setup_vector_irq(int vector)
752 {
753 int isairq = vector - ISA_IRQ_VECTOR(0);
754
755 /* Check whether the irq is in the legacy space */
756 if (isairq < 0 || isairq >= nr_legacy_irqs())
757 return VECTOR_UNUSED;
758 /* Check whether the irq is handled by the IOAPIC */
759 if (test_bit(isairq, &io_apic_irqs))
760 return VECTOR_UNUSED;
761 return irq_to_desc(isairq);
762 }
763
764 /* Online the local APIC infrastructure and initialize the vectors */
lapic_online(void)765 void lapic_online(void)
766 {
767 unsigned int vector;
768
769 lockdep_assert_held(&vector_lock);
770
771 /* Online the vector matrix array for this CPU */
772 irq_matrix_online(vector_matrix);
773
774 /*
775 * The interrupt affinity logic never targets interrupts to offline
776 * CPUs. The exception are the legacy PIC interrupts. In general
777 * they are only targeted to CPU0, but depending on the platform
778 * they can be distributed to any online CPU in hardware. The
779 * kernel has no influence on that. So all active legacy vectors
780 * must be installed on all CPUs. All non legacy interrupts can be
781 * cleared.
782 */
783 for (vector = 0; vector < NR_VECTORS; vector++)
784 this_cpu_write(vector_irq[vector], __setup_vector_irq(vector));
785 }
786
lapic_offline(void)787 void lapic_offline(void)
788 {
789 lock_vector_lock();
790 irq_matrix_offline(vector_matrix);
791 unlock_vector_lock();
792 }
793
apic_set_affinity(struct irq_data * irqd,const struct cpumask * dest,bool force)794 static int apic_set_affinity(struct irq_data *irqd,
795 const struct cpumask *dest, bool force)
796 {
797 int err;
798
799 if (WARN_ON_ONCE(!irqd_is_activated(irqd)))
800 return -EIO;
801
802 raw_spin_lock(&vector_lock);
803 cpumask_and(vector_searchmask, dest, cpu_online_mask);
804 if (irqd_affinity_is_managed(irqd))
805 err = assign_managed_vector(irqd, vector_searchmask);
806 else
807 err = assign_vector_locked(irqd, vector_searchmask);
808 raw_spin_unlock(&vector_lock);
809 return err ? err : IRQ_SET_MASK_OK;
810 }
811
812 #else
813 # define apic_set_affinity NULL
814 #endif
815
apic_retrigger_irq(struct irq_data * irqd)816 static int apic_retrigger_irq(struct irq_data *irqd)
817 {
818 struct apic_chip_data *apicd = apic_chip_data(irqd);
819 unsigned long flags;
820
821 raw_spin_lock_irqsave(&vector_lock, flags);
822 apic->send_IPI(apicd->cpu, apicd->vector);
823 raw_spin_unlock_irqrestore(&vector_lock, flags);
824
825 return 1;
826 }
827
apic_ack_irq(struct irq_data * irqd)828 void apic_ack_irq(struct irq_data *irqd)
829 {
830 irq_move_irq(irqd);
831 ack_APIC_irq();
832 }
833
apic_ack_edge(struct irq_data * irqd)834 void apic_ack_edge(struct irq_data *irqd)
835 {
836 irq_complete_move(irqd_cfg(irqd));
837 apic_ack_irq(irqd);
838 }
839
840 static struct irq_chip lapic_controller = {
841 .name = "APIC",
842 .irq_ack = apic_ack_edge,
843 .irq_set_affinity = apic_set_affinity,
844 .irq_retrigger = apic_retrigger_irq,
845 };
846
847 #ifdef CONFIG_SMP
848
free_moved_vector(struct apic_chip_data * apicd)849 static void free_moved_vector(struct apic_chip_data *apicd)
850 {
851 unsigned int vector = apicd->prev_vector;
852 unsigned int cpu = apicd->prev_cpu;
853 bool managed = apicd->is_managed;
854
855 /*
856 * This should never happen. Managed interrupts are not
857 * migrated except on CPU down, which does not involve the
858 * cleanup vector. But try to keep the accounting correct
859 * nevertheless.
860 */
861 WARN_ON_ONCE(managed);
862
863 trace_vector_free_moved(apicd->irq, cpu, vector, managed);
864 irq_matrix_free(vector_matrix, cpu, vector, managed);
865 per_cpu(vector_irq, cpu)[vector] = VECTOR_UNUSED;
866 hlist_del_init(&apicd->clist);
867 apicd->prev_vector = 0;
868 apicd->move_in_progress = 0;
869 }
870
smp_irq_move_cleanup_interrupt(void)871 asmlinkage __visible void __irq_entry smp_irq_move_cleanup_interrupt(void)
872 {
873 struct hlist_head *clhead = this_cpu_ptr(&cleanup_list);
874 struct apic_chip_data *apicd;
875 struct hlist_node *tmp;
876
877 entering_ack_irq();
878 /* Prevent vectors vanishing under us */
879 raw_spin_lock(&vector_lock);
880
881 hlist_for_each_entry_safe(apicd, tmp, clhead, clist) {
882 unsigned int irr, vector = apicd->prev_vector;
883
884 /*
885 * Paranoia: Check if the vector that needs to be cleaned
886 * up is registered at the APICs IRR. If so, then this is
887 * not the best time to clean it up. Clean it up in the
888 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
889 * to this CPU. IRQ_MOVE_CLEANUP_VECTOR is the lowest
890 * priority external vector, so on return from this
891 * interrupt the device interrupt will happen first.
892 */
893 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
894 if (irr & (1U << (vector % 32))) {
895 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
896 continue;
897 }
898 free_moved_vector(apicd);
899 }
900
901 raw_spin_unlock(&vector_lock);
902 exiting_irq();
903 }
904
__send_cleanup_vector(struct apic_chip_data * apicd)905 static void __send_cleanup_vector(struct apic_chip_data *apicd)
906 {
907 unsigned int cpu;
908
909 raw_spin_lock(&vector_lock);
910 apicd->move_in_progress = 0;
911 cpu = apicd->prev_cpu;
912 if (cpu_online(cpu)) {
913 hlist_add_head(&apicd->clist, per_cpu_ptr(&cleanup_list, cpu));
914 apic->send_IPI(cpu, IRQ_MOVE_CLEANUP_VECTOR);
915 } else {
916 apicd->prev_vector = 0;
917 }
918 raw_spin_unlock(&vector_lock);
919 }
920
send_cleanup_vector(struct irq_cfg * cfg)921 void send_cleanup_vector(struct irq_cfg *cfg)
922 {
923 struct apic_chip_data *apicd;
924
925 apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg);
926 if (apicd->move_in_progress)
927 __send_cleanup_vector(apicd);
928 }
929
__irq_complete_move(struct irq_cfg * cfg,unsigned vector)930 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
931 {
932 struct apic_chip_data *apicd;
933
934 apicd = container_of(cfg, struct apic_chip_data, hw_irq_cfg);
935 if (likely(!apicd->move_in_progress))
936 return;
937
938 if (vector == apicd->vector && apicd->cpu == smp_processor_id())
939 __send_cleanup_vector(apicd);
940 }
941
irq_complete_move(struct irq_cfg * cfg)942 void irq_complete_move(struct irq_cfg *cfg)
943 {
944 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
945 }
946
947 /*
948 * Called from fixup_irqs() with @desc->lock held and interrupts disabled.
949 */
irq_force_complete_move(struct irq_desc * desc)950 void irq_force_complete_move(struct irq_desc *desc)
951 {
952 struct apic_chip_data *apicd;
953 struct irq_data *irqd;
954 unsigned int vector;
955
956 /*
957 * The function is called for all descriptors regardless of which
958 * irqdomain they belong to. For example if an IRQ is provided by
959 * an irq_chip as part of a GPIO driver, the chip data for that
960 * descriptor is specific to the irq_chip in question.
961 *
962 * Check first that the chip_data is what we expect
963 * (apic_chip_data) before touching it any further.
964 */
965 irqd = irq_domain_get_irq_data(x86_vector_domain,
966 irq_desc_get_irq(desc));
967 if (!irqd)
968 return;
969
970 raw_spin_lock(&vector_lock);
971 apicd = apic_chip_data(irqd);
972 if (!apicd)
973 goto unlock;
974
975 /*
976 * If prev_vector is empty, no action required.
977 */
978 vector = apicd->prev_vector;
979 if (!vector)
980 goto unlock;
981
982 /*
983 * This is tricky. If the cleanup of the old vector has not been
984 * done yet, then the following setaffinity call will fail with
985 * -EBUSY. This can leave the interrupt in a stale state.
986 *
987 * All CPUs are stuck in stop machine with interrupts disabled so
988 * calling __irq_complete_move() would be completely pointless.
989 *
990 * 1) The interrupt is in move_in_progress state. That means that we
991 * have not seen an interrupt since the io_apic was reprogrammed to
992 * the new vector.
993 *
994 * 2) The interrupt has fired on the new vector, but the cleanup IPIs
995 * have not been processed yet.
996 */
997 if (apicd->move_in_progress) {
998 /*
999 * In theory there is a race:
1000 *
1001 * set_ioapic(new_vector) <-- Interrupt is raised before update
1002 * is effective, i.e. it's raised on
1003 * the old vector.
1004 *
1005 * So if the target cpu cannot handle that interrupt before
1006 * the old vector is cleaned up, we get a spurious interrupt
1007 * and in the worst case the ioapic irq line becomes stale.
1008 *
1009 * But in case of cpu hotplug this should be a non issue
1010 * because if the affinity update happens right before all
1011 * cpus rendevouz in stop machine, there is no way that the
1012 * interrupt can be blocked on the target cpu because all cpus
1013 * loops first with interrupts enabled in stop machine, so the
1014 * old vector is not yet cleaned up when the interrupt fires.
1015 *
1016 * So the only way to run into this issue is if the delivery
1017 * of the interrupt on the apic/system bus would be delayed
1018 * beyond the point where the target cpu disables interrupts
1019 * in stop machine. I doubt that it can happen, but at least
1020 * there is a theroretical chance. Virtualization might be
1021 * able to expose this, but AFAICT the IOAPIC emulation is not
1022 * as stupid as the real hardware.
1023 *
1024 * Anyway, there is nothing we can do about that at this point
1025 * w/o refactoring the whole fixup_irq() business completely.
1026 * We print at least the irq number and the old vector number,
1027 * so we have the necessary information when a problem in that
1028 * area arises.
1029 */
1030 pr_warn("IRQ fixup: irq %d move in progress, old vector %d\n",
1031 irqd->irq, vector);
1032 }
1033 free_moved_vector(apicd);
1034 unlock:
1035 raw_spin_unlock(&vector_lock);
1036 }
1037
1038 #ifdef CONFIG_HOTPLUG_CPU
1039 /*
1040 * Note, this is not accurate accounting, but at least good enough to
1041 * prevent that the actual interrupt move will run out of vectors.
1042 */
lapic_can_unplug_cpu(void)1043 int lapic_can_unplug_cpu(void)
1044 {
1045 unsigned int rsvd, avl, tomove, cpu = smp_processor_id();
1046 int ret = 0;
1047
1048 raw_spin_lock(&vector_lock);
1049 tomove = irq_matrix_allocated(vector_matrix);
1050 avl = irq_matrix_available(vector_matrix, true);
1051 if (avl < tomove) {
1052 pr_warn("CPU %u has %u vectors, %u available. Cannot disable CPU\n",
1053 cpu, tomove, avl);
1054 ret = -ENOSPC;
1055 goto out;
1056 }
1057 rsvd = irq_matrix_reserved(vector_matrix);
1058 if (avl < rsvd) {
1059 pr_warn("Reserved vectors %u > available %u. IRQ request may fail\n",
1060 rsvd, avl);
1061 }
1062 out:
1063 raw_spin_unlock(&vector_lock);
1064 return ret;
1065 }
1066 #endif /* HOTPLUG_CPU */
1067 #endif /* SMP */
1068
print_APIC_field(int base)1069 static void __init print_APIC_field(int base)
1070 {
1071 int i;
1072
1073 printk(KERN_DEBUG);
1074
1075 for (i = 0; i < 8; i++)
1076 pr_cont("%08x", apic_read(base + i*0x10));
1077
1078 pr_cont("\n");
1079 }
1080
print_local_APIC(void * dummy)1081 static void __init print_local_APIC(void *dummy)
1082 {
1083 unsigned int i, v, ver, maxlvt;
1084 u64 icr;
1085
1086 pr_debug("printing local APIC contents on CPU#%d/%d:\n",
1087 smp_processor_id(), hard_smp_processor_id());
1088 v = apic_read(APIC_ID);
1089 pr_info("... APIC ID: %08x (%01x)\n", v, read_apic_id());
1090 v = apic_read(APIC_LVR);
1091 pr_info("... APIC VERSION: %08x\n", v);
1092 ver = GET_APIC_VERSION(v);
1093 maxlvt = lapic_get_maxlvt();
1094
1095 v = apic_read(APIC_TASKPRI);
1096 pr_debug("... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1097
1098 /* !82489DX */
1099 if (APIC_INTEGRATED(ver)) {
1100 if (!APIC_XAPIC(ver)) {
1101 v = apic_read(APIC_ARBPRI);
1102 pr_debug("... APIC ARBPRI: %08x (%02x)\n",
1103 v, v & APIC_ARBPRI_MASK);
1104 }
1105 v = apic_read(APIC_PROCPRI);
1106 pr_debug("... APIC PROCPRI: %08x\n", v);
1107 }
1108
1109 /*
1110 * Remote read supported only in the 82489DX and local APIC for
1111 * Pentium processors.
1112 */
1113 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1114 v = apic_read(APIC_RRR);
1115 pr_debug("... APIC RRR: %08x\n", v);
1116 }
1117
1118 v = apic_read(APIC_LDR);
1119 pr_debug("... APIC LDR: %08x\n", v);
1120 if (!x2apic_enabled()) {
1121 v = apic_read(APIC_DFR);
1122 pr_debug("... APIC DFR: %08x\n", v);
1123 }
1124 v = apic_read(APIC_SPIV);
1125 pr_debug("... APIC SPIV: %08x\n", v);
1126
1127 pr_debug("... APIC ISR field:\n");
1128 print_APIC_field(APIC_ISR);
1129 pr_debug("... APIC TMR field:\n");
1130 print_APIC_field(APIC_TMR);
1131 pr_debug("... APIC IRR field:\n");
1132 print_APIC_field(APIC_IRR);
1133
1134 /* !82489DX */
1135 if (APIC_INTEGRATED(ver)) {
1136 /* Due to the Pentium erratum 3AP. */
1137 if (maxlvt > 3)
1138 apic_write(APIC_ESR, 0);
1139
1140 v = apic_read(APIC_ESR);
1141 pr_debug("... APIC ESR: %08x\n", v);
1142 }
1143
1144 icr = apic_icr_read();
1145 pr_debug("... APIC ICR: %08x\n", (u32)icr);
1146 pr_debug("... APIC ICR2: %08x\n", (u32)(icr >> 32));
1147
1148 v = apic_read(APIC_LVTT);
1149 pr_debug("... APIC LVTT: %08x\n", v);
1150
1151 if (maxlvt > 3) {
1152 /* PC is LVT#4. */
1153 v = apic_read(APIC_LVTPC);
1154 pr_debug("... APIC LVTPC: %08x\n", v);
1155 }
1156 v = apic_read(APIC_LVT0);
1157 pr_debug("... APIC LVT0: %08x\n", v);
1158 v = apic_read(APIC_LVT1);
1159 pr_debug("... APIC LVT1: %08x\n", v);
1160
1161 if (maxlvt > 2) {
1162 /* ERR is LVT#3. */
1163 v = apic_read(APIC_LVTERR);
1164 pr_debug("... APIC LVTERR: %08x\n", v);
1165 }
1166
1167 v = apic_read(APIC_TMICT);
1168 pr_debug("... APIC TMICT: %08x\n", v);
1169 v = apic_read(APIC_TMCCT);
1170 pr_debug("... APIC TMCCT: %08x\n", v);
1171 v = apic_read(APIC_TDCR);
1172 pr_debug("... APIC TDCR: %08x\n", v);
1173
1174 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1175 v = apic_read(APIC_EFEAT);
1176 maxlvt = (v >> 16) & 0xff;
1177 pr_debug("... APIC EFEAT: %08x\n", v);
1178 v = apic_read(APIC_ECTRL);
1179 pr_debug("... APIC ECTRL: %08x\n", v);
1180 for (i = 0; i < maxlvt; i++) {
1181 v = apic_read(APIC_EILVTn(i));
1182 pr_debug("... APIC EILVT%d: %08x\n", i, v);
1183 }
1184 }
1185 pr_cont("\n");
1186 }
1187
print_local_APICs(int maxcpu)1188 static void __init print_local_APICs(int maxcpu)
1189 {
1190 int cpu;
1191
1192 if (!maxcpu)
1193 return;
1194
1195 preempt_disable();
1196 for_each_online_cpu(cpu) {
1197 if (cpu >= maxcpu)
1198 break;
1199 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1200 }
1201 preempt_enable();
1202 }
1203
print_PIC(void)1204 static void __init print_PIC(void)
1205 {
1206 unsigned int v;
1207 unsigned long flags;
1208
1209 if (!nr_legacy_irqs())
1210 return;
1211
1212 pr_debug("\nprinting PIC contents\n");
1213
1214 raw_spin_lock_irqsave(&i8259A_lock, flags);
1215
1216 v = inb(0xa1) << 8 | inb(0x21);
1217 pr_debug("... PIC IMR: %04x\n", v);
1218
1219 v = inb(0xa0) << 8 | inb(0x20);
1220 pr_debug("... PIC IRR: %04x\n", v);
1221
1222 outb(0x0b, 0xa0);
1223 outb(0x0b, 0x20);
1224 v = inb(0xa0) << 8 | inb(0x20);
1225 outb(0x0a, 0xa0);
1226 outb(0x0a, 0x20);
1227
1228 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1229
1230 pr_debug("... PIC ISR: %04x\n", v);
1231
1232 v = inb(0x4d1) << 8 | inb(0x4d0);
1233 pr_debug("... PIC ELCR: %04x\n", v);
1234 }
1235
1236 static int show_lapic __initdata = 1;
setup_show_lapic(char * arg)1237 static __init int setup_show_lapic(char *arg)
1238 {
1239 int num = -1;
1240
1241 if (strcmp(arg, "all") == 0) {
1242 show_lapic = CONFIG_NR_CPUS;
1243 } else {
1244 get_option(&arg, &num);
1245 if (num >= 0)
1246 show_lapic = num;
1247 }
1248
1249 return 1;
1250 }
1251 __setup("show_lapic=", setup_show_lapic);
1252
print_ICs(void)1253 static int __init print_ICs(void)
1254 {
1255 if (apic_verbosity == APIC_QUIET)
1256 return 0;
1257
1258 print_PIC();
1259
1260 /* don't print out if apic is not there */
1261 if (!boot_cpu_has(X86_FEATURE_APIC) && !apic_from_smp_config())
1262 return 0;
1263
1264 print_local_APICs(show_lapic);
1265 print_IO_APICs();
1266
1267 return 0;
1268 }
1269
1270 late_initcall(print_ICs);
1271