1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: Erin.Lo <erin.lo@mediatek.com> 5 * 6 */ 7 8#include <dt-bindings/clock/mt2701-clk.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/power/mt2701-power.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/memory/mt2701-larb-port.h> 14#include <dt-bindings/reset/mt2701-resets.h> 15#include "mt2701-pinfunc.h" 16 17/ { 18 #address-cells = <2>; 19 #size-cells = <2>; 20 compatible = "mediatek,mt2701"; 21 interrupt-parent = <&cirq>; 22 23 cpus { 24 #address-cells = <1>; 25 #size-cells = <0>; 26 enable-method = "mediatek,mt81xx-tz-smp"; 27 28 cpu@0 { 29 device_type = "cpu"; 30 compatible = "arm,cortex-a7"; 31 reg = <0x0>; 32 }; 33 cpu@1 { 34 device_type = "cpu"; 35 compatible = "arm,cortex-a7"; 36 reg = <0x1>; 37 }; 38 cpu@2 { 39 device_type = "cpu"; 40 compatible = "arm,cortex-a7"; 41 reg = <0x2>; 42 }; 43 cpu@3 { 44 device_type = "cpu"; 45 compatible = "arm,cortex-a7"; 46 reg = <0x3>; 47 }; 48 }; 49 50 reserved-memory { 51 #address-cells = <2>; 52 #size-cells = <2>; 53 ranges; 54 55 trustzone-bootinfo@80002000 { 56 compatible = "mediatek,trustzone-bootinfo"; 57 reg = <0 0x80002000 0 0x1000>; 58 }; 59 }; 60 61 system_clk: dummy13m { 62 compatible = "fixed-clock"; 63 clock-frequency = <13000000>; 64 #clock-cells = <0>; 65 }; 66 67 rtc_clk: dummy32k { 68 compatible = "fixed-clock"; 69 clock-frequency = <32000>; 70 #clock-cells = <0>; 71 }; 72 73 clk26m: oscillator@0 { 74 compatible = "fixed-clock"; 75 #clock-cells = <0>; 76 clock-frequency = <26000000>; 77 clock-output-names = "clk26m"; 78 }; 79 80 rtc32k: oscillator@1 { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 clock-frequency = <32000>; 84 clock-output-names = "rtc32k"; 85 }; 86 87 thermal-zones { 88 cpu_thermal: cpu_thermal { 89 polling-delay-passive = <1000>; /* milliseconds */ 90 polling-delay = <1000>; /* milliseconds */ 91 92 thermal-sensors = <&thermal 0>; 93 sustainable-power = <1000>; 94 95 trips { 96 threshold: trip-point@0 { 97 temperature = <68000>; 98 hysteresis = <2000>; 99 type = "passive"; 100 }; 101 102 target: trip-point@1 { 103 temperature = <85000>; 104 hysteresis = <2000>; 105 type = "passive"; 106 }; 107 108 cpu_crit: cpu_crit@0 { 109 temperature = <115000>; 110 hysteresis = <2000>; 111 type = "critical"; 112 }; 113 }; 114 }; 115 }; 116 117 timer { 118 compatible = "arm,armv7-timer"; 119 interrupt-parent = <&gic>; 120 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 121 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 122 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 123 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 124 }; 125 126 topckgen: syscon@10000000 { 127 compatible = "mediatek,mt2701-topckgen", "syscon"; 128 reg = <0 0x10000000 0 0x1000>; 129 #clock-cells = <1>; 130 }; 131 132 infracfg: syscon@10001000 { 133 compatible = "mediatek,mt2701-infracfg", "syscon"; 134 reg = <0 0x10001000 0 0x1000>; 135 #clock-cells = <1>; 136 #reset-cells = <1>; 137 }; 138 139 pericfg: syscon@10003000 { 140 compatible = "mediatek,mt2701-pericfg", "syscon"; 141 reg = <0 0x10003000 0 0x1000>; 142 #clock-cells = <1>; 143 #reset-cells = <1>; 144 }; 145 146 syscfg_pctl_a: syscfg@10005000 { 147 compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon"; 148 reg = <0 0x10005000 0 0x1000>; 149 }; 150 151 scpsys: scpsys@10006000 { 152 compatible = "mediatek,mt2701-scpsys", "syscon"; 153 #power-domain-cells = <1>; 154 reg = <0 0x10006000 0 0x1000>; 155 infracfg = <&infracfg>; 156 clocks = <&topckgen CLK_TOP_MM_SEL>, 157 <&topckgen CLK_TOP_MFG_SEL>, 158 <&topckgen CLK_TOP_ETHIF_SEL>; 159 clock-names = "mm", "mfg", "ethif"; 160 }; 161 162 watchdog: watchdog@10007000 { 163 compatible = "mediatek,mt2701-wdt", 164 "mediatek,mt6589-wdt"; 165 reg = <0 0x10007000 0 0x100>; 166 }; 167 168 timer: timer@10008000 { 169 compatible = "mediatek,mt2701-timer", 170 "mediatek,mt6577-timer"; 171 reg = <0 0x10008000 0 0x80>; 172 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>; 173 clocks = <&system_clk>, <&rtc_clk>; 174 clock-names = "system-clk", "rtc-clk"; 175 }; 176 177 pio: pinctrl@1000b000 { 178 compatible = "mediatek,mt2701-pinctrl"; 179 reg = <0 0x1000b000 0 0x1000>; 180 mediatek,pctl-regmap = <&syscfg_pctl_a>; 181 pins-are-numbered; 182 gpio-controller; 183 #gpio-cells = <2>; 184 interrupt-controller; 185 #interrupt-cells = <2>; 186 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 188 }; 189 190 smi_common: smi@1000c000 { 191 compatible = "mediatek,mt2701-smi-common"; 192 reg = <0 0x1000c000 0 0x1000>; 193 clocks = <&infracfg CLK_INFRA_SMI>, 194 <&mmsys CLK_MM_SMI_COMMON>, 195 <&infracfg CLK_INFRA_SMI>; 196 clock-names = "apb", "smi", "async"; 197 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; 198 }; 199 200 sysirq: interrupt-controller@10200100 { 201 compatible = "mediatek,mt2701-sysirq", 202 "mediatek,mt6577-sysirq"; 203 interrupt-controller; 204 #interrupt-cells = <3>; 205 interrupt-parent = <&gic>; 206 reg = <0 0x10200100 0 0x1c>; 207 }; 208 209 cirq: interrupt-controller@10204000 { 210 compatible = "mediatek,mt2701-cirq", 211 "mediatek,mtk-cirq"; 212 interrupt-controller; 213 #interrupt-cells = <3>; 214 interrupt-parent = <&sysirq>; 215 reg = <0 0x10204000 0 0x400>; 216 mediatek,ext-irq-range = <32 200>; 217 }; 218 219 iommu: mmsys_iommu@10205000 { 220 compatible = "mediatek,mt2701-m4u"; 221 reg = <0 0x10205000 0 0x1000>; 222 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>; 223 clocks = <&infracfg CLK_INFRA_M4U>; 224 clock-names = "bclk"; 225 mediatek,larbs = <&larb0 &larb1 &larb2>; 226 #iommu-cells = <1>; 227 }; 228 229 apmixedsys: syscon@10209000 { 230 compatible = "mediatek,mt2701-apmixedsys", "syscon"; 231 reg = <0 0x10209000 0 0x1000>; 232 #clock-cells = <1>; 233 }; 234 235 gic: interrupt-controller@10211000 { 236 compatible = "arm,cortex-a7-gic"; 237 interrupt-controller; 238 #interrupt-cells = <3>; 239 interrupt-parent = <&gic>; 240 reg = <0 0x10211000 0 0x1000>, 241 <0 0x10212000 0 0x2000>, 242 <0 0x10214000 0 0x2000>, 243 <0 0x10216000 0 0x2000>; 244 }; 245 246 auxadc: adc@11001000 { 247 compatible = "mediatek,mt2701-auxadc"; 248 reg = <0 0x11001000 0 0x1000>; 249 clocks = <&pericfg CLK_PERI_AUXADC>; 250 clock-names = "main"; 251 #io-channel-cells = <1>; 252 status = "disabled"; 253 }; 254 255 uart0: serial@11002000 { 256 compatible = "mediatek,mt2701-uart", 257 "mediatek,mt6577-uart"; 258 reg = <0 0x11002000 0 0x400>; 259 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>; 260 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 261 clock-names = "baud", "bus"; 262 status = "disabled"; 263 }; 264 265 uart1: serial@11003000 { 266 compatible = "mediatek,mt2701-uart", 267 "mediatek,mt6577-uart"; 268 reg = <0 0x11003000 0 0x400>; 269 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 270 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 271 clock-names = "baud", "bus"; 272 status = "disabled"; 273 }; 274 275 uart2: serial@11004000 { 276 compatible = "mediatek,mt2701-uart", 277 "mediatek,mt6577-uart"; 278 reg = <0 0x11004000 0 0x400>; 279 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>; 280 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 281 clock-names = "baud", "bus"; 282 status = "disabled"; 283 }; 284 285 uart3: serial@11005000 { 286 compatible = "mediatek,mt2701-uart", 287 "mediatek,mt6577-uart"; 288 reg = <0 0x11005000 0 0x400>; 289 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>; 290 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 291 clock-names = "baud", "bus"; 292 status = "disabled"; 293 }; 294 295 i2c0: i2c@11007000 { 296 compatible = "mediatek,mt2701-i2c", 297 "mediatek,mt6577-i2c"; 298 reg = <0 0x11007000 0 0x70>, 299 <0 0x11000200 0 0x80>; 300 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>; 301 clock-div = <16>; 302 clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>; 303 clock-names = "main", "dma"; 304 #address-cells = <1>; 305 #size-cells = <0>; 306 status = "disabled"; 307 }; 308 309 i2c1: i2c@11008000 { 310 compatible = "mediatek,mt2701-i2c", 311 "mediatek,mt6577-i2c"; 312 reg = <0 0x11008000 0 0x70>, 313 <0 0x11000280 0 0x80>; 314 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>; 315 clock-div = <16>; 316 clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>; 317 clock-names = "main", "dma"; 318 #address-cells = <1>; 319 #size-cells = <0>; 320 status = "disabled"; 321 }; 322 323 i2c2: i2c@11009000 { 324 compatible = "mediatek,mt2701-i2c", 325 "mediatek,mt6577-i2c"; 326 reg = <0 0x11009000 0 0x70>, 327 <0 0x11000300 0 0x80>; 328 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>; 329 clock-div = <16>; 330 clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>; 331 clock-names = "main", "dma"; 332 #address-cells = <1>; 333 #size-cells = <0>; 334 status = "disabled"; 335 }; 336 337 spi0: spi@1100a000 { 338 compatible = "mediatek,mt2701-spi"; 339 #address-cells = <1>; 340 #size-cells = <0>; 341 reg = <0 0x1100a000 0 0x100>; 342 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 343 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 344 <&topckgen CLK_TOP_SPI0_SEL>, 345 <&pericfg CLK_PERI_SPI0>; 346 clock-names = "parent-clk", "sel-clk", "spi-clk"; 347 status = "disabled"; 348 }; 349 350 thermal: thermal@1100b000 { 351 #thermal-sensor-cells = <0>; 352 compatible = "mediatek,mt2701-thermal"; 353 reg = <0 0x1100b000 0 0x1000>; 354 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>; 355 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 356 clock-names = "therm", "auxadc"; 357 resets = <&pericfg MT2701_PERI_THERM_SW_RST>; 358 reset-names = "therm"; 359 mediatek,auxadc = <&auxadc>; 360 mediatek,apmixedsys = <&apmixedsys>; 361 }; 362 363 nandc: nfi@1100d000 { 364 compatible = "mediatek,mt2701-nfc"; 365 reg = <0 0x1100d000 0 0x1000>; 366 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>; 367 clocks = <&pericfg CLK_PERI_NFI>, 368 <&pericfg CLK_PERI_NFI_PAD>; 369 clock-names = "nfi_clk", "pad_clk"; 370 status = "disabled"; 371 ecc-engine = <&bch>; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 }; 375 376 bch: ecc@1100e000 { 377 compatible = "mediatek,mt2701-ecc"; 378 reg = <0 0x1100e000 0 0x1000>; 379 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>; 380 clocks = <&pericfg CLK_PERI_NFI_ECC>; 381 clock-names = "nfiecc_clk"; 382 status = "disabled"; 383 }; 384 385 nor_flash: spi@11014000 { 386 compatible = "mediatek,mt2701-nor", 387 "mediatek,mt8173-nor"; 388 reg = <0 0x11014000 0 0xe0>; 389 clocks = <&pericfg CLK_PERI_FLASH>, 390 <&topckgen CLK_TOP_FLASH_SEL>; 391 clock-names = "spi", "sf"; 392 #address-cells = <1>; 393 #size-cells = <0>; 394 status = "disabled"; 395 }; 396 397 spi1: spi@11016000 { 398 compatible = "mediatek,mt2701-spi"; 399 #address-cells = <1>; 400 #size-cells = <0>; 401 reg = <0 0x11016000 0 0x100>; 402 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 403 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 404 <&topckgen CLK_TOP_SPI1_SEL>, 405 <&pericfg CLK_PERI_SPI1>; 406 clock-names = "parent-clk", "sel-clk", "spi-clk"; 407 status = "disabled"; 408 }; 409 410 spi2: spi@11017000 { 411 compatible = "mediatek,mt2701-spi"; 412 #address-cells = <1>; 413 #size-cells = <0>; 414 reg = <0 0x11017000 0 0x1000>; 415 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>; 416 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 417 <&topckgen CLK_TOP_SPI2_SEL>, 418 <&pericfg CLK_PERI_SPI2>; 419 clock-names = "parent-clk", "sel-clk", "spi-clk"; 420 status = "disabled"; 421 }; 422 423 audsys: clock-controller@11220000 { 424 compatible = "mediatek,mt2701-audsys", "syscon"; 425 reg = <0 0x11220000 0 0x2000>; 426 #clock-cells = <1>; 427 428 afe: audio-controller { 429 compatible = "mediatek,mt2701-audio"; 430 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, 431 <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 432 interrupt-names = "afe", "asys"; 433 power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; 434 435 clocks = <&infracfg CLK_INFRA_AUDIO>, 436 <&topckgen CLK_TOP_AUD_MUX1_SEL>, 437 <&topckgen CLK_TOP_AUD_MUX2_SEL>, 438 <&topckgen CLK_TOP_AUD_48K_TIMING>, 439 <&topckgen CLK_TOP_AUD_44K_TIMING>, 440 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>, 441 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>, 442 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>, 443 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>, 444 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>, 445 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>, 446 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>, 447 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>, 448 <&topckgen CLK_TOP_AUD_I2S1_MCLK>, 449 <&topckgen CLK_TOP_AUD_I2S2_MCLK>, 450 <&topckgen CLK_TOP_AUD_I2S3_MCLK>, 451 <&topckgen CLK_TOP_AUD_I2S4_MCLK>, 452 <&audsys CLK_AUD_I2SO1>, 453 <&audsys CLK_AUD_I2SO2>, 454 <&audsys CLK_AUD_I2SO3>, 455 <&audsys CLK_AUD_I2SO4>, 456 <&audsys CLK_AUD_I2SIN1>, 457 <&audsys CLK_AUD_I2SIN2>, 458 <&audsys CLK_AUD_I2SIN3>, 459 <&audsys CLK_AUD_I2SIN4>, 460 <&audsys CLK_AUD_ASRCO1>, 461 <&audsys CLK_AUD_ASRCO2>, 462 <&audsys CLK_AUD_ASRCO3>, 463 <&audsys CLK_AUD_ASRCO4>, 464 <&audsys CLK_AUD_AFE>, 465 <&audsys CLK_AUD_AFE_CONN>, 466 <&audsys CLK_AUD_A1SYS>, 467 <&audsys CLK_AUD_A2SYS>, 468 <&audsys CLK_AUD_AFE_MRGIF>; 469 470 clock-names = "infra_sys_audio_clk", 471 "top_audio_mux1_sel", 472 "top_audio_mux2_sel", 473 "top_audio_a1sys_hp", 474 "top_audio_a2sys_hp", 475 "i2s0_src_sel", 476 "i2s1_src_sel", 477 "i2s2_src_sel", 478 "i2s3_src_sel", 479 "i2s0_src_div", 480 "i2s1_src_div", 481 "i2s2_src_div", 482 "i2s3_src_div", 483 "i2s0_mclk_en", 484 "i2s1_mclk_en", 485 "i2s2_mclk_en", 486 "i2s3_mclk_en", 487 "i2so0_hop_ck", 488 "i2so1_hop_ck", 489 "i2so2_hop_ck", 490 "i2so3_hop_ck", 491 "i2si0_hop_ck", 492 "i2si1_hop_ck", 493 "i2si2_hop_ck", 494 "i2si3_hop_ck", 495 "asrc0_out_ck", 496 "asrc1_out_ck", 497 "asrc2_out_ck", 498 "asrc3_out_ck", 499 "audio_afe_pd", 500 "audio_afe_conn_pd", 501 "audio_a1sys_pd", 502 "audio_a2sys_pd", 503 "audio_mrgif_pd"; 504 505 assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, 506 <&topckgen CLK_TOP_AUD_MUX2_SEL>, 507 <&topckgen CLK_TOP_AUD_MUX1_DIV>, 508 <&topckgen CLK_TOP_AUD_MUX2_DIV>; 509 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, 510 <&topckgen CLK_TOP_AUD2PLL_90M>; 511 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; 512 }; 513 }; 514 515 mmsys: syscon@14000000 { 516 compatible = "mediatek,mt2701-mmsys", "syscon"; 517 reg = <0 0x14000000 0 0x1000>; 518 #clock-cells = <1>; 519 }; 520 521 bls: pwm@1400a000 { 522 compatible = "mediatek,mt2701-disp-pwm"; 523 reg = <0 0x1400a000 0 0x1000>; 524 #pwm-cells = <2>; 525 clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>; 526 clock-names = "main", "mm"; 527 status = "disabled"; 528 }; 529 530 larb0: larb@14010000 { 531 compatible = "mediatek,mt2701-smi-larb"; 532 reg = <0 0x14010000 0 0x1000>; 533 mediatek,smi = <&smi_common>; 534 mediatek,larb-id = <0>; 535 clocks = <&mmsys CLK_MM_SMI_LARB0>, 536 <&mmsys CLK_MM_SMI_LARB0>; 537 clock-names = "apb", "smi"; 538 power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; 539 }; 540 541 imgsys: syscon@15000000 { 542 compatible = "mediatek,mt2701-imgsys", "syscon"; 543 reg = <0 0x15000000 0 0x1000>; 544 #clock-cells = <1>; 545 }; 546 547 larb2: larb@15001000 { 548 compatible = "mediatek,mt2701-smi-larb"; 549 reg = <0 0x15001000 0 0x1000>; 550 mediatek,smi = <&smi_common>; 551 mediatek,larb-id = <2>; 552 clocks = <&imgsys CLK_IMG_SMI_COMM>, 553 <&imgsys CLK_IMG_SMI_COMM>; 554 clock-names = "apb", "smi"; 555 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; 556 }; 557 558 jpegdec: jpegdec@15004000 { 559 compatible = "mediatek,mt2701-jpgdec"; 560 reg = <0 0x15004000 0 0x1000>; 561 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; 562 clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, 563 <&imgsys CLK_IMG_JPGDEC>; 564 clock-names = "jpgdec-smi", 565 "jpgdec"; 566 power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; 567 mediatek,larb = <&larb2>; 568 iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, 569 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; 570 }; 571 572 vdecsys: syscon@16000000 { 573 compatible = "mediatek,mt2701-vdecsys", "syscon"; 574 reg = <0 0x16000000 0 0x1000>; 575 #clock-cells = <1>; 576 }; 577 578 larb1: larb@16010000 { 579 compatible = "mediatek,mt2701-smi-larb"; 580 reg = <0 0x16010000 0 0x1000>; 581 mediatek,smi = <&smi_common>; 582 mediatek,larb-id = <1>; 583 clocks = <&vdecsys CLK_VDEC_CKGEN>, 584 <&vdecsys CLK_VDEC_LARB>; 585 clock-names = "apb", "smi"; 586 power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>; 587 }; 588 589 hifsys: syscon@1a000000 { 590 compatible = "mediatek,mt2701-hifsys", "syscon"; 591 reg = <0 0x1a000000 0 0x1000>; 592 #clock-cells = <1>; 593 #reset-cells = <1>; 594 }; 595 596 usb0: usb@1a1c0000 { 597 compatible = "mediatek,mt8173-xhci"; 598 reg = <0 0x1a1c0000 0 0x1000>, 599 <0 0x1a1c4700 0 0x0100>; 600 reg-names = "mac", "ippc"; 601 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>; 602 clocks = <&hifsys CLK_HIFSYS_USB0PHY>, 603 <&topckgen CLK_TOP_ETHIF_SEL>; 604 clock-names = "sys_ck", "ref_ck"; 605 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; 606 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; 607 status = "disabled"; 608 }; 609 610 u3phy0: usb-phy@1a1c4000 { 611 compatible = "mediatek,mt2701-u3phy"; 612 reg = <0 0x1a1c4000 0 0x0700>; 613 #address-cells = <2>; 614 #size-cells = <2>; 615 ranges; 616 status = "disabled"; 617 618 u2port0: usb-phy@1a1c4800 { 619 reg = <0 0x1a1c4800 0 0x0100>; 620 clocks = <&topckgen CLK_TOP_USB_PHY48M>; 621 clock-names = "ref"; 622 #phy-cells = <1>; 623 status = "okay"; 624 }; 625 626 u3port0: usb-phy@1a1c4900 { 627 reg = <0 0x1a1c4900 0 0x0700>; 628 clocks = <&clk26m>; 629 clock-names = "ref"; 630 #phy-cells = <1>; 631 status = "okay"; 632 }; 633 }; 634 635 usb1: usb@1a240000 { 636 compatible = "mediatek,mt8173-xhci"; 637 reg = <0 0x1a240000 0 0x1000>, 638 <0 0x1a244700 0 0x0100>; 639 reg-names = "mac", "ippc"; 640 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>; 641 clocks = <&hifsys CLK_HIFSYS_USB1PHY>, 642 <&topckgen CLK_TOP_ETHIF_SEL>; 643 clock-names = "sys_ck", "ref_ck"; 644 power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; 645 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 646 status = "disabled"; 647 }; 648 649 u3phy1: usb-phy@1a244000 { 650 compatible = "mediatek,mt2701-u3phy"; 651 reg = <0 0x1a244000 0 0x0700>; 652 #address-cells = <2>; 653 #size-cells = <2>; 654 ranges; 655 status = "disabled"; 656 657 u2port1: usb-phy@1a244800 { 658 reg = <0 0x1a244800 0 0x0100>; 659 clocks = <&topckgen CLK_TOP_USB_PHY48M>; 660 clock-names = "ref"; 661 #phy-cells = <1>; 662 status = "okay"; 663 }; 664 665 u3port1: usb-phy@1a244900 { 666 reg = <0 0x1a244900 0 0x0700>; 667 clocks = <&clk26m>; 668 clock-names = "ref"; 669 #phy-cells = <1>; 670 status = "okay"; 671 }; 672 }; 673 674 ethsys: syscon@1b000000 { 675 compatible = "mediatek,mt2701-ethsys", "syscon"; 676 reg = <0 0x1b000000 0 0x1000>; 677 #clock-cells = <1>; 678 #reset-cells = <1>; 679 }; 680 681 eth: ethernet@1b100000 { 682 compatible = "mediatek,mt2701-eth", "syscon"; 683 reg = <0 0x1b100000 0 0x20000>; 684 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>, 685 <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>, 686 <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; 687 clocks = <&topckgen CLK_TOP_ETHIF_SEL>, 688 <ðsys CLK_ETHSYS_ESW>, 689 <ðsys CLK_ETHSYS_GP1>, 690 <ðsys CLK_ETHSYS_GP2>, 691 <&apmixedsys CLK_APMIXED_TRGPLL>; 692 clock-names = "ethif", "esw", "gp1", "gp2", "trgpll"; 693 resets = <ðsys MT2701_ETHSYS_FE_RST>, 694 <ðsys MT2701_ETHSYS_GMAC_RST>, 695 <ðsys MT2701_ETHSYS_PPE_RST>; 696 reset-names = "fe", "gmac", "ppe"; 697 power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>; 698 mediatek,ethsys = <ðsys>; 699 mediatek,pctl = <&syscfg_pctl_a>; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 status = "disabled"; 703 }; 704 705 bdpsys: syscon@1c000000 { 706 compatible = "mediatek,mt2701-bdpsys", "syscon"; 707 reg = <0 0x1c000000 0 0x1000>; 708 #clock-cells = <1>; 709 }; 710}; 711