1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
7 *
8 * SMP support for BMIPS
9 */
10
11 #include <linux/init.h>
12 #include <linux/sched.h>
13 #include <linux/sched/hotplug.h>
14 #include <linux/sched/task_stack.h>
15 #include <linux/mm.h>
16 #include <linux/delay.h>
17 #include <linux/smp.h>
18 #include <linux/interrupt.h>
19 #include <linux/spinlock.h>
20 #include <linux/cpu.h>
21 #include <linux/cpumask.h>
22 #include <linux/reboot.h>
23 #include <linux/io.h>
24 #include <linux/compiler.h>
25 #include <linux/linkage.h>
26 #include <linux/bug.h>
27 #include <linux/kernel.h>
28 #include <linux/kexec.h>
29
30 #include <asm/time.h>
31 #include <asm/pgtable.h>
32 #include <asm/processor.h>
33 #include <asm/bootinfo.h>
34 #include <asm/pmon.h>
35 #include <asm/cacheflush.h>
36 #include <asm/tlbflush.h>
37 #include <asm/mipsregs.h>
38 #include <asm/bmips.h>
39 #include <asm/traps.h>
40 #include <asm/barrier.h>
41 #include <asm/cpu-features.h>
42
43 static int __maybe_unused max_cpus = 1;
44
45 /* these may be configured by the platform code */
46 int bmips_smp_enabled = 1;
47 int bmips_cpu_offset;
48 cpumask_t bmips_booted_mask;
49 unsigned long bmips_tp1_irqs = IE_IRQ1;
50
51 #define RESET_FROM_KSEG0 0x80080800
52 #define RESET_FROM_KSEG1 0xa0080800
53
54 static void bmips_set_reset_vec(int cpu, u32 val);
55
56 #ifdef CONFIG_SMP
57
58 /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
59 unsigned long bmips_smp_boot_sp;
60 unsigned long bmips_smp_boot_gp;
61
62 static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
63 static void bmips5000_send_ipi_single(int cpu, unsigned int action);
64 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
65 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);
66
67 /* SW interrupts 0,1 are used for interprocessor signaling */
68 #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
69 #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
70
71 #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
72 #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
73 #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
74 #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
75
bmips_smp_setup(void)76 static void __init bmips_smp_setup(void)
77 {
78 int i, cpu = 1, boot_cpu = 0;
79 int cpu_hw_intr;
80
81 switch (current_cpu_type()) {
82 case CPU_BMIPS4350:
83 case CPU_BMIPS4380:
84 /* arbitration priority */
85 clear_c0_brcm_cmt_ctrl(0x30);
86
87 /* NBK and weak order flags */
88 set_c0_brcm_config_0(0x30000);
89
90 /* Find out if we are running on TP0 or TP1 */
91 boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
92
93 /*
94 * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
95 * thread
96 * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
97 * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
98 */
99 if (boot_cpu == 0)
100 cpu_hw_intr = 0x02;
101 else
102 cpu_hw_intr = 0x1d;
103
104 change_c0_brcm_cmt_intr(0xf8018000,
105 (cpu_hw_intr << 27) | (0x03 << 15));
106
107 /* single core, 2 threads (2 pipelines) */
108 max_cpus = 2;
109
110 break;
111 case CPU_BMIPS5000:
112 /* enable raceless SW interrupts */
113 set_c0_brcm_config(0x03 << 22);
114
115 /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
116 change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
117
118 /* N cores, 2 threads per core */
119 max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
120
121 /* clear any pending SW interrupts */
122 for (i = 0; i < max_cpus; i++) {
123 write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
124 write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
125 }
126
127 break;
128 default:
129 max_cpus = 1;
130 }
131
132 if (!bmips_smp_enabled)
133 max_cpus = 1;
134
135 /* this can be overridden by the BSP */
136 if (!board_ebase_setup)
137 board_ebase_setup = &bmips_ebase_setup;
138
139 __cpu_number_map[boot_cpu] = 0;
140 __cpu_logical_map[0] = boot_cpu;
141
142 for (i = 0; i < max_cpus; i++) {
143 if (i != boot_cpu) {
144 __cpu_number_map[i] = cpu;
145 __cpu_logical_map[cpu] = i;
146 cpu++;
147 }
148 set_cpu_possible(i, 1);
149 set_cpu_present(i, 1);
150 }
151 }
152
153 /*
154 * IPI IRQ setup - runs on CPU0
155 */
bmips_prepare_cpus(unsigned int max_cpus)156 static void bmips_prepare_cpus(unsigned int max_cpus)
157 {
158 irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id);
159
160 switch (current_cpu_type()) {
161 case CPU_BMIPS4350:
162 case CPU_BMIPS4380:
163 bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
164 break;
165 case CPU_BMIPS5000:
166 bmips_ipi_interrupt = bmips5000_ipi_interrupt;
167 break;
168 default:
169 return;
170 }
171
172 if (request_irq(IPI0_IRQ, bmips_ipi_interrupt,
173 IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi0", NULL))
174 panic("Can't request IPI0 interrupt");
175 if (request_irq(IPI1_IRQ, bmips_ipi_interrupt,
176 IRQF_PERCPU | IRQF_NO_SUSPEND, "smp_ipi1", NULL))
177 panic("Can't request IPI1 interrupt");
178 }
179
180 /*
181 * Tell the hardware to boot CPUx - runs on CPU0
182 */
bmips_boot_secondary(int cpu,struct task_struct * idle)183 static int bmips_boot_secondary(int cpu, struct task_struct *idle)
184 {
185 bmips_smp_boot_sp = __KSTK_TOS(idle);
186 bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
187 mb();
188
189 /*
190 * Initial boot sequence for secondary CPU:
191 * bmips_reset_nmi_vec @ a000_0000 ->
192 * bmips_smp_entry ->
193 * plat_wired_tlb_setup (cached function call; optional) ->
194 * start_secondary (cached jump)
195 *
196 * Warm restart sequence:
197 * play_dead WAIT loop ->
198 * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
199 * eret to play_dead ->
200 * bmips_secondary_reentry ->
201 * start_secondary
202 */
203
204 pr_info("SMP: Booting CPU%d...\n", cpu);
205
206 if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
207 /* kseg1 might not exist if this CPU enabled XKS01 */
208 bmips_set_reset_vec(cpu, RESET_FROM_KSEG0);
209
210 switch (current_cpu_type()) {
211 case CPU_BMIPS4350:
212 case CPU_BMIPS4380:
213 bmips43xx_send_ipi_single(cpu, 0);
214 break;
215 case CPU_BMIPS5000:
216 bmips5000_send_ipi_single(cpu, 0);
217 break;
218 }
219 } else {
220 bmips_set_reset_vec(cpu, RESET_FROM_KSEG1);
221
222 switch (current_cpu_type()) {
223 case CPU_BMIPS4350:
224 case CPU_BMIPS4380:
225 /* Reset slave TP1 if booting from TP0 */
226 if (cpu_logical_map(cpu) == 1)
227 set_c0_brcm_cmt_ctrl(0x01);
228 break;
229 case CPU_BMIPS5000:
230 write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
231 break;
232 }
233 cpumask_set_cpu(cpu, &bmips_booted_mask);
234 }
235
236 return 0;
237 }
238
239 /*
240 * Early setup - runs on secondary CPU after cache probe
241 */
bmips_init_secondary(void)242 static void bmips_init_secondary(void)
243 {
244 bmips_cpu_setup();
245
246 switch (current_cpu_type()) {
247 case CPU_BMIPS4350:
248 case CPU_BMIPS4380:
249 clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
250 break;
251 case CPU_BMIPS5000:
252 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
253 cpu_set_core(¤t_cpu_data, (read_c0_brcm_config() >> 25) & 3);
254 break;
255 }
256 }
257
258 /*
259 * Late setup - runs on secondary CPU before entering the idle loop
260 */
bmips_smp_finish(void)261 static void bmips_smp_finish(void)
262 {
263 pr_info("SMP: CPU%d is running\n", smp_processor_id());
264
265 /* make sure there won't be a timer interrupt for a little while */
266 write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
267
268 irq_enable_hazard();
269 set_c0_status(IE_SW0 | IE_SW1 | bmips_tp1_irqs | IE_IRQ5 | ST0_IE);
270 irq_enable_hazard();
271 }
272
273 /*
274 * BMIPS5000 raceless IPIs
275 *
276 * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
277 * IPI0 is used for SMP_RESCHEDULE_YOURSELF
278 * IPI1 is used for SMP_CALL_FUNCTION
279 */
280
bmips5000_send_ipi_single(int cpu,unsigned int action)281 static void bmips5000_send_ipi_single(int cpu, unsigned int action)
282 {
283 write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
284 }
285
bmips5000_ipi_interrupt(int irq,void * dev_id)286 static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
287 {
288 int action = irq - IPI0_IRQ;
289
290 write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
291
292 if (action == 0)
293 scheduler_ipi();
294 else
295 generic_smp_call_function_interrupt();
296
297 return IRQ_HANDLED;
298 }
299
bmips5000_send_ipi_mask(const struct cpumask * mask,unsigned int action)300 static void bmips5000_send_ipi_mask(const struct cpumask *mask,
301 unsigned int action)
302 {
303 unsigned int i;
304
305 for_each_cpu(i, mask)
306 bmips5000_send_ipi_single(i, action);
307 }
308
309 /*
310 * BMIPS43xx racey IPIs
311 *
312 * We use one inbound SW IRQ for each CPU.
313 *
314 * A spinlock must be held in order to keep CPUx from accidentally clearing
315 * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
316 * same spinlock is used to protect the action masks.
317 */
318
319 static DEFINE_SPINLOCK(ipi_lock);
320 static DEFINE_PER_CPU(int, ipi_action_mask);
321
bmips43xx_send_ipi_single(int cpu,unsigned int action)322 static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
323 {
324 unsigned long flags;
325
326 spin_lock_irqsave(&ipi_lock, flags);
327 set_c0_cause(cpu ? C_SW1 : C_SW0);
328 per_cpu(ipi_action_mask, cpu) |= action;
329 irq_enable_hazard();
330 spin_unlock_irqrestore(&ipi_lock, flags);
331 }
332
bmips43xx_ipi_interrupt(int irq,void * dev_id)333 static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
334 {
335 unsigned long flags;
336 int action, cpu = irq - IPI0_IRQ;
337
338 spin_lock_irqsave(&ipi_lock, flags);
339 action = __this_cpu_read(ipi_action_mask);
340 per_cpu(ipi_action_mask, cpu) = 0;
341 clear_c0_cause(cpu ? C_SW1 : C_SW0);
342 spin_unlock_irqrestore(&ipi_lock, flags);
343
344 if (action & SMP_RESCHEDULE_YOURSELF)
345 scheduler_ipi();
346 if (action & SMP_CALL_FUNCTION)
347 generic_smp_call_function_interrupt();
348
349 return IRQ_HANDLED;
350 }
351
bmips43xx_send_ipi_mask(const struct cpumask * mask,unsigned int action)352 static void bmips43xx_send_ipi_mask(const struct cpumask *mask,
353 unsigned int action)
354 {
355 unsigned int i;
356
357 for_each_cpu(i, mask)
358 bmips43xx_send_ipi_single(i, action);
359 }
360
361 #ifdef CONFIG_HOTPLUG_CPU
362
bmips_cpu_disable(void)363 static int bmips_cpu_disable(void)
364 {
365 unsigned int cpu = smp_processor_id();
366
367 if (cpu == 0)
368 return -EBUSY;
369
370 pr_info("SMP: CPU%d is offline\n", cpu);
371
372 set_cpu_online(cpu, false);
373 calculate_cpu_foreign_map();
374 irq_cpu_offline();
375 clear_c0_status(IE_IRQ5);
376
377 local_flush_tlb_all();
378 local_flush_icache_range(0, ~0);
379
380 return 0;
381 }
382
bmips_cpu_die(unsigned int cpu)383 static void bmips_cpu_die(unsigned int cpu)
384 {
385 }
386
play_dead(void)387 void __ref play_dead(void)
388 {
389 idle_task_exit();
390
391 /* flush data cache */
392 _dma_cache_wback_inv(0, ~0);
393
394 /*
395 * Wakeup is on SW0 or SW1; disable everything else
396 * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
397 * IRQ handlers; this clears ST0_IE and returns immediately.
398 */
399 clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
400 change_c0_status(
401 IE_IRQ5 | bmips_tp1_irqs | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
402 IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
403 irq_disable_hazard();
404
405 /*
406 * wait for SW interrupt from bmips_boot_secondary(), then jump
407 * back to start_secondary()
408 */
409 __asm__ __volatile__(
410 " wait\n"
411 " j bmips_secondary_reentry\n"
412 : : : "memory");
413 }
414
415 #endif /* CONFIG_HOTPLUG_CPU */
416
417 const struct plat_smp_ops bmips43xx_smp_ops = {
418 .smp_setup = bmips_smp_setup,
419 .prepare_cpus = bmips_prepare_cpus,
420 .boot_secondary = bmips_boot_secondary,
421 .smp_finish = bmips_smp_finish,
422 .init_secondary = bmips_init_secondary,
423 .send_ipi_single = bmips43xx_send_ipi_single,
424 .send_ipi_mask = bmips43xx_send_ipi_mask,
425 #ifdef CONFIG_HOTPLUG_CPU
426 .cpu_disable = bmips_cpu_disable,
427 .cpu_die = bmips_cpu_die,
428 #endif
429 #ifdef CONFIG_KEXEC
430 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump,
431 #endif
432 };
433
434 const struct plat_smp_ops bmips5000_smp_ops = {
435 .smp_setup = bmips_smp_setup,
436 .prepare_cpus = bmips_prepare_cpus,
437 .boot_secondary = bmips_boot_secondary,
438 .smp_finish = bmips_smp_finish,
439 .init_secondary = bmips_init_secondary,
440 .send_ipi_single = bmips5000_send_ipi_single,
441 .send_ipi_mask = bmips5000_send_ipi_mask,
442 #ifdef CONFIG_HOTPLUG_CPU
443 .cpu_disable = bmips_cpu_disable,
444 .cpu_die = bmips_cpu_die,
445 #endif
446 #ifdef CONFIG_KEXEC
447 .kexec_nonboot_cpu = kexec_nonboot_cpu_jump,
448 #endif
449 };
450
451 #endif /* CONFIG_SMP */
452
453 /***********************************************************************
454 * BMIPS vector relocation
455 * This is primarily used for SMP boot, but it is applicable to some
456 * UP BMIPS systems as well.
457 ***********************************************************************/
458
bmips_wr_vec(unsigned long dst,char * start,char * end)459 static void bmips_wr_vec(unsigned long dst, char *start, char *end)
460 {
461 memcpy((void *)dst, start, end - start);
462 dma_cache_wback(dst, end - start);
463 local_flush_icache_range(dst, dst + (end - start));
464 instruction_hazard();
465 }
466
bmips_nmi_handler_setup(void)467 static inline void bmips_nmi_handler_setup(void)
468 {
469 bmips_wr_vec(BMIPS_NMI_RESET_VEC, bmips_reset_nmi_vec,
470 bmips_reset_nmi_vec_end);
471 bmips_wr_vec(BMIPS_WARM_RESTART_VEC, bmips_smp_int_vec,
472 bmips_smp_int_vec_end);
473 }
474
475 struct reset_vec_info {
476 int cpu;
477 u32 val;
478 };
479
bmips_set_reset_vec_remote(void * vinfo)480 static void bmips_set_reset_vec_remote(void *vinfo)
481 {
482 struct reset_vec_info *info = vinfo;
483 int shift = info->cpu & 0x01 ? 16 : 0;
484 u32 mask = ~(0xffff << shift), val = info->val >> 16;
485
486 preempt_disable();
487 if (smp_processor_id() > 0) {
488 smp_call_function_single(0, &bmips_set_reset_vec_remote,
489 info, 1);
490 } else {
491 if (info->cpu & 0x02) {
492 /* BMIPS5200 "should" use mask/shift, but it's buggy */
493 bmips_write_zscm_reg(0xa0, (val << 16) | val);
494 bmips_read_zscm_reg(0xa0);
495 } else {
496 write_c0_brcm_bootvec((read_c0_brcm_bootvec() & mask) |
497 (val << shift));
498 }
499 }
500 preempt_enable();
501 }
502
bmips_set_reset_vec(int cpu,u32 val)503 static void bmips_set_reset_vec(int cpu, u32 val)
504 {
505 struct reset_vec_info info;
506
507 if (current_cpu_type() == CPU_BMIPS5000) {
508 /* this needs to run from CPU0 (which is always online) */
509 info.cpu = cpu;
510 info.val = val;
511 bmips_set_reset_vec_remote(&info);
512 } else {
513 void __iomem *cbr = BMIPS_GET_CBR();
514
515 if (cpu == 0)
516 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
517 else {
518 if (current_cpu_type() != CPU_BMIPS4380)
519 return;
520 __raw_writel(val, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
521 }
522 }
523 __sync();
524 back_to_back_c0_hazard();
525 }
526
bmips_ebase_setup(void)527 void bmips_ebase_setup(void)
528 {
529 unsigned long new_ebase = ebase;
530
531 BUG_ON(ebase != CKSEG0);
532
533 switch (current_cpu_type()) {
534 case CPU_BMIPS4350:
535 /*
536 * BMIPS4350 cannot relocate the normal vectors, but it
537 * can relocate the BEV=1 vectors. So CPU1 starts up at
538 * the relocated BEV=1, IV=0 general exception vector @
539 * 0xa000_0380.
540 *
541 * set_uncached_handler() is used here because:
542 * - CPU1 will run this from uncached space
543 * - None of the cacheflush functions are set up yet
544 */
545 set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
546 &bmips_smp_int_vec, 0x80);
547 __sync();
548 return;
549 case CPU_BMIPS3300:
550 case CPU_BMIPS4380:
551 /*
552 * 0x8000_0000: reset/NMI (initially in kseg1)
553 * 0x8000_0400: normal vectors
554 */
555 new_ebase = 0x80000400;
556 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
557 break;
558 case CPU_BMIPS5000:
559 /*
560 * 0x8000_0000: reset/NMI (initially in kseg1)
561 * 0x8000_1000: normal vectors
562 */
563 new_ebase = 0x80001000;
564 bmips_set_reset_vec(0, RESET_FROM_KSEG0);
565 write_c0_ebase(new_ebase);
566 break;
567 default:
568 return;
569 }
570
571 board_nmi_handler_setup = &bmips_nmi_handler_setup;
572 ebase = new_ebase;
573 }
574
plat_wired_tlb_setup(void)575 asmlinkage void __weak plat_wired_tlb_setup(void)
576 {
577 /*
578 * Called when starting/restarting a secondary CPU.
579 * Kernel stacks and other important data might only be accessible
580 * once the wired entries are present.
581 */
582 }
583
bmips_cpu_setup(void)584 void bmips_cpu_setup(void)
585 {
586 void __iomem __maybe_unused *cbr = BMIPS_GET_CBR();
587 u32 __maybe_unused cfg;
588
589 switch (current_cpu_type()) {
590 case CPU_BMIPS3300:
591 /* Set BIU to async mode */
592 set_c0_brcm_bus_pll(BIT(22));
593 __sync();
594
595 /* put the BIU back in sync mode */
596 clear_c0_brcm_bus_pll(BIT(22));
597
598 /* clear BHTD to enable branch history table */
599 clear_c0_brcm_reset(BIT(16));
600
601 /* Flush and enable RAC */
602 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
603 __raw_writel(cfg | 0x100, cbr + BMIPS_RAC_CONFIG);
604 __raw_readl(cbr + BMIPS_RAC_CONFIG);
605
606 cfg = __raw_readl(cbr + BMIPS_RAC_CONFIG);
607 __raw_writel(cfg | 0xf, cbr + BMIPS_RAC_CONFIG);
608 __raw_readl(cbr + BMIPS_RAC_CONFIG);
609
610 cfg = __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
611 __raw_writel(cfg | 0x0fff0000, cbr + BMIPS_RAC_ADDRESS_RANGE);
612 __raw_readl(cbr + BMIPS_RAC_ADDRESS_RANGE);
613 break;
614
615 case CPU_BMIPS4380:
616 /* CBG workaround for early BMIPS4380 CPUs */
617 switch (read_c0_prid()) {
618 case 0x2a040:
619 case 0x2a042:
620 case 0x2a044:
621 case 0x2a060:
622 cfg = __raw_readl(cbr + BMIPS_L2_CONFIG);
623 __raw_writel(cfg & ~0x07000000, cbr + BMIPS_L2_CONFIG);
624 __raw_readl(cbr + BMIPS_L2_CONFIG);
625 }
626
627 /* clear BHTD to enable branch history table */
628 clear_c0_brcm_config_0(BIT(21));
629
630 /* XI/ROTR enable */
631 set_c0_brcm_config_0(BIT(23));
632 set_c0_brcm_cmt_ctrl(BIT(15));
633 break;
634
635 case CPU_BMIPS5000:
636 /* enable RDHWR, BRDHWR */
637 set_c0_brcm_config(BIT(17) | BIT(21));
638
639 /* Disable JTB */
640 __asm__ __volatile__(
641 " .set noreorder\n"
642 " li $8, 0x5a455048\n"
643 " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */
644 " .word 0x4008b008\n" /* mfc0 t0, $22, 8 */
645 " li $9, 0x00008000\n"
646 " or $8, $8, $9\n"
647 " .word 0x4088b008\n" /* mtc0 t0, $22, 8 */
648 " sync\n"
649 " li $8, 0x0\n"
650 " .word 0x4088b00f\n" /* mtc0 t0, $22, 15 */
651 " .set reorder\n"
652 : : : "$8", "$9");
653
654 /* XI enable */
655 set_c0_brcm_config(BIT(27));
656
657 /* enable MIPS32R2 ROR instruction for XI TLB handlers */
658 __asm__ __volatile__(
659 " li $8, 0x5a455048\n"
660 " .word 0x4088b00f\n" /* mtc0 $8, $22, 15 */
661 " nop; nop; nop\n"
662 " .word 0x4008b008\n" /* mfc0 $8, $22, 8 */
663 " lui $9, 0x0100\n"
664 " or $8, $9\n"
665 " .word 0x4088b008\n" /* mtc0 $8, $22, 8 */
666 : : : "$8", "$9");
667 break;
668 }
669 }
670