1 /*
2 * Performance events x86 architecture header
3 *
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
11 *
12 * For licencing details see kernel-base/COPYING
13 */
14
15 #include <linux/perf_event.h>
16
17 #include <asm/intel_ds.h>
18
19 /* To enable MSR tracing please use the generic trace points. */
20
21 /*
22 * | NHM/WSM | SNB |
23 * register -------------------------------
24 * | HT | no HT | HT | no HT |
25 *-----------------------------------------
26 * offcore | core | core | cpu | core |
27 * lbr_sel | core | core | cpu | core |
28 * ld_lat | cpu | core | cpu | core |
29 *-----------------------------------------
30 *
31 * Given that there is a small number of shared regs,
32 * we can pre-allocate their slot in the per-cpu
33 * per-core reg tables.
34 */
35 enum extra_reg_type {
36 EXTRA_REG_NONE = -1, /* not used */
37
38 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
39 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
40 EXTRA_REG_LBR = 2, /* lbr_select */
41 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */
42 EXTRA_REG_FE = 4, /* fe_* */
43
44 EXTRA_REG_MAX /* number of entries needed */
45 };
46
47 struct event_constraint {
48 union {
49 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
50 u64 idxmsk64;
51 };
52 u64 code;
53 u64 cmask;
54 int weight;
55 int overlap;
56 int flags;
57 unsigned int size;
58 };
59
constraint_match(struct event_constraint * c,u64 ecode)60 static inline bool constraint_match(struct event_constraint *c, u64 ecode)
61 {
62 return ((ecode & c->cmask) - c->code) <= (u64)c->size;
63 }
64
65 /*
66 * struct hw_perf_event.flags flags
67 */
68 #define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */
69 #define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */
70 #define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */
71 #define PERF_X86_EVENT_PEBS_LD_HSW 0x0008 /* haswell style datala, load */
72 #define PERF_X86_EVENT_PEBS_NA_HSW 0x0010 /* haswell style datala, unknown */
73 #define PERF_X86_EVENT_EXCL 0x0020 /* HT exclusivity on counter */
74 #define PERF_X86_EVENT_DYNAMIC 0x0040 /* dynamic alloc'd constraint */
75 #define PERF_X86_EVENT_RDPMC_ALLOWED 0x0080 /* grant rdpmc permission */
76 #define PERF_X86_EVENT_EXCL_ACCT 0x0100 /* accounted EXCL event */
77 #define PERF_X86_EVENT_AUTO_RELOAD 0x0200 /* use PEBS auto-reload */
78 #define PERF_X86_EVENT_LARGE_PEBS 0x0400 /* use large PEBS */
79 #define PERF_X86_EVENT_PEBS_VIA_PT 0x0800 /* use PT buffer for PEBS */
80 #define PERF_X86_EVENT_PAIR 0x1000 /* Large Increment per Cycle */
81
82 struct amd_nb {
83 int nb_id; /* NorthBridge id */
84 int refcnt; /* reference count */
85 struct perf_event *owners[X86_PMC_IDX_MAX];
86 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
87 };
88
89 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1)
90 #define PEBS_PMI_AFTER_EACH_RECORD BIT_ULL(60)
91 #define PEBS_OUTPUT_OFFSET 61
92 #define PEBS_OUTPUT_MASK (3ull << PEBS_OUTPUT_OFFSET)
93 #define PEBS_OUTPUT_PT (1ull << PEBS_OUTPUT_OFFSET)
94 #define PEBS_VIA_PT_MASK (PEBS_OUTPUT_PT | PEBS_PMI_AFTER_EACH_RECORD)
95
96 /*
97 * Flags PEBS can handle without an PMI.
98 *
99 * TID can only be handled by flushing at context switch.
100 * REGS_USER can be handled for events limited to ring 3.
101 *
102 */
103 #define LARGE_PEBS_FLAGS \
104 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
105 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
106 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
107 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
108 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \
109 PERF_SAMPLE_PERIOD)
110
111 #define PEBS_GP_REGS \
112 ((1ULL << PERF_REG_X86_AX) | \
113 (1ULL << PERF_REG_X86_BX) | \
114 (1ULL << PERF_REG_X86_CX) | \
115 (1ULL << PERF_REG_X86_DX) | \
116 (1ULL << PERF_REG_X86_DI) | \
117 (1ULL << PERF_REG_X86_SI) | \
118 (1ULL << PERF_REG_X86_SP) | \
119 (1ULL << PERF_REG_X86_BP) | \
120 (1ULL << PERF_REG_X86_IP) | \
121 (1ULL << PERF_REG_X86_FLAGS) | \
122 (1ULL << PERF_REG_X86_R8) | \
123 (1ULL << PERF_REG_X86_R9) | \
124 (1ULL << PERF_REG_X86_R10) | \
125 (1ULL << PERF_REG_X86_R11) | \
126 (1ULL << PERF_REG_X86_R12) | \
127 (1ULL << PERF_REG_X86_R13) | \
128 (1ULL << PERF_REG_X86_R14) | \
129 (1ULL << PERF_REG_X86_R15))
130
131 /*
132 * Per register state.
133 */
134 struct er_account {
135 raw_spinlock_t lock; /* per-core: protect structure */
136 u64 config; /* extra MSR config */
137 u64 reg; /* extra MSR number */
138 atomic_t ref; /* reference count */
139 };
140
141 /*
142 * Per core/cpu state
143 *
144 * Used to coordinate shared registers between HT threads or
145 * among events on a single PMU.
146 */
147 struct intel_shared_regs {
148 struct er_account regs[EXTRA_REG_MAX];
149 int refcnt; /* per-core: #HT threads */
150 unsigned core_id; /* per-core: core id */
151 };
152
153 enum intel_excl_state_type {
154 INTEL_EXCL_UNUSED = 0, /* counter is unused */
155 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */
156 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */
157 };
158
159 struct intel_excl_states {
160 enum intel_excl_state_type state[X86_PMC_IDX_MAX];
161 bool sched_started; /* true if scheduling has started */
162 };
163
164 struct intel_excl_cntrs {
165 raw_spinlock_t lock;
166
167 struct intel_excl_states states[2];
168
169 union {
170 u16 has_exclusive[2];
171 u32 exclusive_present;
172 };
173
174 int refcnt; /* per-core: #HT threads */
175 unsigned core_id; /* per-core: core id */
176 };
177
178 struct x86_perf_task_context;
179 #define MAX_LBR_ENTRIES 32
180
181 enum {
182 X86_PERF_KFREE_SHARED = 0,
183 X86_PERF_KFREE_EXCL = 1,
184 X86_PERF_KFREE_MAX
185 };
186
187 struct cpu_hw_events {
188 /*
189 * Generic x86 PMC bits
190 */
191 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
192 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
193 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
194 int enabled;
195
196 int n_events; /* the # of events in the below arrays */
197 int n_added; /* the # last events in the below arrays;
198 they've never been enabled yet */
199 int n_txn; /* the # last events in the below arrays;
200 added in the current transaction */
201 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
202 u64 tags[X86_PMC_IDX_MAX];
203
204 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
205 struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
206
207 int n_excl; /* the number of exclusive events */
208
209 unsigned int txn_flags;
210 int is_fake;
211
212 /*
213 * Intel DebugStore bits
214 */
215 struct debug_store *ds;
216 void *ds_pebs_vaddr;
217 void *ds_bts_vaddr;
218 u64 pebs_enabled;
219 int n_pebs;
220 int n_large_pebs;
221 int n_pebs_via_pt;
222 int pebs_output;
223
224 /* Current super set of events hardware configuration */
225 u64 pebs_data_cfg;
226 u64 active_pebs_data_cfg;
227 int pebs_record_size;
228
229 /*
230 * Intel LBR bits
231 */
232 int lbr_users;
233 int lbr_pebs_users;
234 struct perf_branch_stack lbr_stack;
235 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
236 struct er_account *lbr_sel;
237 u64 br_sel;
238 struct x86_perf_task_context *last_task_ctx;
239 int last_log_id;
240
241 /*
242 * Intel host/guest exclude bits
243 */
244 u64 intel_ctrl_guest_mask;
245 u64 intel_ctrl_host_mask;
246 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
247
248 /*
249 * Intel checkpoint mask
250 */
251 u64 intel_cp_status;
252
253 /*
254 * manage shared (per-core, per-cpu) registers
255 * used on Intel NHM/WSM/SNB
256 */
257 struct intel_shared_regs *shared_regs;
258 /*
259 * manage exclusive counter access between hyperthread
260 */
261 struct event_constraint *constraint_list; /* in enable order */
262 struct intel_excl_cntrs *excl_cntrs;
263 int excl_thread_id; /* 0 or 1 */
264
265 /*
266 * SKL TSX_FORCE_ABORT shadow
267 */
268 u64 tfa_shadow;
269
270 /*
271 * AMD specific bits
272 */
273 struct amd_nb *amd_nb;
274 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
275 u64 perf_ctr_virt_mask;
276
277 void *kfree_on_online[X86_PERF_KFREE_MAX];
278 };
279
280 #define __EVENT_CONSTRAINT_RANGE(c, e, n, m, w, o, f) { \
281 { .idxmsk64 = (n) }, \
282 .code = (c), \
283 .size = (e) - (c), \
284 .cmask = (m), \
285 .weight = (w), \
286 .overlap = (o), \
287 .flags = f, \
288 }
289
290 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) \
291 __EVENT_CONSTRAINT_RANGE(c, c, n, m, w, o, f)
292
293 #define EVENT_CONSTRAINT(c, n, m) \
294 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
295
296 /*
297 * The constraint_match() function only works for 'simple' event codes
298 * and not for extended (AMD64_EVENTSEL_EVENT) events codes.
299 */
300 #define EVENT_CONSTRAINT_RANGE(c, e, n, m) \
301 __EVENT_CONSTRAINT_RANGE(c, e, n, m, HWEIGHT(n), 0, 0)
302
303 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \
304 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\
305 0, PERF_X86_EVENT_EXCL)
306
307 /*
308 * The overlap flag marks event constraints with overlapping counter
309 * masks. This is the case if the counter mask of such an event is not
310 * a subset of any other counter mask of a constraint with an equal or
311 * higher weight, e.g.:
312 *
313 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
314 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
315 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
316 *
317 * The event scheduler may not select the correct counter in the first
318 * cycle because it needs to know which subsequent events will be
319 * scheduled. It may fail to schedule the events then. So we set the
320 * overlap flag for such constraints to give the scheduler a hint which
321 * events to select for counter rescheduling.
322 *
323 * Care must be taken as the rescheduling algorithm is O(n!) which
324 * will increase scheduling cycles for an over-committed system
325 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
326 * and its counter masks must be kept at a minimum.
327 */
328 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
329 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
330
331 /*
332 * Constraint on the Event code.
333 */
334 #define INTEL_EVENT_CONSTRAINT(c, n) \
335 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
336
337 /*
338 * Constraint on a range of Event codes
339 */
340 #define INTEL_EVENT_CONSTRAINT_RANGE(c, e, n) \
341 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT)
342
343 /*
344 * Constraint on the Event code + UMask + fixed-mask
345 *
346 * filter mask to validate fixed counter events.
347 * the following filters disqualify for fixed counters:
348 * - inv
349 * - edge
350 * - cnt-mask
351 * - in_tx
352 * - in_tx_checkpointed
353 * The other filters are supported by fixed counters.
354 * The any-thread option is supported starting with v3.
355 */
356 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
357 #define FIXED_EVENT_CONSTRAINT(c, n) \
358 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
359
360 /*
361 * Constraint on the Event code + UMask
362 */
363 #define INTEL_UEVENT_CONSTRAINT(c, n) \
364 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
365
366 /* Constraint on specific umask bit only + event */
367 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \
368 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c))
369
370 /* Like UEVENT_CONSTRAINT, but match flags too */
371 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \
372 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
373
374 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \
375 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
376 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL)
377
378 #define INTEL_PLD_CONSTRAINT(c, n) \
379 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
380 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
381
382 #define INTEL_PST_CONSTRAINT(c, n) \
383 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
384 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
385
386 /* Event constraint, but match on all event flags too. */
387 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
388 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
389
390 #define INTEL_FLAGS_EVENT_CONSTRAINT_RANGE(c, e, n) \
391 EVENT_CONSTRAINT_RANGE(c, e, n, ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS)
392
393 /* Check only flags, but allow all event/umask */
394 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \
395 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
396
397 /* Check flags and event code, and set the HSW store flag */
398 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \
399 __EVENT_CONSTRAINT(code, n, \
400 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
401 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
402
403 /* Check flags and event code, and set the HSW load flag */
404 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \
405 __EVENT_CONSTRAINT(code, n, \
406 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
407 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
408
409 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD_RANGE(code, end, n) \
410 __EVENT_CONSTRAINT_RANGE(code, end, n, \
411 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
412 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
413
414 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \
415 __EVENT_CONSTRAINT(code, n, \
416 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
417 HWEIGHT(n), 0, \
418 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
419
420 /* Check flags and event code/umask, and set the HSW store flag */
421 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
422 __EVENT_CONSTRAINT(code, n, \
423 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
424 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
425
426 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \
427 __EVENT_CONSTRAINT(code, n, \
428 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
429 HWEIGHT(n), 0, \
430 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL)
431
432 /* Check flags and event code/umask, and set the HSW load flag */
433 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
434 __EVENT_CONSTRAINT(code, n, \
435 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
436 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
437
438 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \
439 __EVENT_CONSTRAINT(code, n, \
440 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
441 HWEIGHT(n), 0, \
442 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
443
444 /* Check flags and event code/umask, and set the HSW N/A flag */
445 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
446 __EVENT_CONSTRAINT(code, n, \
447 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
448 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW)
449
450
451 /*
452 * We define the end marker as having a weight of -1
453 * to enable blacklisting of events using a counter bitmask
454 * of zero and thus a weight of zero.
455 * The end marker has a weight that cannot possibly be
456 * obtained from counting the bits in the bitmask.
457 */
458 #define EVENT_CONSTRAINT_END { .weight = -1 }
459
460 /*
461 * Check for end marker with weight == -1
462 */
463 #define for_each_event_constraint(e, c) \
464 for ((e) = (c); (e)->weight != -1; (e)++)
465
466 /*
467 * Extra registers for specific events.
468 *
469 * Some events need large masks and require external MSRs.
470 * Those extra MSRs end up being shared for all events on
471 * a PMU and sometimes between PMU of sibling HT threads.
472 * In either case, the kernel needs to handle conflicting
473 * accesses to those extra, shared, regs. The data structure
474 * to manage those registers is stored in cpu_hw_event.
475 */
476 struct extra_reg {
477 unsigned int event;
478 unsigned int msr;
479 u64 config_mask;
480 u64 valid_mask;
481 int idx; /* per_xxx->regs[] reg index */
482 bool extra_msr_access;
483 };
484
485 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
486 .event = (e), \
487 .msr = (ms), \
488 .config_mask = (m), \
489 .valid_mask = (vm), \
490 .idx = EXTRA_REG_##i, \
491 .extra_msr_access = true, \
492 }
493
494 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
495 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
496
497 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
498 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
499 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
500
501 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
502 INTEL_UEVENT_EXTRA_REG(c, \
503 MSR_PEBS_LD_LAT_THRESHOLD, \
504 0xffff, \
505 LDLAT)
506
507 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
508
509 union perf_capabilities {
510 struct {
511 u64 lbr_format:6;
512 u64 pebs_trap:1;
513 u64 pebs_arch_reg:1;
514 u64 pebs_format:4;
515 u64 smm_freeze:1;
516 /*
517 * PMU supports separate counter range for writing
518 * values > 32bit.
519 */
520 u64 full_width_write:1;
521 u64 pebs_baseline:1;
522 u64 pebs_metrics_available:1;
523 u64 pebs_output_pt_available:1;
524 };
525 u64 capabilities;
526 };
527
528 struct x86_pmu_quirk {
529 struct x86_pmu_quirk *next;
530 void (*func)(void);
531 };
532
533 union x86_pmu_config {
534 struct {
535 u64 event:8,
536 umask:8,
537 usr:1,
538 os:1,
539 edge:1,
540 pc:1,
541 interrupt:1,
542 __reserved1:1,
543 en:1,
544 inv:1,
545 cmask:8,
546 event2:4,
547 __reserved2:4,
548 go:1,
549 ho:1;
550 } bits;
551 u64 value;
552 };
553
554 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
555
556 enum {
557 x86_lbr_exclusive_lbr,
558 x86_lbr_exclusive_bts,
559 x86_lbr_exclusive_pt,
560 x86_lbr_exclusive_max,
561 };
562
563 /*
564 * struct x86_pmu - generic x86 pmu
565 */
566 struct x86_pmu {
567 /*
568 * Generic x86 PMC bits
569 */
570 const char *name;
571 int version;
572 int (*handle_irq)(struct pt_regs *);
573 void (*disable_all)(void);
574 void (*enable_all)(int added);
575 void (*enable)(struct perf_event *);
576 void (*disable)(struct perf_event *);
577 void (*add)(struct perf_event *);
578 void (*del)(struct perf_event *);
579 void (*read)(struct perf_event *event);
580 int (*hw_config)(struct perf_event *event);
581 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
582 unsigned eventsel;
583 unsigned perfctr;
584 int (*addr_offset)(int index, bool eventsel);
585 int (*rdpmc_index)(int index);
586 u64 (*event_map)(int);
587 int max_events;
588 int num_counters;
589 int num_counters_fixed;
590 int cntval_bits;
591 u64 cntval_mask;
592 union {
593 unsigned long events_maskl;
594 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
595 };
596 int events_mask_len;
597 int apic;
598 u64 max_period;
599 struct event_constraint *
600 (*get_event_constraints)(struct cpu_hw_events *cpuc,
601 int idx,
602 struct perf_event *event);
603
604 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
605 struct perf_event *event);
606
607 void (*start_scheduling)(struct cpu_hw_events *cpuc);
608
609 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr);
610
611 void (*stop_scheduling)(struct cpu_hw_events *cpuc);
612
613 struct event_constraint *event_constraints;
614 struct x86_pmu_quirk *quirks;
615 int perfctr_second_write;
616 u64 (*limit_period)(struct perf_event *event, u64 l);
617
618 /* PMI handler bits */
619 unsigned int late_ack :1,
620 counter_freezing :1;
621 /*
622 * sysfs attrs
623 */
624 int attr_rdpmc_broken;
625 int attr_rdpmc;
626 struct attribute **format_attrs;
627
628 ssize_t (*events_sysfs_show)(char *page, u64 config);
629 const struct attribute_group **attr_update;
630
631 unsigned long attr_freeze_on_smi;
632
633 /*
634 * CPU Hotplug hooks
635 */
636 int (*cpu_prepare)(int cpu);
637 void (*cpu_starting)(int cpu);
638 void (*cpu_dying)(int cpu);
639 void (*cpu_dead)(int cpu);
640
641 void (*check_microcode)(void);
642 void (*sched_task)(struct perf_event_context *ctx,
643 bool sched_in);
644
645 /*
646 * Intel Arch Perfmon v2+
647 */
648 u64 intel_ctrl;
649 union perf_capabilities intel_cap;
650
651 /*
652 * Intel DebugStore bits
653 */
654 unsigned int bts :1,
655 bts_active :1,
656 pebs :1,
657 pebs_active :1,
658 pebs_broken :1,
659 pebs_prec_dist :1,
660 pebs_no_tlb :1,
661 pebs_no_isolation :1;
662 int pebs_record_size;
663 int pebs_buffer_size;
664 int max_pebs_events;
665 void (*drain_pebs)(struct pt_regs *regs);
666 struct event_constraint *pebs_constraints;
667 void (*pebs_aliases)(struct perf_event *event);
668 unsigned long large_pebs_flags;
669 u64 rtm_abort_event;
670
671 /*
672 * Intel LBR
673 */
674 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
675 int lbr_nr; /* hardware stack size */
676 u64 lbr_sel_mask; /* LBR_SELECT valid bits */
677 const int *lbr_sel_map; /* lbr_select mappings */
678 bool lbr_double_abort; /* duplicated lbr aborts */
679 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
680
681 /*
682 * Intel PT/LBR/BTS are exclusive
683 */
684 atomic_t lbr_exclusive[x86_lbr_exclusive_max];
685
686 /*
687 * AMD bits
688 */
689 unsigned int amd_nb_constraints : 1;
690
691 /*
692 * Extra registers for events
693 */
694 struct extra_reg *extra_regs;
695 unsigned int flags;
696
697 /*
698 * Intel host/guest support (KVM)
699 */
700 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
701
702 /*
703 * Check period value for PERF_EVENT_IOC_PERIOD ioctl.
704 */
705 int (*check_period) (struct perf_event *event, u64 period);
706
707 int (*aux_output_match) (struct perf_event *event);
708 };
709
710 struct x86_perf_task_context {
711 u64 lbr_from[MAX_LBR_ENTRIES];
712 u64 lbr_to[MAX_LBR_ENTRIES];
713 u64 lbr_info[MAX_LBR_ENTRIES];
714 int tos;
715 int valid_lbrs;
716 int lbr_callstack_users;
717 int lbr_stack_state;
718 int log_id;
719 };
720
721 #define x86_add_quirk(func_) \
722 do { \
723 static struct x86_pmu_quirk __quirk __initdata = { \
724 .func = func_, \
725 }; \
726 __quirk.next = x86_pmu.quirks; \
727 x86_pmu.quirks = &__quirk; \
728 } while (0)
729
730 /*
731 * x86_pmu flags
732 */
733 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */
734 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */
735 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */
736 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */
737 #define PMU_FL_PEBS_ALL 0x10 /* all events are valid PEBS events */
738 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */
739 #define PMU_FL_PAIR 0x40 /* merge counters for large incr. events */
740
741 #define EVENT_VAR(_id) event_attr_##_id
742 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
743
744 #define EVENT_ATTR(_name, _id) \
745 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
746 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
747 .id = PERF_COUNT_HW_##_id, \
748 .event_str = NULL, \
749 };
750
751 #define EVENT_ATTR_STR(_name, v, str) \
752 static struct perf_pmu_events_attr event_attr_##v = { \
753 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
754 .id = 0, \
755 .event_str = str, \
756 };
757
758 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \
759 static struct perf_pmu_events_ht_attr event_attr_##v = { \
760 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\
761 .id = 0, \
762 .event_str_noht = noht, \
763 .event_str_ht = ht, \
764 }
765
766 struct pmu *x86_get_pmu(void);
767 extern struct x86_pmu x86_pmu __read_mostly;
768
x86_pmu_has_lbr_callstack(void)769 static inline bool x86_pmu_has_lbr_callstack(void)
770 {
771 return x86_pmu.lbr_sel_map &&
772 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0;
773 }
774
775 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
776
777 int x86_perf_event_set_period(struct perf_event *event);
778
779 /*
780 * Generalized hw caching related hw_event table, filled
781 * in on a per model basis. A value of 0 means
782 * 'not supported', -1 means 'hw_event makes no sense on
783 * this CPU', any other value means the raw hw_event
784 * ID.
785 */
786
787 #define C(x) PERF_COUNT_HW_CACHE_##x
788
789 extern u64 __read_mostly hw_cache_event_ids
790 [PERF_COUNT_HW_CACHE_MAX]
791 [PERF_COUNT_HW_CACHE_OP_MAX]
792 [PERF_COUNT_HW_CACHE_RESULT_MAX];
793 extern u64 __read_mostly hw_cache_extra_regs
794 [PERF_COUNT_HW_CACHE_MAX]
795 [PERF_COUNT_HW_CACHE_OP_MAX]
796 [PERF_COUNT_HW_CACHE_RESULT_MAX];
797
798 u64 x86_perf_event_update(struct perf_event *event);
799
x86_pmu_config_addr(int index)800 static inline unsigned int x86_pmu_config_addr(int index)
801 {
802 return x86_pmu.eventsel + (x86_pmu.addr_offset ?
803 x86_pmu.addr_offset(index, true) : index);
804 }
805
x86_pmu_event_addr(int index)806 static inline unsigned int x86_pmu_event_addr(int index)
807 {
808 return x86_pmu.perfctr + (x86_pmu.addr_offset ?
809 x86_pmu.addr_offset(index, false) : index);
810 }
811
x86_pmu_rdpmc_index(int index)812 static inline int x86_pmu_rdpmc_index(int index)
813 {
814 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
815 }
816
817 int x86_add_exclusive(unsigned int what);
818
819 void x86_del_exclusive(unsigned int what);
820
821 int x86_reserve_hardware(void);
822
823 void x86_release_hardware(void);
824
825 int x86_pmu_max_precise(void);
826
827 void hw_perf_lbr_event_destroy(struct perf_event *event);
828
829 int x86_setup_perfctr(struct perf_event *event);
830
831 int x86_pmu_hw_config(struct perf_event *event);
832
833 void x86_pmu_disable_all(void);
834
__x86_pmu_enable_event(struct hw_perf_event * hwc,u64 enable_mask)835 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
836 u64 enable_mask)
837 {
838 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
839
840 if (hwc->extra_reg.reg)
841 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
842 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
843 }
844
845 void x86_pmu_enable_all(int added);
846
847 int perf_assign_events(struct event_constraint **constraints, int n,
848 int wmin, int wmax, int gpmax, int *assign);
849 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
850
851 void x86_pmu_stop(struct perf_event *event, int flags);
852
x86_pmu_disable_event(struct perf_event * event)853 static inline void x86_pmu_disable_event(struct perf_event *event)
854 {
855 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
856 struct hw_perf_event *hwc = &event->hw;
857
858 wrmsrl(hwc->config_base, hwc->config & ~disable_mask);
859 }
860
861 void x86_pmu_enable_event(struct perf_event *event);
862
863 int x86_pmu_handle_irq(struct pt_regs *regs);
864
865 extern struct event_constraint emptyconstraint;
866
867 extern struct event_constraint unconstrained;
868
kernel_ip(unsigned long ip)869 static inline bool kernel_ip(unsigned long ip)
870 {
871 #ifdef CONFIG_X86_32
872 return ip > PAGE_OFFSET;
873 #else
874 return (long)ip < 0;
875 #endif
876 }
877
878 /*
879 * Not all PMUs provide the right context information to place the reported IP
880 * into full context. Specifically segment registers are typically not
881 * supplied.
882 *
883 * Assuming the address is a linear address (it is for IBS), we fake the CS and
884 * vm86 mode using the known zero-based code segment and 'fix up' the registers
885 * to reflect this.
886 *
887 * Intel PEBS/LBR appear to typically provide the effective address, nothing
888 * much we can do about that but pray and treat it like a linear address.
889 */
set_linear_ip(struct pt_regs * regs,unsigned long ip)890 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
891 {
892 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
893 if (regs->flags & X86_VM_MASK)
894 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
895 regs->ip = ip;
896 }
897
898 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
899 ssize_t intel_event_sysfs_show(char *page, u64 config);
900
901 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
902 char *page);
903 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
904 char *page);
905
906 #ifdef CONFIG_CPU_SUP_AMD
907
908 int amd_pmu_init(void);
909
910 #else /* CONFIG_CPU_SUP_AMD */
911
amd_pmu_init(void)912 static inline int amd_pmu_init(void)
913 {
914 return 0;
915 }
916
917 #endif /* CONFIG_CPU_SUP_AMD */
918
is_pebs_pt(struct perf_event * event)919 static inline int is_pebs_pt(struct perf_event *event)
920 {
921 return !!(event->hw.flags & PERF_X86_EVENT_PEBS_VIA_PT);
922 }
923
924 #ifdef CONFIG_CPU_SUP_INTEL
925
intel_pmu_has_bts_period(struct perf_event * event,u64 period)926 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period)
927 {
928 struct hw_perf_event *hwc = &event->hw;
929 unsigned int hw_event, bts_event;
930
931 if (event->attr.freq)
932 return false;
933
934 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
935 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
936
937 return hw_event == bts_event && period == 1;
938 }
939
intel_pmu_has_bts(struct perf_event * event)940 static inline bool intel_pmu_has_bts(struct perf_event *event)
941 {
942 struct hw_perf_event *hwc = &event->hw;
943
944 return intel_pmu_has_bts_period(event, hwc->sample_period);
945 }
946
947 int intel_pmu_save_and_restart(struct perf_event *event);
948
949 struct event_constraint *
950 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
951 struct perf_event *event);
952
953 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu);
954 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc);
955
956 int intel_pmu_init(void);
957
958 void init_debug_store_on_cpu(int cpu);
959
960 void fini_debug_store_on_cpu(int cpu);
961
962 void release_ds_buffers(void);
963
964 void reserve_ds_buffers(void);
965
966 extern struct event_constraint bts_constraint;
967
968 void intel_pmu_enable_bts(u64 config);
969
970 void intel_pmu_disable_bts(void);
971
972 int intel_pmu_drain_bts_buffer(void);
973
974 extern struct event_constraint intel_core2_pebs_event_constraints[];
975
976 extern struct event_constraint intel_atom_pebs_event_constraints[];
977
978 extern struct event_constraint intel_slm_pebs_event_constraints[];
979
980 extern struct event_constraint intel_glm_pebs_event_constraints[];
981
982 extern struct event_constraint intel_glp_pebs_event_constraints[];
983
984 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
985
986 extern struct event_constraint intel_westmere_pebs_event_constraints[];
987
988 extern struct event_constraint intel_snb_pebs_event_constraints[];
989
990 extern struct event_constraint intel_ivb_pebs_event_constraints[];
991
992 extern struct event_constraint intel_hsw_pebs_event_constraints[];
993
994 extern struct event_constraint intel_bdw_pebs_event_constraints[];
995
996 extern struct event_constraint intel_skl_pebs_event_constraints[];
997
998 extern struct event_constraint intel_icl_pebs_event_constraints[];
999
1000 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
1001
1002 void intel_pmu_pebs_add(struct perf_event *event);
1003
1004 void intel_pmu_pebs_del(struct perf_event *event);
1005
1006 void intel_pmu_pebs_enable(struct perf_event *event);
1007
1008 void intel_pmu_pebs_disable(struct perf_event *event);
1009
1010 void intel_pmu_pebs_enable_all(void);
1011
1012 void intel_pmu_pebs_disable_all(void);
1013
1014 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in);
1015
1016 void intel_pmu_auto_reload_read(struct perf_event *event);
1017
1018 void intel_pmu_store_pebs_lbrs(struct pebs_lbr *lbr);
1019
1020 void intel_ds_init(void);
1021
1022 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in);
1023
1024 u64 lbr_from_signext_quirk_wr(u64 val);
1025
1026 void intel_pmu_lbr_reset(void);
1027
1028 void intel_pmu_lbr_add(struct perf_event *event);
1029
1030 void intel_pmu_lbr_del(struct perf_event *event);
1031
1032 void intel_pmu_lbr_enable_all(bool pmi);
1033
1034 void intel_pmu_lbr_disable_all(void);
1035
1036 void intel_pmu_lbr_read(void);
1037
1038 void intel_pmu_lbr_init_core(void);
1039
1040 void intel_pmu_lbr_init_nhm(void);
1041
1042 void intel_pmu_lbr_init_atom(void);
1043
1044 void intel_pmu_lbr_init_slm(void);
1045
1046 void intel_pmu_lbr_init_snb(void);
1047
1048 void intel_pmu_lbr_init_hsw(void);
1049
1050 void intel_pmu_lbr_init_skl(void);
1051
1052 void intel_pmu_lbr_init_knl(void);
1053
1054 void intel_pmu_pebs_data_source_nhm(void);
1055
1056 void intel_pmu_pebs_data_source_skl(bool pmem);
1057
1058 int intel_pmu_setup_lbr_filter(struct perf_event *event);
1059
1060 void intel_pt_interrupt(void);
1061
1062 int intel_bts_interrupt(void);
1063
1064 void intel_bts_enable_local(void);
1065
1066 void intel_bts_disable_local(void);
1067
1068 int p4_pmu_init(void);
1069
1070 int p6_pmu_init(void);
1071
1072 int knc_pmu_init(void);
1073
is_ht_workaround_enabled(void)1074 static inline int is_ht_workaround_enabled(void)
1075 {
1076 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED);
1077 }
1078
1079 #else /* CONFIG_CPU_SUP_INTEL */
1080
reserve_ds_buffers(void)1081 static inline void reserve_ds_buffers(void)
1082 {
1083 }
1084
release_ds_buffers(void)1085 static inline void release_ds_buffers(void)
1086 {
1087 }
1088
intel_pmu_init(void)1089 static inline int intel_pmu_init(void)
1090 {
1091 return 0;
1092 }
1093
intel_cpuc_prepare(struct cpu_hw_events * cpuc,int cpu)1094 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
1095 {
1096 return 0;
1097 }
1098
intel_cpuc_finish(struct cpu_hw_events * cpuc)1099 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc)
1100 {
1101 }
1102
is_ht_workaround_enabled(void)1103 static inline int is_ht_workaround_enabled(void)
1104 {
1105 return 0;
1106 }
1107 #endif /* CONFIG_CPU_SUP_INTEL */
1108